1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 *
4 * Copyright (C) 2015 Nikolay Martynov <mar.kolya@gmail.com>
5 * Copyright (C) 2015 John Crispin <john@phrozen.org>
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/slab.h>
11 #include <linux/sys_soc.h>
12 #include <linux/memblock.h>
13
14 #include <asm/bootinfo.h>
15 #include <asm/mipsregs.h>
16 #include <asm/smp-ops.h>
17 #include <asm/mips-cps.h>
18 #include <asm/mach-ralink/ralink_regs.h>
19 #include <asm/mach-ralink/mt7621.h>
20
21 #include "common.h"
22
23 static void *detect_magic __initdata = detect_memory_region;
24
mips_cpc_default_phys_base(void)25 phys_addr_t mips_cpc_default_phys_base(void)
26 {
27 panic("Cannot detect cpc address");
28 }
29
mt7621_memory_detect(void)30 static void __init mt7621_memory_detect(void)
31 {
32 void *dm = &detect_magic;
33 phys_addr_t size;
34
35 for (size = 32 * SZ_1M; size < 256 * SZ_1M; size <<= 1) {
36 if (!__builtin_memcmp(dm, dm + size, sizeof(detect_magic)))
37 break;
38 }
39
40 if ((size == 256 * SZ_1M) &&
41 (CPHYSADDR(dm + size) < MT7621_LOWMEM_MAX_SIZE) &&
42 __builtin_memcmp(dm, dm + size, sizeof(detect_magic))) {
43 memblock_add(MT7621_LOWMEM_BASE, MT7621_LOWMEM_MAX_SIZE);
44 memblock_add(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE);
45 } else {
46 memblock_add(MT7621_LOWMEM_BASE, size);
47 }
48 }
49
ralink_of_remap(void)50 void __init ralink_of_remap(void)
51 {
52 rt_sysc_membase = plat_of_remap_node("mediatek,mt7621-sysc");
53 rt_memc_membase = plat_of_remap_node("mediatek,mt7621-memc");
54
55 if (!rt_sysc_membase || !rt_memc_membase)
56 panic("Failed to remap core resources");
57 }
58
soc_dev_init(struct ralink_soc_info * soc_info,u32 rev)59 static void soc_dev_init(struct ralink_soc_info *soc_info, u32 rev)
60 {
61 struct soc_device *soc_dev;
62 struct soc_device_attribute *soc_dev_attr;
63
64 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
65 if (!soc_dev_attr)
66 return;
67
68 soc_dev_attr->soc_id = "mt7621";
69 soc_dev_attr->family = "Ralink";
70
71 if (((rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK) == 1 &&
72 (rev & CHIP_REV_ECO_MASK) == 1)
73 soc_dev_attr->revision = "E2";
74 else
75 soc_dev_attr->revision = "E1";
76
77 soc_dev_attr->data = soc_info;
78
79 soc_dev = soc_device_register(soc_dev_attr);
80 if (IS_ERR(soc_dev)) {
81 kfree(soc_dev_attr);
82 return;
83 }
84 }
85
prom_soc_init(struct ralink_soc_info * soc_info)86 void __init prom_soc_init(struct ralink_soc_info *soc_info)
87 {
88 void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
89 unsigned char *name = NULL;
90 u32 n0;
91 u32 n1;
92 u32 rev;
93
94 /* Early detection of CMP support */
95 mips_cm_probe();
96 mips_cpc_probe();
97
98 if (mips_cps_numiocu(0)) {
99 /*
100 * mips_cm_probe() wipes out bootloader
101 * config for CM regions and we have to configure them
102 * again. This SoC cannot talk to pamlbus devices
103 * witout proper iocu region set up.
104 *
105 * FIXME: it would be better to do this with values
106 * from DT, but we need this very early because
107 * without this we cannot talk to pretty much anything
108 * including serial.
109 */
110 write_gcr_reg0_base(MT7621_PALMBUS_BASE);
111 write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE |
112 CM_GCR_REGn_MASK_CMTGT_IOCU0);
113 __sync();
114 }
115
116 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
117 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
118
119 if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
120 name = "MT7621";
121 soc_info->compatible = "mediatek,mt7621-soc";
122 } else {
123 panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
124 }
125 ralink_soc = MT762X_SOC_MT7621AT;
126 rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
127
128 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
129 "MediaTek %s ver:%u eco:%u",
130 name,
131 (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
132 (rev & CHIP_REV_ECO_MASK));
133
134 soc_info->mem_detect = mt7621_memory_detect;
135
136 soc_dev_init(soc_info, rev);
137
138 if (!register_cps_smp_ops())
139 return;
140 if (!register_cmp_smp_ops())
141 return;
142 if (!register_vsmp_smp_ops())
143 return;
144 }
145