1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  *    Initial setup-routines for HP 9000 based hardware.
4  *
5  *    Copyright (C) 1991, 1992, 1995  Linus Torvalds
6  *    Modifications for PA-RISC (C) 1999-2008 Helge Deller <deller@gmx.de>
7  *    Modifications copyright 1999 SuSE GmbH (Philipp Rumpf)
8  *    Modifications copyright 2000 Martin K. Petersen <mkp@mkp.net>
9  *    Modifications copyright 2000 Philipp Rumpf <prumpf@tux.org>
10  *    Modifications copyright 2001 Ryan Bradetich <rbradetich@uswest.net>
11  *
12  *    Initial PA-RISC Version: 04-23-1999 by Helge Deller
13  */
14 #include <linux/delay.h>
15 #include <linux/init.h>
16 #include <linux/mm.h>
17 #include <linux/module.h>
18 #include <linux/seq_file.h>
19 #include <linux/random.h>
20 #include <linux/slab.h>
21 #include <linux/cpu.h>
22 #include <asm/param.h>
23 #include <asm/cache.h>
24 #include <asm/hardware.h>	/* for register_parisc_driver() stuff */
25 #include <asm/processor.h>
26 #include <asm/page.h>
27 #include <asm/pdc.h>
28 #include <asm/pdcpat.h>
29 #include <asm/irq.h>		/* for struct irq_region */
30 #include <asm/parisc-device.h>
31 
32 struct system_cpuinfo_parisc boot_cpu_data __ro_after_init;
33 EXPORT_SYMBOL(boot_cpu_data);
34 #ifdef CONFIG_PA8X00
35 int _parisc_requires_coherency __ro_after_init;
36 EXPORT_SYMBOL(_parisc_requires_coherency);
37 #endif
38 
39 DEFINE_PER_CPU(struct cpuinfo_parisc, cpu_data);
40 
41 /*
42 **  	PARISC CPU driver - claim "device" and initialize CPU data structures.
43 **
44 ** Consolidate per CPU initialization into (mostly) one module.
45 ** Monarch CPU will initialize boot_cpu_data which shouldn't
46 ** change once the system has booted.
47 **
48 ** The callback *should* do per-instance initialization of
49 ** everything including the monarch. "Per CPU" init code in
50 ** setup.c:start_parisc() has migrated here and start_parisc()
51 ** will call register_parisc_driver(&cpu_driver) before calling do_inventory().
52 **
53 ** The goal of consolidating CPU initialization into one place is
54 ** to make sure all CPUs get initialized the same way.
55 ** The code path not shared is how PDC hands control of the CPU to the OS.
56 ** The initialization of OS data structures is the same (done below).
57 */
58 
59 /**
60  * init_cpu_profiler - enable/setup per cpu profiling hooks.
61  * @cpunum: The processor instance.
62  *
63  * FIXME: doesn't do much yet...
64  */
65 static void
init_percpu_prof(unsigned long cpunum)66 init_percpu_prof(unsigned long cpunum)
67 {
68 }
69 
70 
71 /**
72  * processor_probe - Determine if processor driver should claim this device.
73  * @dev: The device which has been found.
74  *
75  * Determine if processor driver should claim this chip (return 0) or not
76  * (return 1).  If so, initialize the chip and tell other partners in crime
77  * they have work to do.
78  */
processor_probe(struct parisc_device * dev)79 static int __init processor_probe(struct parisc_device *dev)
80 {
81 	unsigned long txn_addr;
82 	unsigned long cpuid;
83 	struct cpuinfo_parisc *p;
84 	struct pdc_pat_cpu_num cpu_info = { };
85 
86 #ifdef CONFIG_SMP
87 	if (num_online_cpus() >= nr_cpu_ids) {
88 		printk(KERN_INFO "num_online_cpus() >= nr_cpu_ids\n");
89 		return 1;
90 	}
91 #else
92 	if (boot_cpu_data.cpu_count > 0) {
93 		printk(KERN_INFO "CONFIG_SMP=n  ignoring additional CPUs\n");
94 		return 1;
95 	}
96 #endif
97 
98 	/* logical CPU ID and update global counter
99 	 * May get overwritten by PAT code.
100 	 */
101 	cpuid = boot_cpu_data.cpu_count;
102 	txn_addr = dev->hpa.start;	/* for legacy PDC */
103 	cpu_info.cpu_num = cpu_info.cpu_loc = cpuid;
104 
105 #ifdef CONFIG_64BIT
106 	if (is_pdc_pat()) {
107 		ulong status;
108 		unsigned long bytecnt;
109 	        pdc_pat_cell_mod_maddr_block_t *pa_pdc_cell;
110 
111 		pa_pdc_cell = kmalloc(sizeof (*pa_pdc_cell), GFP_KERNEL);
112 		if (!pa_pdc_cell)
113 			panic("couldn't allocate memory for PDC_PAT_CELL!");
114 
115 		status = pdc_pat_cell_module(&bytecnt, dev->pcell_loc,
116 			dev->mod_index, PA_VIEW, pa_pdc_cell);
117 
118 		BUG_ON(PDC_OK != status);
119 
120 		/* verify it's the same as what do_pat_inventory() found */
121 		BUG_ON(dev->mod_info != pa_pdc_cell->mod_info);
122 		BUG_ON(dev->pmod_loc != pa_pdc_cell->mod_location);
123 
124 		txn_addr = pa_pdc_cell->mod[0];   /* id_eid for IO sapic */
125 
126 		kfree(pa_pdc_cell);
127 
128 		/* get the cpu number */
129 		status = pdc_pat_cpu_get_number(&cpu_info, dev->hpa.start);
130 		BUG_ON(PDC_OK != status);
131 
132 		pr_info("Logical CPU #%lu is physical cpu #%lu at location "
133 			"0x%lx with hpa %pa\n",
134 			cpuid, cpu_info.cpu_num, cpu_info.cpu_loc,
135 			&dev->hpa.start);
136 
137 #undef USE_PAT_CPUID
138 #ifdef USE_PAT_CPUID
139 /* We need contiguous numbers for cpuid. Firmware's notion
140  * of cpuid is for physical CPUs and we just don't care yet.
141  * We'll care when we need to query PAT PDC about a CPU *after*
142  * boot time (ie shutdown a CPU from an OS perspective).
143  */
144 		if (cpu_info.cpu_num >= NR_CPUS) {
145 			printk(KERN_WARNING "IGNORING CPU at %pa,"
146 				" cpu_slot_id > NR_CPUS"
147 				" (%ld > %d)\n",
148 				&dev->hpa.start, cpu_info.cpu_num, NR_CPUS);
149 			/* Ignore CPU since it will only crash */
150 			boot_cpu_data.cpu_count--;
151 			return 1;
152 		} else {
153 			cpuid = cpu_info.cpu_num;
154 		}
155 #endif
156 	}
157 #endif
158 
159 	p = &per_cpu(cpu_data, cpuid);
160 	boot_cpu_data.cpu_count++;
161 
162 	/* initialize counters - CPU 0 gets it_value set in time_init() */
163 	if (cpuid)
164 		memset(p, 0, sizeof(struct cpuinfo_parisc));
165 
166 	p->dev = dev;		/* Save IODC data in case we need it */
167 	p->hpa = dev->hpa.start;	/* save CPU hpa */
168 	p->cpuid = cpuid;	/* save CPU id */
169 	p->txn_addr = txn_addr;	/* save CPU IRQ address */
170 	p->cpu_num = cpu_info.cpu_num;
171 	p->cpu_loc = cpu_info.cpu_loc;
172 
173 	store_cpu_topology(cpuid);
174 
175 #ifdef CONFIG_SMP
176 	/*
177 	** FIXME: review if any other initialization is clobbered
178 	**	  for boot_cpu by the above memset().
179 	*/
180 	init_percpu_prof(cpuid);
181 #endif
182 
183 	/*
184 	** CONFIG_SMP: init_smp_config() will attempt to get CPUs into
185 	** OS control. RENDEZVOUS is the default state - see mem_set above.
186 	**	p->state = STATE_RENDEZVOUS;
187 	*/
188 
189 #if 0
190 	/* CPU 0 IRQ table is statically allocated/initialized */
191 	if (cpuid) {
192 		struct irqaction actions[];
193 
194 		/*
195 		** itimer and ipi IRQ handlers are statically initialized in
196 		** arch/parisc/kernel/irq.c. ie Don't need to register them.
197 		*/
198 		actions = kmalloc(sizeof(struct irqaction)*MAX_CPU_IRQ, GFP_ATOMIC);
199 		if (!actions) {
200 			/* not getting it's own table, share with monarch */
201 			actions = cpu_irq_actions[0];
202 		}
203 
204 		cpu_irq_actions[cpuid] = actions;
205 	}
206 #endif
207 
208 	/*
209 	 * Bring this CPU up now! (ignore bootstrap cpuid == 0)
210 	 */
211 #ifdef CONFIG_SMP
212 	if (cpuid) {
213 		set_cpu_present(cpuid, true);
214 		add_cpu(cpuid);
215 	}
216 #endif
217 
218 	return 0;
219 }
220 
221 /**
222  * collect_boot_cpu_data - Fill the boot_cpu_data structure.
223  *
224  * This function collects and stores the generic processor information
225  * in the boot_cpu_data structure.
226  */
collect_boot_cpu_data(void)227 void __init collect_boot_cpu_data(void)
228 {
229 	unsigned long cr16_seed;
230 	char orig_prod_num[64], current_prod_num[64], serial_no[64];
231 
232 	memset(&boot_cpu_data, 0, sizeof(boot_cpu_data));
233 
234 	cr16_seed = get_cycles();
235 	add_device_randomness(&cr16_seed, sizeof(cr16_seed));
236 
237 	boot_cpu_data.cpu_hz = 100 * PAGE0->mem_10msec; /* Hz of this PARISC */
238 
239 	/* get CPU-Model Information... */
240 #define p ((unsigned long *)&boot_cpu_data.pdc.model)
241 	if (pdc_model_info(&boot_cpu_data.pdc.model) == PDC_OK) {
242 		printk(KERN_INFO
243 			"model %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
244 			p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7], p[8]);
245 
246 		add_device_randomness(&boot_cpu_data.pdc.model,
247 			sizeof(boot_cpu_data.pdc.model));
248 	}
249 #undef p
250 
251 	if (pdc_model_versions(&boot_cpu_data.pdc.versions, 0) == PDC_OK) {
252 		printk(KERN_INFO "vers  %08lx\n",
253 			boot_cpu_data.pdc.versions);
254 
255 		add_device_randomness(&boot_cpu_data.pdc.versions,
256 			sizeof(boot_cpu_data.pdc.versions));
257 	}
258 
259 	if (pdc_model_cpuid(&boot_cpu_data.pdc.cpuid) == PDC_OK) {
260 		printk(KERN_INFO "CPUID vers %ld rev %ld (0x%08lx)\n",
261 			(boot_cpu_data.pdc.cpuid >> 5) & 127,
262 			boot_cpu_data.pdc.cpuid & 31,
263 			boot_cpu_data.pdc.cpuid);
264 
265 		add_device_randomness(&boot_cpu_data.pdc.cpuid,
266 			sizeof(boot_cpu_data.pdc.cpuid));
267 	}
268 
269 	if (pdc_model_capabilities(&boot_cpu_data.pdc.capabilities) == PDC_OK)
270 		printk(KERN_INFO "capabilities 0x%lx\n",
271 			boot_cpu_data.pdc.capabilities);
272 
273 	if (pdc_model_sysmodel(boot_cpu_data.pdc.sys_model_name) == PDC_OK)
274 		printk(KERN_INFO "model %s\n",
275 			boot_cpu_data.pdc.sys_model_name);
276 
277 	dump_stack_set_arch_desc("%s", boot_cpu_data.pdc.sys_model_name);
278 
279 	boot_cpu_data.hversion =  boot_cpu_data.pdc.model.hversion;
280 	boot_cpu_data.sversion =  boot_cpu_data.pdc.model.sversion;
281 
282 	boot_cpu_data.cpu_type = parisc_get_cpu_type(boot_cpu_data.hversion);
283 	boot_cpu_data.cpu_name = cpu_name_version[boot_cpu_data.cpu_type][0];
284 	boot_cpu_data.family_name = cpu_name_version[boot_cpu_data.cpu_type][1];
285 
286 #ifdef CONFIG_PA8X00
287 	_parisc_requires_coherency = (boot_cpu_data.cpu_type == mako) ||
288 				(boot_cpu_data.cpu_type == mako2);
289 #endif
290 
291 	if (pdc_model_platform_info(orig_prod_num, current_prod_num, serial_no) == PDC_OK) {
292 		printk(KERN_INFO "product %s, original product %s, S/N: %s\n",
293 			current_prod_num[0] ? current_prod_num : "n/a",
294 			orig_prod_num, serial_no);
295 		add_device_randomness(orig_prod_num, strlen(orig_prod_num));
296 		add_device_randomness(current_prod_num, strlen(current_prod_num));
297 		add_device_randomness(serial_no, strlen(serial_no));
298 	}
299 }
300 
301 
302 /**
303  * init_per_cpu - Handle individual processor initializations.
304  * @cpunum: logical processor number.
305  *
306  * This function handles initialization for *every* CPU
307  * in the system:
308  *
309  * o Set "default" CPU width for trap handlers
310  *
311  * o Enable FP coprocessor
312  *   REVISIT: this could be done in the "code 22" trap handler.
313  *	(frowands idea - that way we know which processes need FP
314  *	registers saved on the interrupt stack.)
315  *   NEWS FLASH: wide kernels need FP coprocessor enabled to handle
316  *	formatted printing of %lx for example (double divides I think)
317  *
318  * o Enable CPU profiling hooks.
319  */
init_per_cpu(int cpunum)320 int __init init_per_cpu(int cpunum)
321 {
322 	int ret;
323 	struct pdc_coproc_cfg coproc_cfg;
324 
325 	set_firmware_width();
326 	ret = pdc_coproc_cfg(&coproc_cfg);
327 
328 	store_cpu_topology(cpunum);
329 
330 	if(ret >= 0 && coproc_cfg.ccr_functional) {
331 		mtctl(coproc_cfg.ccr_functional, 10);  /* 10 == Coprocessor Control Reg */
332 
333 		/* FWIW, FP rev/model is a more accurate way to determine
334 		** CPU type. CPU rev/model has some ambiguous cases.
335 		*/
336 		per_cpu(cpu_data, cpunum).fp_rev = coproc_cfg.revision;
337 		per_cpu(cpu_data, cpunum).fp_model = coproc_cfg.model;
338 
339 		if (cpunum == 0)
340 			printk(KERN_INFO  "FP[%d] enabled: Rev %ld Model %ld\n",
341 				cpunum, coproc_cfg.revision, coproc_cfg.model);
342 
343 		/*
344 		** store status register to stack (hopefully aligned)
345 		** and clear the T-bit.
346 		*/
347 		asm volatile ("fstd    %fr0,8(%sp)");
348 
349 	} else {
350 		printk(KERN_WARNING  "WARNING: No FP CoProcessor?!"
351 			" (coproc_cfg.ccr_functional == 0x%lx, expected 0xc0)\n"
352 #ifdef CONFIG_64BIT
353 			"Halting Machine - FP required\n"
354 #endif
355 			, coproc_cfg.ccr_functional);
356 #ifdef CONFIG_64BIT
357 		mdelay(100);	/* previous chars get pushed to console */
358 		panic("FP CoProc not reported");
359 #endif
360 	}
361 
362 	/* FUTURE: Enable Performance Monitor : ccr bit 0x20 */
363 	init_percpu_prof(cpunum);
364 
365 	return ret;
366 }
367 
368 /*
369  * Display CPU info for all CPUs.
370  */
371 int
show_cpuinfo(struct seq_file * m,void * v)372 show_cpuinfo (struct seq_file *m, void *v)
373 {
374 	unsigned long cpu;
375 
376 	for_each_online_cpu(cpu) {
377 		const struct cpuinfo_parisc *cpuinfo = &per_cpu(cpu_data, cpu);
378 #ifdef CONFIG_SMP
379 		if (0 == cpuinfo->hpa)
380 			continue;
381 #endif
382 		seq_printf(m, "processor\t: %lu\n"
383 				"cpu family\t: PA-RISC %s\n",
384 				 cpu, boot_cpu_data.family_name);
385 
386 		seq_printf(m, "cpu\t\t: %s\n",  boot_cpu_data.cpu_name );
387 
388 		/* cpu MHz */
389 		seq_printf(m, "cpu MHz\t\t: %d.%06d\n",
390 				 boot_cpu_data.cpu_hz / 1000000,
391 				 boot_cpu_data.cpu_hz % 1000000  );
392 
393 #ifdef CONFIG_PARISC_CPU_TOPOLOGY
394 		seq_printf(m, "physical id\t: %d\n",
395 				topology_physical_package_id(cpu));
396 		seq_printf(m, "siblings\t: %d\n",
397 				cpumask_weight(topology_core_cpumask(cpu)));
398 		seq_printf(m, "core id\t\t: %d\n", topology_core_id(cpu));
399 #endif
400 
401 		seq_printf(m, "capabilities\t:");
402 		if (boot_cpu_data.pdc.capabilities & PDC_MODEL_OS32)
403 			seq_puts(m, " os32");
404 		if (boot_cpu_data.pdc.capabilities & PDC_MODEL_OS64)
405 			seq_puts(m, " os64");
406 		if (boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC)
407 			seq_puts(m, " iopdir_fdc");
408 		switch (boot_cpu_data.pdc.capabilities & PDC_MODEL_NVA_MASK) {
409 		case PDC_MODEL_NVA_SUPPORTED:
410 			seq_puts(m, " nva_supported");
411 			break;
412 		case PDC_MODEL_NVA_SLOW:
413 			seq_puts(m, " nva_slow");
414 			break;
415 		case PDC_MODEL_NVA_UNSUPPORTED:
416 			seq_puts(m, " needs_equivalent_aliasing");
417 			break;
418 		}
419 		seq_printf(m, " (0x%02lx)\n", boot_cpu_data.pdc.capabilities);
420 
421 		seq_printf(m, "model\t\t: %s\n"
422 				"model name\t: %s\n",
423 				 boot_cpu_data.pdc.sys_model_name,
424 				 cpuinfo->dev ?
425 				 cpuinfo->dev->name : "Unknown");
426 
427 		seq_printf(m, "hversion\t: 0x%08x\n"
428 			        "sversion\t: 0x%08x\n",
429 				 boot_cpu_data.hversion,
430 				 boot_cpu_data.sversion );
431 
432 		/* print cachesize info */
433 		show_cache_info(m);
434 
435 		seq_printf(m, "bogomips\t: %lu.%02lu\n",
436 			     loops_per_jiffy / (500000 / HZ),
437 			     loops_per_jiffy / (5000 / HZ) % 100);
438 
439 		seq_printf(m, "software id\t: %ld\n\n",
440 				boot_cpu_data.pdc.model.sw_id);
441 	}
442 	return 0;
443 }
444 
445 static const struct parisc_device_id processor_tbl[] __initconst = {
446 	{ HPHW_NPROC, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, SVERSION_ANY_ID },
447 	{ 0, }
448 };
449 
450 static struct parisc_driver cpu_driver __refdata = {
451 	.name		= "CPU",
452 	.id_table	= processor_tbl,
453 	.probe		= processor_probe
454 };
455 
456 /**
457  * processor_init - Processor initialization procedure.
458  *
459  * Register this driver.
460  */
processor_init(void)461 void __init processor_init(void)
462 {
463 	register_parisc_driver(&cpu_driver);
464 }
465