1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
4  *
5  * Author: Michael Johnston <michael.johnston@freescale.com>
6  *
7  * Description:
8  * TWR-P102x Board Setup
9  */
10 
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/errno.h>
14 #include <linux/fsl/guts.h>
15 #include <linux/pci.h>
16 #include <linux/of_platform.h>
17 
18 #include <asm/pci-bridge.h>
19 #include <asm/udbg.h>
20 #include <asm/mpic.h>
21 #include <soc/fsl/qe/qe.h>
22 
23 #include <sysdev/fsl_soc.h>
24 #include <sysdev/fsl_pci.h>
25 #include "smp.h"
26 
27 #include "mpc85xx.h"
28 
twr_p1025_pic_init(void)29 static void __init twr_p1025_pic_init(void)
30 {
31 	struct mpic *mpic;
32 
33 	mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
34 			MPIC_SINGLE_DEST_CPU,
35 			0, 256, " OpenPIC  ");
36 
37 	BUG_ON(mpic == NULL);
38 	mpic_init(mpic);
39 }
40 
41 /* ************************************************************************
42  *
43  * Setup the architecture
44  *
45  */
twr_p1025_setup_arch(void)46 static void __init twr_p1025_setup_arch(void)
47 {
48 	if (ppc_md.progress)
49 		ppc_md.progress("twr_p1025_setup_arch()", 0);
50 
51 	mpc85xx_smp_init();
52 
53 	fsl_pci_assign_primary();
54 
55 #ifdef CONFIG_QUICC_ENGINE
56 	mpc85xx_qe_par_io_init();
57 
58 #if IS_ENABLED(CONFIG_UCC_GETH) || IS_ENABLED(CONFIG_SERIAL_QE)
59 	if (machine_is(twr_p1025)) {
60 		struct ccsr_guts __iomem *guts;
61 		struct device_node *np;
62 
63 		np = of_find_compatible_node(NULL, NULL, "fsl,p1021-guts");
64 		if (np) {
65 			guts = of_iomap(np, 0);
66 			if (!guts)
67 				pr_err("twr_p1025: could not map global utilities register\n");
68 			else {
69 			/* P1025 has pins muxed for QE and other functions. To
70 			 * enable QE UEC mode, we need to set bit QE0 for UCC1
71 			 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
72 			 * and QE12 for QE MII management signals in PMUXCR
73 			 * register.
74 			 * Set QE mux bits in PMUXCR */
75 			setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
76 					MPC85xx_PMUXCR_QE(3) |
77 					MPC85xx_PMUXCR_QE(9) |
78 					MPC85xx_PMUXCR_QE(12));
79 			iounmap(guts);
80 
81 #if IS_ENABLED(CONFIG_SERIAL_QE)
82 			/* On P1025TWR board, the UCC7 acted as UART port.
83 			 * However, The UCC7's CTS pin is low level in default,
84 			 * it will impact the transmission in full duplex
85 			 * communication. So disable the Flow control pin PA18.
86 			 * The UCC7 UART just can use RXD and TXD pins.
87 			 */
88 			par_io_config_pin(0, 18, 0, 0, 0, 0);
89 #endif
90 			/* Drive PB29 to CPLD low - CPLD will then change
91 			 * muxing from LBC to QE */
92 			par_io_config_pin(1, 29, 1, 0, 0, 0);
93 			par_io_data_set(1, 29, 0);
94 			}
95 			of_node_put(np);
96 		}
97 	}
98 #endif
99 #endif	/* CONFIG_QUICC_ENGINE */
100 
101 	pr_info("TWR-P1025 board from Freescale Semiconductor\n");
102 }
103 
104 machine_arch_initcall(twr_p1025, mpc85xx_common_publish_devices);
105 
twr_p1025_probe(void)106 static int __init twr_p1025_probe(void)
107 {
108 	return of_machine_is_compatible("fsl,TWR-P1025");
109 }
110 
define_machine(twr_p1025)111 define_machine(twr_p1025) {
112 	.name			= "TWR-P1025",
113 	.probe			= twr_p1025_probe,
114 	.setup_arch		= twr_p1025_setup_arch,
115 	.init_IRQ		= twr_p1025_pic_init,
116 #ifdef CONFIG_PCI
117 	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
118 #endif
119 	.get_irq		= mpic_get_irq,
120 	.calibrate_decr		= generic_calibrate_decr,
121 	.progress		= udbg_progress,
122 };
123