1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
4 * Copyright (C) 2020 Western Digital Corporation or its affiliates.
5 */
6#include <dt-bindings/clock/k210-clk.h>
7#include <dt-bindings/pinctrl/k210-fpioa.h>
8#include <dt-bindings/reset/k210-rst.h>
9
10/ {
11	/*
12	 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
13	 * wide, and the upper half of all addresses is ignored.
14	 */
15	#address-cells = <1>;
16	#size-cells = <1>;
17	compatible = "canaan,kendryte-k210";
18
19	aliases {
20		serial0 = &uarths0;
21		serial1 = &uart1;
22		serial2 = &uart2;
23		serial3 = &uart3;
24	};
25
26	/*
27	 * The K210 has an sv39 MMU following the privileged specification v1.9.
28	 * Since this is a non-ratified draft specification, the kernel does not
29	 * support it and the K210 support enabled only for the !MMU case.
30	 * Be consistent with this by setting the CPUs MMU type to "none".
31	 */
32	cpus {
33		#address-cells = <1>;
34		#size-cells = <0>;
35		timebase-frequency = <7800000>;
36		cpu0: cpu@0 {
37			device_type = "cpu";
38			compatible = "canaan,k210", "riscv";
39			reg = <0>;
40			riscv,isa = "rv64imafdc";
41			mmu-type = "riscv,none";
42			i-cache-block-size = <64>;
43			i-cache-size = <0x8000>;
44			d-cache-block-size = <64>;
45			d-cache-size = <0x8000>;
46			cpu0_intc: interrupt-controller {
47				#interrupt-cells = <1>;
48				interrupt-controller;
49				compatible = "riscv,cpu-intc";
50			};
51		};
52		cpu1: cpu@1 {
53			device_type = "cpu";
54			compatible = "canaan,k210", "riscv";
55			reg = <1>;
56			riscv,isa = "rv64imafdc";
57			mmu-type = "riscv,none";
58			i-cache-block-size = <64>;
59			i-cache-size = <0x8000>;
60			d-cache-block-size = <64>;
61			d-cache-size = <0x8000>;
62			cpu1_intc: interrupt-controller {
63				#interrupt-cells = <1>;
64				interrupt-controller;
65				compatible = "riscv,cpu-intc";
66			};
67		};
68	};
69
70	sram: memory@80000000 {
71		device_type = "memory";
72		compatible = "canaan,k210-sram";
73		reg = <0x80000000 0x400000>,
74		      <0x80400000 0x200000>,
75		      <0x80600000 0x200000>;
76		reg-names = "sram0", "sram1", "aisram";
77		clocks = <&sysclk K210_CLK_SRAM0>,
78			 <&sysclk K210_CLK_SRAM1>,
79			 <&sysclk K210_CLK_AI>;
80		clock-names = "sram0", "sram1", "aisram";
81	};
82
83	clocks {
84		in0: oscillator {
85			compatible = "fixed-clock";
86			#clock-cells = <0>;
87			clock-frequency = <26000000>;
88		};
89	};
90
91	soc {
92		#address-cells = <1>;
93		#size-cells = <1>;
94		compatible = "simple-bus";
95		ranges;
96		interrupt-parent = <&plic0>;
97
98		rom0: nvmem@1000 {
99			reg = <0x1000 0x1000>;
100			read-only;
101		};
102
103		clint0: timer@2000000 {
104			compatible = "canaan,k210-clint", "sifive,clint0";
105			reg = <0x2000000 0xC000>;
106			interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
107					      &cpu1_intc 3 &cpu1_intc 7>;
108		};
109
110		plic0: interrupt-controller@c000000 {
111			#interrupt-cells = <1>;
112			#address-cells = <0>;
113			compatible = "canaan,k210-plic", "sifive,plic-1.0.0";
114			reg = <0xC000000 0x4000000>;
115			interrupt-controller;
116			interrupts-extended = <&cpu0_intc 11 &cpu1_intc 11>;
117			riscv,ndev = <65>;
118		};
119
120		uarths0: serial@38000000 {
121			compatible = "canaan,k210-uarths", "sifive,uart0";
122			reg = <0x38000000 0x1000>;
123			interrupts = <33>;
124			clocks = <&sysclk K210_CLK_CPU>;
125		};
126
127		gpio0: gpio-controller@38001000 {
128			#interrupt-cells = <2>;
129			#gpio-cells = <2>;
130			compatible = "canaan,k210-gpiohs", "sifive,gpio0";
131			reg = <0x38001000 0x1000>;
132			interrupt-controller;
133			interrupts = <34 35 36 37 38 39 40 41
134				      42 43 44 45 46 47 48 49
135				      50 51 52 53 54 55 56 57
136				      58 59 60 61 62 63 64 65>;
137			gpio-controller;
138			ngpios = <32>;
139		};
140
141		dmac0: dma-controller@50000000 {
142			compatible = "snps,axi-dma-1.01a";
143			reg = <0x50000000 0x1000>;
144			interrupts = <27 28 29 30 31 32>;
145			#dma-cells = <1>;
146			clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>;
147			clock-names = "core-clk", "cfgr-clk";
148			resets = <&sysrst K210_RST_DMA>;
149			dma-channels = <6>;
150			snps,dma-masters = <2>;
151			snps,priority = <0 1 2 3 4 5>;
152			snps,data-width = <5>;
153			snps,block-size = <0x200000 0x200000 0x200000
154					   0x200000 0x200000 0x200000>;
155			snps,axi-max-burst-len = <256>;
156		};
157
158		apb0: bus@50200000 {
159			#address-cells = <1>;
160			#size-cells = <1>;
161			compatible = "simple-pm-bus";
162			ranges;
163			clocks = <&sysclk K210_CLK_APB0>;
164
165			gpio1: gpio@50200000 {
166				#address-cells = <1>;
167				#size-cells = <0>;
168				compatible = "snps,dw-apb-gpio";
169				reg = <0x50200000 0x80>;
170				clocks = <&sysclk K210_CLK_APB0>,
171					 <&sysclk K210_CLK_GPIO>;
172				clock-names = "bus", "db";
173				resets = <&sysrst K210_RST_GPIO>;
174
175				gpio1_0: gpio-port@0 {
176					#gpio-cells = <2>;
177					#interrupt-cells = <2>;
178					compatible = "snps,dw-apb-gpio-port";
179					reg = <0>;
180					interrupt-controller;
181					interrupts = <23>;
182					gpio-controller;
183					ngpios = <8>;
184				};
185			};
186
187			uart1: serial@50210000 {
188				compatible = "snps,dw-apb-uart";
189				reg = <0x50210000 0x100>;
190				interrupts = <11>;
191				clocks = <&sysclk K210_CLK_UART1>,
192					 <&sysclk K210_CLK_APB0>;
193				clock-names = "baudclk", "apb_pclk";
194				resets = <&sysrst K210_RST_UART1>;
195				reg-io-width = <4>;
196				reg-shift = <2>;
197				dcd-override;
198				dsr-override;
199				cts-override;
200				ri-override;
201			};
202
203			uart2: serial@50220000 {
204				compatible = "snps,dw-apb-uart";
205				reg = <0x50220000 0x100>;
206				interrupts = <12>;
207				clocks = <&sysclk K210_CLK_UART2>,
208					 <&sysclk K210_CLK_APB0>;
209				clock-names = "baudclk", "apb_pclk";
210				resets = <&sysrst K210_RST_UART2>;
211				reg-io-width = <4>;
212				reg-shift = <2>;
213				dcd-override;
214				dsr-override;
215				cts-override;
216				ri-override;
217			};
218
219			uart3: serial@50230000 {
220				compatible = "snps,dw-apb-uart";
221				reg = <0x50230000 0x100>;
222				interrupts = <13>;
223				clocks = <&sysclk K210_CLK_UART3>,
224					 <&sysclk K210_CLK_APB0>;
225				clock-names = "baudclk", "apb_pclk";
226				resets = <&sysrst K210_RST_UART3>;
227				reg-io-width = <4>;
228				reg-shift = <2>;
229				dcd-override;
230				dsr-override;
231				cts-override;
232				ri-override;
233			};
234
235			spi2: spi@50240000 {
236				compatible = "canaan,k210-spi";
237				spi-slave;
238				reg = <0x50240000 0x100>;
239				#address-cells = <0>;
240				#size-cells = <0>;
241				interrupts = <3>;
242				clocks = <&sysclk K210_CLK_SPI2>,
243					 <&sysclk K210_CLK_APB0>;
244				clock-names = "ssi_clk", "pclk";
245				resets = <&sysrst K210_RST_SPI2>;
246				spi-max-frequency = <25000000>;
247			};
248
249			i2s0: i2s@50250000 {
250				compatible = "snps,designware-i2s";
251				reg = <0x50250000 0x200>;
252				interrupts = <5>;
253				clocks = <&sysclk K210_CLK_I2S0>;
254				clock-names = "i2sclk";
255				resets = <&sysrst K210_RST_I2S0>;
256			};
257
258			i2s1: i2s@50260000 {
259				compatible = "snps,designware-i2s";
260				reg = <0x50260000 0x200>;
261				interrupts = <6>;
262				clocks = <&sysclk K210_CLK_I2S1>;
263				clock-names = "i2sclk";
264				resets = <&sysrst K210_RST_I2S1>;
265			};
266
267			i2s2: i2s@50270000 {
268				compatible = "snps,designware-i2s";
269				reg = <0x50270000 0x200>;
270				interrupts = <7>;
271				clocks = <&sysclk K210_CLK_I2S2>;
272				clock-names = "i2sclk";
273				resets = <&sysrst K210_RST_I2S2>;
274			};
275
276			i2c0: i2c@50280000 {
277				compatible = "snps,designware-i2c";
278				reg = <0x50280000 0x100>;
279				interrupts = <8>;
280				clocks = <&sysclk K210_CLK_I2C0>,
281					 <&sysclk K210_CLK_APB0>;
282				clock-names = "ref", "pclk";
283				resets = <&sysrst K210_RST_I2C0>;
284			};
285
286			i2c1: i2c@50290000 {
287				compatible = "snps,designware-i2c";
288				reg = <0x50290000 0x100>;
289				interrupts = <9>;
290				clocks = <&sysclk K210_CLK_I2C1>,
291					 <&sysclk K210_CLK_APB0>;
292				clock-names = "ref", "pclk";
293				resets = <&sysrst K210_RST_I2C1>;
294			};
295
296			i2c2: i2c@502a0000 {
297				compatible = "snps,designware-i2c";
298				reg = <0x502A0000 0x100>;
299				interrupts = <10>;
300				clocks = <&sysclk K210_CLK_I2C2>,
301					 <&sysclk K210_CLK_APB0>;
302				clock-names = "ref", "pclk";
303				resets = <&sysrst K210_RST_I2C2>;
304			};
305
306			fpioa: pinmux@502b0000 {
307				compatible = "canaan,k210-fpioa";
308				reg = <0x502B0000 0x100>;
309				clocks = <&sysclk K210_CLK_FPIOA>,
310					 <&sysclk K210_CLK_APB0>;
311				clock-names = "ref", "pclk";
312				resets = <&sysrst K210_RST_FPIOA>;
313				canaan,k210-sysctl-power = <&sysctl 108>;
314			};
315
316			timer0: timer@502d0000 {
317				compatible = "snps,dw-apb-timer";
318				reg = <0x502D0000 0x100>;
319				interrupts = <14 15>;
320				clocks = <&sysclk K210_CLK_TIMER0>,
321					 <&sysclk K210_CLK_APB0>;
322				clock-names = "timer", "pclk";
323				resets = <&sysrst K210_RST_TIMER0>;
324			};
325
326			timer1: timer@502e0000 {
327				compatible = "snps,dw-apb-timer";
328				reg = <0x502E0000 0x100>;
329				interrupts = <16 17>;
330				clocks = <&sysclk K210_CLK_TIMER1>,
331					 <&sysclk K210_CLK_APB0>;
332				clock-names = "timer", "pclk";
333				resets = <&sysrst K210_RST_TIMER1>;
334			};
335
336			timer2: timer@502f0000 {
337				compatible = "snps,dw-apb-timer";
338				reg = <0x502F0000 0x100>;
339				interrupts = <18 19>;
340				clocks = <&sysclk K210_CLK_TIMER2>,
341					 <&sysclk K210_CLK_APB0>;
342				clock-names = "timer", "pclk";
343				resets = <&sysrst K210_RST_TIMER2>;
344			};
345		};
346
347		apb1: bus@50400000 {
348			#address-cells = <1>;
349			#size-cells = <1>;
350			compatible = "simple-pm-bus";
351			ranges;
352			clocks = <&sysclk K210_CLK_APB1>;
353
354			wdt0: watchdog@50400000 {
355				compatible = "snps,dw-wdt";
356				reg = <0x50400000 0x100>;
357				interrupts = <21>;
358				clocks = <&sysclk K210_CLK_WDT0>,
359					 <&sysclk K210_CLK_APB1>;
360				clock-names = "tclk", "pclk";
361				resets = <&sysrst K210_RST_WDT0>;
362			};
363
364			wdt1: watchdog@50410000 {
365				compatible = "snps,dw-wdt";
366				reg = <0x50410000 0x100>;
367				interrupts = <22>;
368				clocks = <&sysclk K210_CLK_WDT1>,
369					 <&sysclk K210_CLK_APB1>;
370				clock-names = "tclk", "pclk";
371				resets = <&sysrst K210_RST_WDT1>;
372			};
373
374			sysctl: syscon@50440000 {
375				compatible = "canaan,k210-sysctl",
376					     "syscon", "simple-mfd";
377				reg = <0x50440000 0x100>;
378				clocks = <&sysclk K210_CLK_APB1>;
379				clock-names = "pclk";
380
381				sysclk: clock-controller {
382					#clock-cells = <1>;
383					compatible = "canaan,k210-clk";
384					clocks = <&in0>;
385				};
386
387				sysrst: reset-controller {
388					compatible = "canaan,k210-rst";
389					#reset-cells = <1>;
390				};
391
392				reboot: syscon-reboot {
393					compatible = "syscon-reboot";
394					regmap = <&sysctl>;
395					offset = <48>;
396					mask = <1>;
397					value = <1>;
398				};
399			};
400		};
401
402		apb2: bus@52000000 {
403			#address-cells = <1>;
404			#size-cells = <1>;
405			compatible = "simple-pm-bus";
406			ranges;
407			clocks = <&sysclk K210_CLK_APB2>;
408
409			spi0: spi@52000000 {
410				#address-cells = <1>;
411				#size-cells = <0>;
412				compatible = "canaan,k210-spi";
413				reg = <0x52000000 0x100>;
414				interrupts = <1>;
415				clocks = <&sysclk K210_CLK_SPI0>,
416					 <&sysclk K210_CLK_APB2>;
417				clock-names = "ssi_clk", "pclk";
418				resets = <&sysrst K210_RST_SPI0>;
419				reset-names = "spi";
420				spi-max-frequency = <25000000>;
421				num-cs = <4>;
422				reg-io-width = <4>;
423			};
424
425			spi1: spi@53000000 {
426				#address-cells = <1>;
427				#size-cells = <0>;
428				compatible = "canaan,k210-spi";
429				reg = <0x53000000 0x100>;
430				interrupts = <2>;
431				clocks = <&sysclk K210_CLK_SPI1>,
432					 <&sysclk K210_CLK_APB2>;
433				clock-names = "ssi_clk", "pclk";
434				resets = <&sysrst K210_RST_SPI1>;
435				reset-names = "spi";
436				spi-max-frequency = <25000000>;
437				num-cs = <4>;
438				reg-io-width = <4>;
439			};
440
441			spi3: spi@54000000 {
442				#address-cells = <1>;
443				#size-cells = <0>;
444				compatible = "snps,dwc-ssi-1.01a";
445				reg = <0x54000000 0x200>;
446				interrupts = <4>;
447				clocks = <&sysclk K210_CLK_SPI3>,
448					 <&sysclk K210_CLK_APB2>;
449				clock-names = "ssi_clk", "pclk";
450				resets = <&sysrst K210_RST_SPI3>;
451				reset-names = "spi";
452				/* Could possibly go up to 200 MHz */
453				spi-max-frequency = <100000000>;
454				num-cs = <4>;
455				reg-io-width = <4>;
456			};
457		};
458	};
459};
460