1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* Copyright (c) 2020 Microchip Technology Inc */ 3 4/dts-v1/; 5 6#include "microchip-mpfs.dtsi" 7 8/* Clock frequency (in Hz) of the rtcclk */ 9#define RTCCLK_FREQ 1000000 10 11/ { 12 model = "Microchip PolarFire-SoC Icicle Kit"; 13 compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs"; 14 15 aliases { 16 ethernet0 = &emac1; 17 serial0 = &serial0; 18 serial1 = &serial1; 19 serial2 = &serial2; 20 serial3 = &serial3; 21 }; 22 23 chosen { 24 stdout-path = "serial0:115200n8"; 25 }; 26 27 cpus { 28 timebase-frequency = <RTCCLK_FREQ>; 29 }; 30 31 memory@80000000 { 32 device_type = "memory"; 33 reg = <0x0 0x80000000 0x0 0x40000000>; 34 clocks = <&clkcfg 26>; 35 }; 36}; 37 38&serial0 { 39 status = "okay"; 40}; 41 42&serial1 { 43 status = "okay"; 44}; 45 46&serial2 { 47 status = "okay"; 48}; 49 50&serial3 { 51 status = "okay"; 52}; 53 54&mmc { 55 status = "okay"; 56 57 bus-width = <4>; 58 disable-wp; 59 cap-sd-highspeed; 60 card-detect-delay = <200>; 61 sd-uhs-sdr12; 62 sd-uhs-sdr25; 63 sd-uhs-sdr50; 64 sd-uhs-sdr104; 65}; 66 67&emac0 { 68 phy-mode = "sgmii"; 69 phy-handle = <&phy0>; 70 phy0: ethernet-phy@8 { 71 reg = <8>; 72 ti,fifo-depth = <0x01>; 73 }; 74}; 75 76&emac1 { 77 status = "okay"; 78 phy-mode = "sgmii"; 79 phy-handle = <&phy1>; 80 phy1: ethernet-phy@9 { 81 reg = <9>; 82 ti,fifo-depth = <0x01>; 83 }; 84}; 85