1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * S390 version
4 * Copyright IBM Corp. 1999
5 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
6 *
7 * Derived from "include/asm-i386/spinlock.h"
8 */
9
10 #ifndef __ASM_SPINLOCK_H
11 #define __ASM_SPINLOCK_H
12
13 #include <linux/smp.h>
14 #include <asm/atomic_ops.h>
15 #include <asm/barrier.h>
16 #include <asm/processor.h>
17 #include <asm/alternative.h>
18
19 #define SPINLOCK_LOCKVAL (S390_lowcore.spinlock_lockval)
20
21 extern int spin_retry;
22
23 bool arch_vcpu_is_preempted(int cpu);
24
25 #define vcpu_is_preempted arch_vcpu_is_preempted
26
27 /*
28 * Simple spin lock operations. There are two variants, one clears IRQ's
29 * on the local processor, one does not.
30 *
31 * We make no fairness assumptions. They have a cost.
32 *
33 * (the type definitions are in asm/spinlock_types.h)
34 */
35
36 void arch_spin_relax(arch_spinlock_t *lock);
37 #define arch_spin_relax arch_spin_relax
38
39 void arch_spin_lock_wait(arch_spinlock_t *);
40 int arch_spin_trylock_retry(arch_spinlock_t *);
41 void arch_spin_lock_setup(int cpu);
42
arch_spin_lockval(int cpu)43 static inline u32 arch_spin_lockval(int cpu)
44 {
45 return cpu + 1;
46 }
47
arch_spin_value_unlocked(arch_spinlock_t lock)48 static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
49 {
50 return lock.lock == 0;
51 }
52
arch_spin_is_locked(arch_spinlock_t * lp)53 static inline int arch_spin_is_locked(arch_spinlock_t *lp)
54 {
55 return READ_ONCE(lp->lock) != 0;
56 }
57
arch_spin_trylock_once(arch_spinlock_t * lp)58 static inline int arch_spin_trylock_once(arch_spinlock_t *lp)
59 {
60 barrier();
61 return likely(__atomic_cmpxchg_bool(&lp->lock, 0, SPINLOCK_LOCKVAL));
62 }
63
arch_spin_lock(arch_spinlock_t * lp)64 static inline void arch_spin_lock(arch_spinlock_t *lp)
65 {
66 if (!arch_spin_trylock_once(lp))
67 arch_spin_lock_wait(lp);
68 }
69
arch_spin_trylock(arch_spinlock_t * lp)70 static inline int arch_spin_trylock(arch_spinlock_t *lp)
71 {
72 if (!arch_spin_trylock_once(lp))
73 return arch_spin_trylock_retry(lp);
74 return 1;
75 }
76
arch_spin_unlock(arch_spinlock_t * lp)77 static inline void arch_spin_unlock(arch_spinlock_t *lp)
78 {
79 typecheck(int, lp->lock);
80 asm_inline volatile(
81 ALTERNATIVE("", ".long 0xb2fa0070", 49) /* NIAI 7 */
82 " sth %1,%0\n"
83 : "=R" (((unsigned short *) &lp->lock)[1])
84 : "d" (0) : "cc", "memory");
85 }
86
87 /*
88 * Read-write spinlocks, allowing multiple readers
89 * but only one writer.
90 *
91 * NOTE! it is quite common to have readers in interrupts
92 * but no interrupt writers. For those circumstances we
93 * can "mix" irq-safe locks - any writer needs to get a
94 * irq-safe write-lock, but readers can get non-irqsafe
95 * read-locks.
96 */
97
98 #define arch_read_relax(rw) barrier()
99 #define arch_write_relax(rw) barrier()
100
101 void arch_read_lock_wait(arch_rwlock_t *lp);
102 void arch_write_lock_wait(arch_rwlock_t *lp);
103
arch_read_lock(arch_rwlock_t * rw)104 static inline void arch_read_lock(arch_rwlock_t *rw)
105 {
106 int old;
107
108 old = __atomic_add(1, &rw->cnts);
109 if (old & 0xffff0000)
110 arch_read_lock_wait(rw);
111 }
112
arch_read_unlock(arch_rwlock_t * rw)113 static inline void arch_read_unlock(arch_rwlock_t *rw)
114 {
115 __atomic_add_const_barrier(-1, &rw->cnts);
116 }
117
arch_write_lock(arch_rwlock_t * rw)118 static inline void arch_write_lock(arch_rwlock_t *rw)
119 {
120 if (!__atomic_cmpxchg_bool(&rw->cnts, 0, 0x30000))
121 arch_write_lock_wait(rw);
122 }
123
arch_write_unlock(arch_rwlock_t * rw)124 static inline void arch_write_unlock(arch_rwlock_t *rw)
125 {
126 __atomic_add_barrier(-0x30000, &rw->cnts);
127 }
128
129
arch_read_trylock(arch_rwlock_t * rw)130 static inline int arch_read_trylock(arch_rwlock_t *rw)
131 {
132 int old;
133
134 old = READ_ONCE(rw->cnts);
135 return (!(old & 0xffff0000) &&
136 __atomic_cmpxchg_bool(&rw->cnts, old, old + 1));
137 }
138
arch_write_trylock(arch_rwlock_t * rw)139 static inline int arch_write_trylock(arch_rwlock_t *rw)
140 {
141 int old;
142
143 old = READ_ONCE(rw->cnts);
144 return !old && __atomic_cmpxchg_bool(&rw->cnts, 0, 0x30000);
145 }
146
147 #endif /* __ASM_SPINLOCK_H */
148