1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2004 IBM Corporation
4 *
5 * Authors:
6 * Leendert van Doorn <leendert@watson.ibm.com>
7 * Dave Safford <safford@watson.ibm.com>
8 * Reiner Sailer <sailer@watson.ibm.com>
9 * Kylene Hall <kjhall@us.ibm.com>
10 *
11 * Maintained by: <tpmdd-devel@lists.sourceforge.net>
12 *
13 * Device driver for TCG/TCPA TPM (trusted platform module).
14 * Specifications at www.trustedcomputinggroup.org
15 */
16
17 #include <linux/platform_device.h>
18 #include <linux/slab.h>
19 #include "tpm.h"
20
21 /* National definitions */
22 enum tpm_nsc_addr{
23 TPM_NSC_IRQ = 0x07,
24 TPM_NSC_BASE0_HI = 0x60,
25 TPM_NSC_BASE0_LO = 0x61,
26 TPM_NSC_BASE1_HI = 0x62,
27 TPM_NSC_BASE1_LO = 0x63
28 };
29
30 enum tpm_nsc_index {
31 NSC_LDN_INDEX = 0x07,
32 NSC_SID_INDEX = 0x20,
33 NSC_LDC_INDEX = 0x30,
34 NSC_DIO_INDEX = 0x60,
35 NSC_CIO_INDEX = 0x62,
36 NSC_IRQ_INDEX = 0x70,
37 NSC_ITS_INDEX = 0x71
38 };
39
40 enum tpm_nsc_status_loc {
41 NSC_STATUS = 0x01,
42 NSC_COMMAND = 0x01,
43 NSC_DATA = 0x00
44 };
45
46 /* status bits */
47 enum tpm_nsc_status {
48 NSC_STATUS_OBF = 0x01, /* output buffer full */
49 NSC_STATUS_IBF = 0x02, /* input buffer full */
50 NSC_STATUS_F0 = 0x04, /* F0 */
51 NSC_STATUS_A2 = 0x08, /* A2 */
52 NSC_STATUS_RDY = 0x10, /* ready to receive command */
53 NSC_STATUS_IBR = 0x20 /* ready to receive data */
54 };
55
56 /* command bits */
57 enum tpm_nsc_cmd_mode {
58 NSC_COMMAND_NORMAL = 0x01, /* normal mode */
59 NSC_COMMAND_EOC = 0x03,
60 NSC_COMMAND_CANCEL = 0x22
61 };
62
63 struct tpm_nsc_priv {
64 unsigned long base;
65 };
66
67 /*
68 * Wait for a certain status to appear
69 */
wait_for_stat(struct tpm_chip * chip,u8 mask,u8 val,u8 * data)70 static int wait_for_stat(struct tpm_chip *chip, u8 mask, u8 val, u8 * data)
71 {
72 struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);
73 unsigned long stop;
74
75 /* status immediately available check */
76 *data = inb(priv->base + NSC_STATUS);
77 if ((*data & mask) == val)
78 return 0;
79
80 /* wait for status */
81 stop = jiffies + 10 * HZ;
82 do {
83 msleep(TPM_TIMEOUT);
84 *data = inb(priv->base + 1);
85 if ((*data & mask) == val)
86 return 0;
87 }
88 while (time_before(jiffies, stop));
89
90 return -EBUSY;
91 }
92
nsc_wait_for_ready(struct tpm_chip * chip)93 static int nsc_wait_for_ready(struct tpm_chip *chip)
94 {
95 struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);
96 int status;
97 unsigned long stop;
98
99 /* status immediately available check */
100 status = inb(priv->base + NSC_STATUS);
101 if (status & NSC_STATUS_OBF)
102 status = inb(priv->base + NSC_DATA);
103 if (status & NSC_STATUS_RDY)
104 return 0;
105
106 /* wait for status */
107 stop = jiffies + 100;
108 do {
109 msleep(TPM_TIMEOUT);
110 status = inb(priv->base + NSC_STATUS);
111 if (status & NSC_STATUS_OBF)
112 status = inb(priv->base + NSC_DATA);
113 if (status & NSC_STATUS_RDY)
114 return 0;
115 }
116 while (time_before(jiffies, stop));
117
118 dev_info(&chip->dev, "wait for ready failed\n");
119 return -EBUSY;
120 }
121
122
tpm_nsc_recv(struct tpm_chip * chip,u8 * buf,size_t count)123 static int tpm_nsc_recv(struct tpm_chip *chip, u8 * buf, size_t count)
124 {
125 struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);
126 u8 *buffer = buf;
127 u8 data, *p;
128 u32 size;
129 __be32 *native_size;
130
131 if (count < 6)
132 return -EIO;
133
134 if (wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0) {
135 dev_err(&chip->dev, "F0 timeout\n");
136 return -EIO;
137 }
138
139 data = inb(priv->base + NSC_DATA);
140 if (data != NSC_COMMAND_NORMAL) {
141 dev_err(&chip->dev, "not in normal mode (0x%x)\n",
142 data);
143 return -EIO;
144 }
145
146 /* read the whole packet */
147 for (p = buffer; p < &buffer[count]; p++) {
148 if (wait_for_stat
149 (chip, NSC_STATUS_OBF, NSC_STATUS_OBF, &data) < 0) {
150 dev_err(&chip->dev,
151 "OBF timeout (while reading data)\n");
152 return -EIO;
153 }
154 if (data & NSC_STATUS_F0)
155 break;
156 *p = inb(priv->base + NSC_DATA);
157 }
158
159 if ((data & NSC_STATUS_F0) == 0 &&
160 (wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0)) {
161 dev_err(&chip->dev, "F0 not set\n");
162 return -EIO;
163 }
164
165 data = inb(priv->base + NSC_DATA);
166 if (data != NSC_COMMAND_EOC) {
167 dev_err(&chip->dev,
168 "expected end of command(0x%x)\n", data);
169 return -EIO;
170 }
171
172 native_size = (__force __be32 *) (buf + 2);
173 size = be32_to_cpu(*native_size);
174
175 if (count < size)
176 return -EIO;
177
178 return size;
179 }
180
tpm_nsc_send(struct tpm_chip * chip,u8 * buf,size_t count)181 static int tpm_nsc_send(struct tpm_chip *chip, u8 * buf, size_t count)
182 {
183 struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);
184 u8 data;
185 int i;
186
187 /*
188 * If we hit the chip with back to back commands it locks up
189 * and never set IBF. Hitting it with this "hammer" seems to
190 * fix it. Not sure why this is needed, we followed the flow
191 * chart in the manual to the letter.
192 */
193 outb(NSC_COMMAND_CANCEL, priv->base + NSC_COMMAND);
194
195 if (nsc_wait_for_ready(chip) != 0)
196 return -EIO;
197
198 if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
199 dev_err(&chip->dev, "IBF timeout\n");
200 return -EIO;
201 }
202
203 outb(NSC_COMMAND_NORMAL, priv->base + NSC_COMMAND);
204 if (wait_for_stat(chip, NSC_STATUS_IBR, NSC_STATUS_IBR, &data) < 0) {
205 dev_err(&chip->dev, "IBR timeout\n");
206 return -EIO;
207 }
208
209 for (i = 0; i < count; i++) {
210 if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
211 dev_err(&chip->dev,
212 "IBF timeout (while writing data)\n");
213 return -EIO;
214 }
215 outb(buf[i], priv->base + NSC_DATA);
216 }
217
218 if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
219 dev_err(&chip->dev, "IBF timeout\n");
220 return -EIO;
221 }
222 outb(NSC_COMMAND_EOC, priv->base + NSC_COMMAND);
223
224 return 0;
225 }
226
tpm_nsc_cancel(struct tpm_chip * chip)227 static void tpm_nsc_cancel(struct tpm_chip *chip)
228 {
229 struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);
230
231 outb(NSC_COMMAND_CANCEL, priv->base + NSC_COMMAND);
232 }
233
tpm_nsc_status(struct tpm_chip * chip)234 static u8 tpm_nsc_status(struct tpm_chip *chip)
235 {
236 struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);
237
238 return inb(priv->base + NSC_STATUS);
239 }
240
tpm_nsc_req_canceled(struct tpm_chip * chip,u8 status)241 static bool tpm_nsc_req_canceled(struct tpm_chip *chip, u8 status)
242 {
243 return (status == NSC_STATUS_RDY);
244 }
245
246 static const struct tpm_class_ops tpm_nsc = {
247 .recv = tpm_nsc_recv,
248 .send = tpm_nsc_send,
249 .cancel = tpm_nsc_cancel,
250 .status = tpm_nsc_status,
251 .req_complete_mask = NSC_STATUS_OBF,
252 .req_complete_val = NSC_STATUS_OBF,
253 .req_canceled = tpm_nsc_req_canceled,
254 };
255
256 static struct platform_device *pdev = NULL;
257
tpm_nsc_remove(struct device * dev)258 static void tpm_nsc_remove(struct device *dev)
259 {
260 struct tpm_chip *chip = dev_get_drvdata(dev);
261 struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);
262
263 tpm_chip_unregister(chip);
264 release_region(priv->base, 2);
265 }
266
267 static SIMPLE_DEV_PM_OPS(tpm_nsc_pm, tpm_pm_suspend, tpm_pm_resume);
268
269 static struct platform_driver nsc_drv = {
270 .driver = {
271 .name = "tpm_nsc",
272 .pm = &tpm_nsc_pm,
273 },
274 };
275
tpm_read_index(int base,int index)276 static inline int tpm_read_index(int base, int index)
277 {
278 outb(index, base);
279 return inb(base+1) & 0xFF;
280 }
281
tpm_write_index(int base,int index,int value)282 static inline void tpm_write_index(int base, int index, int value)
283 {
284 outb(index, base);
285 outb(value & 0xFF, base+1);
286 }
287
init_nsc(void)288 static int __init init_nsc(void)
289 {
290 int rc = 0;
291 int lo, hi, err;
292 int nscAddrBase = TPM_ADDR;
293 struct tpm_chip *chip;
294 unsigned long base;
295 struct tpm_nsc_priv *priv;
296
297 /* verify that it is a National part (SID) */
298 if (tpm_read_index(TPM_ADDR, NSC_SID_INDEX) != 0xEF) {
299 nscAddrBase = (tpm_read_index(TPM_SUPERIO_ADDR, 0x2C)<<8)|
300 (tpm_read_index(TPM_SUPERIO_ADDR, 0x2B)&0xFE);
301 if (tpm_read_index(nscAddrBase, NSC_SID_INDEX) != 0xF6)
302 return -ENODEV;
303 }
304
305 err = platform_driver_register(&nsc_drv);
306 if (err)
307 return err;
308
309 hi = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_HI);
310 lo = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_LO);
311 base = (hi<<8) | lo;
312
313 /* enable the DPM module */
314 tpm_write_index(nscAddrBase, NSC_LDC_INDEX, 0x01);
315
316 pdev = platform_device_alloc("tpm_nscl0", -1);
317 if (!pdev) {
318 rc = -ENOMEM;
319 goto err_unreg_drv;
320 }
321
322 pdev->num_resources = 0;
323 pdev->dev.driver = &nsc_drv.driver;
324 pdev->dev.release = tpm_nsc_remove;
325
326 if ((rc = platform_device_add(pdev)) < 0)
327 goto err_put_dev;
328
329 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
330 if (!priv) {
331 rc = -ENOMEM;
332 goto err_del_dev;
333 }
334
335 priv->base = base;
336
337 if (request_region(base, 2, "tpm_nsc0") == NULL ) {
338 rc = -EBUSY;
339 goto err_del_dev;
340 }
341
342 chip = tpmm_chip_alloc(&pdev->dev, &tpm_nsc);
343 if (IS_ERR(chip)) {
344 rc = -ENODEV;
345 goto err_rel_reg;
346 }
347
348 dev_set_drvdata(&chip->dev, priv);
349
350 rc = tpm_chip_register(chip);
351 if (rc)
352 goto err_rel_reg;
353
354 dev_dbg(&pdev->dev, "NSC TPM detected\n");
355 dev_dbg(&pdev->dev,
356 "NSC LDN 0x%x, SID 0x%x, SRID 0x%x\n",
357 tpm_read_index(nscAddrBase,0x07), tpm_read_index(nscAddrBase,0x20),
358 tpm_read_index(nscAddrBase,0x27));
359 dev_dbg(&pdev->dev,
360 "NSC SIOCF1 0x%x SIOCF5 0x%x SIOCF6 0x%x SIOCF8 0x%x\n",
361 tpm_read_index(nscAddrBase,0x21), tpm_read_index(nscAddrBase,0x25),
362 tpm_read_index(nscAddrBase,0x26), tpm_read_index(nscAddrBase,0x28));
363 dev_dbg(&pdev->dev, "NSC IO Base0 0x%x\n",
364 (tpm_read_index(nscAddrBase,0x60) << 8) | tpm_read_index(nscAddrBase,0x61));
365 dev_dbg(&pdev->dev, "NSC IO Base1 0x%x\n",
366 (tpm_read_index(nscAddrBase,0x62) << 8) | tpm_read_index(nscAddrBase,0x63));
367 dev_dbg(&pdev->dev, "NSC Interrupt number and wakeup 0x%x\n",
368 tpm_read_index(nscAddrBase,0x70));
369 dev_dbg(&pdev->dev, "NSC IRQ type select 0x%x\n",
370 tpm_read_index(nscAddrBase,0x71));
371 dev_dbg(&pdev->dev,
372 "NSC DMA channel select0 0x%x, select1 0x%x\n",
373 tpm_read_index(nscAddrBase,0x74), tpm_read_index(nscAddrBase,0x75));
374 dev_dbg(&pdev->dev,
375 "NSC Config "
376 "0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
377 tpm_read_index(nscAddrBase,0xF0), tpm_read_index(nscAddrBase,0xF1),
378 tpm_read_index(nscAddrBase,0xF2), tpm_read_index(nscAddrBase,0xF3),
379 tpm_read_index(nscAddrBase,0xF4), tpm_read_index(nscAddrBase,0xF5),
380 tpm_read_index(nscAddrBase,0xF6), tpm_read_index(nscAddrBase,0xF7),
381 tpm_read_index(nscAddrBase,0xF8), tpm_read_index(nscAddrBase,0xF9));
382
383 dev_info(&pdev->dev,
384 "NSC TPM revision %d\n",
385 tpm_read_index(nscAddrBase, 0x27) & 0x1F);
386
387 return 0;
388
389 err_rel_reg:
390 release_region(base, 2);
391 err_del_dev:
392 platform_device_del(pdev);
393 err_put_dev:
394 platform_device_put(pdev);
395 err_unreg_drv:
396 platform_driver_unregister(&nsc_drv);
397 return rc;
398 }
399
cleanup_nsc(void)400 static void __exit cleanup_nsc(void)
401 {
402 if (pdev) {
403 tpm_nsc_remove(&pdev->dev);
404 platform_device_unregister(pdev);
405 }
406
407 platform_driver_unregister(&nsc_drv);
408 }
409
410 module_init(init_nsc);
411 module_exit(cleanup_nsc);
412
413 MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
414 MODULE_DESCRIPTION("TPM Driver");
415 MODULE_VERSION("2.0");
416 MODULE_LICENSE("GPL");
417