1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7 #include <linux/module.h>
8 #include <linux/clk-provider.h>
9 #include <linux/of.h>
10 #include <linux/of_address.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13
14 #include "clk-mtk.h"
15 #include "clk-gate.h"
16
17 #include <dt-bindings/clock/mt6779-clk.h>
18
19 static const struct mtk_gate_regs audio0_cg_regs = {
20 .set_ofs = 0x0,
21 .clr_ofs = 0x0,
22 .sta_ofs = 0x0,
23 };
24
25 static const struct mtk_gate_regs audio1_cg_regs = {
26 .set_ofs = 0x4,
27 .clr_ofs = 0x4,
28 .sta_ofs = 0x4,
29 };
30
31 #define GATE_AUDIO0(_id, _name, _parent, _shift) \
32 GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, \
33 &mtk_clk_gate_ops_no_setclr)
34 #define GATE_AUDIO1(_id, _name, _parent, _shift) \
35 GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, \
36 &mtk_clk_gate_ops_no_setclr)
37
38 static const struct mtk_gate audio_clks[] = {
39 /* AUDIO0 */
40 GATE_AUDIO0(CLK_AUD_AFE, "aud_afe", "audio_sel", 2),
41 GATE_AUDIO0(CLK_AUD_22M, "aud_22m", "aud_eng1_sel", 8),
42 GATE_AUDIO0(CLK_AUD_24M, "aud_24m", "aud_eng2_sel", 9),
43 GATE_AUDIO0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner",
44 "aud_eng2_sel", 18),
45 GATE_AUDIO0(CLK_AUD_APLL_TUNER, "aud_apll_tuner",
46 "aud_eng1_sel", 19),
47 GATE_AUDIO0(CLK_AUD_TDM, "aud_tdm", "aud_eng1_sel", 20),
48 GATE_AUDIO0(CLK_AUD_ADC, "aud_adc", "audio_sel", 24),
49 GATE_AUDIO0(CLK_AUD_DAC, "aud_dac", "audio_sel", 25),
50 GATE_AUDIO0(CLK_AUD_DAC_PREDIS, "aud_dac_predis",
51 "audio_sel", 26),
52 GATE_AUDIO0(CLK_AUD_TML, "aud_tml", "audio_sel", 27),
53 GATE_AUDIO0(CLK_AUD_NLE, "aud_nle", "audio_sel", 28),
54 /* AUDIO1 */
55 GATE_AUDIO1(CLK_AUD_I2S1_BCLK_SW, "aud_i2s1_bclk",
56 "audio_sel", 4),
57 GATE_AUDIO1(CLK_AUD_I2S2_BCLK_SW, "aud_i2s2_bclk",
58 "audio_sel", 5),
59 GATE_AUDIO1(CLK_AUD_I2S3_BCLK_SW, "aud_i2s3_bclk",
60 "audio_sel", 6),
61 GATE_AUDIO1(CLK_AUD_I2S4_BCLK_SW, "aud_i2s4_bclk",
62 "audio_sel", 7),
63 GATE_AUDIO1(CLK_AUD_I2S5_BCLK_SW, "aud_i2s5_bclk",
64 "audio_sel", 8),
65 GATE_AUDIO1(CLK_AUD_CONN_I2S_ASRC, "aud_conn_i2s",
66 "audio_sel", 12),
67 GATE_AUDIO1(CLK_AUD_GENERAL1_ASRC, "aud_general1",
68 "audio_sel", 13),
69 GATE_AUDIO1(CLK_AUD_GENERAL2_ASRC, "aud_general2",
70 "audio_sel", 14),
71 GATE_AUDIO1(CLK_AUD_DAC_HIRES, "aud_dac_hires",
72 "audio_h_sel", 15),
73 GATE_AUDIO1(CLK_AUD_ADC_HIRES, "aud_adc_hires",
74 "audio_h_sel", 16),
75 GATE_AUDIO1(CLK_AUD_ADC_HIRES_TML, "aud_adc_hires_tml",
76 "audio_h_sel", 17),
77 GATE_AUDIO1(CLK_AUD_PDN_ADDA6_ADC, "aud_pdn_adda6_adc",
78 "audio_sel", 20),
79 GATE_AUDIO1(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires",
80 "audio_h_sel",
81 21),
82 GATE_AUDIO1(CLK_AUD_3RD_DAC, "aud_3rd_dac", "audio_sel",
83 28),
84 GATE_AUDIO1(CLK_AUD_3RD_DAC_PREDIS, "aud_3rd_dac_predis",
85 "audio_sel", 29),
86 GATE_AUDIO1(CLK_AUD_3RD_DAC_TML, "aud_3rd_dac_tml",
87 "audio_sel", 30),
88 GATE_AUDIO1(CLK_AUD_3RD_DAC_HIRES, "aud_3rd_dac_hires",
89 "audio_h_sel", 31),
90 };
91
92 static const struct of_device_id of_match_clk_mt6779_aud[] = {
93 { .compatible = "mediatek,mt6779-audio", },
94 {}
95 };
96
clk_mt6779_aud_probe(struct platform_device * pdev)97 static int clk_mt6779_aud_probe(struct platform_device *pdev)
98 {
99 struct clk_onecell_data *clk_data;
100 struct device_node *node = pdev->dev.of_node;
101
102 clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);
103
104 mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
105 clk_data);
106
107 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
108 }
109
110 static struct platform_driver clk_mt6779_aud_drv = {
111 .probe = clk_mt6779_aud_probe,
112 .driver = {
113 .name = "clk-mt6779-aud",
114 .of_match_table = of_match_clk_mt6779_aud,
115 },
116 };
117
118 module_platform_driver(clk_mt6779_aud_drv);
119 MODULE_LICENSE("GPL");
120