1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
4  * Copyright (c) BayLibre, SAS.
5  * Author : Neil Armstrong <narmstrong@baylibre.com>
6  */
7 
8 #include <linux/kernel.h>
9 #include <linux/bitops.h>
10 #include <linux/err.h>
11 #include <linux/platform_device.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/of_device.h>
15 #include <linux/clk-provider.h>
16 #include <linux/regmap.h>
17 #include <linux/reset-controller.h>
18 
19 #include <dt-bindings/clock/qcom,gcc-mdm9615.h>
20 #include <dt-bindings/reset/qcom,gcc-mdm9615.h>
21 
22 #include "common.h"
23 #include "clk-regmap.h"
24 #include "clk-pll.h"
25 #include "clk-rcg.h"
26 #include "clk-branch.h"
27 #include "reset.h"
28 
29 static struct clk_fixed_factor cxo = {
30 	.mult = 1,
31 	.div = 1,
32 	.hw.init = &(struct clk_init_data){
33 		.name = "cxo",
34 		.parent_names = (const char *[]){ "cxo_board" },
35 		.num_parents = 1,
36 		.ops = &clk_fixed_factor_ops,
37 	},
38 };
39 
40 static struct clk_pll pll0 = {
41 	.l_reg = 0x30c4,
42 	.m_reg = 0x30c8,
43 	.n_reg = 0x30cc,
44 	.config_reg = 0x30d4,
45 	.mode_reg = 0x30c0,
46 	.status_reg = 0x30d8,
47 	.status_bit = 16,
48 	.clkr.hw.init = &(struct clk_init_data){
49 		.name = "pll0",
50 		.parent_names = (const char *[]){ "cxo" },
51 		.num_parents = 1,
52 		.ops = &clk_pll_ops,
53 	},
54 };
55 
56 static struct clk_regmap pll0_vote = {
57 	.enable_reg = 0x34c0,
58 	.enable_mask = BIT(0),
59 	.hw.init = &(struct clk_init_data){
60 		.name = "pll0_vote",
61 		.parent_names = (const char *[]){ "pll8" },
62 		.num_parents = 1,
63 		.ops = &clk_pll_vote_ops,
64 	},
65 };
66 
67 static struct clk_regmap pll4_vote = {
68 	.enable_reg = 0x34c0,
69 	.enable_mask = BIT(4),
70 	.hw.init = &(struct clk_init_data){
71 		.name = "pll4_vote",
72 		.parent_names = (const char *[]){ "pll4" },
73 		.num_parents = 1,
74 		.ops = &clk_pll_vote_ops,
75 	},
76 };
77 
78 static struct clk_pll pll8 = {
79 	.l_reg = 0x3144,
80 	.m_reg = 0x3148,
81 	.n_reg = 0x314c,
82 	.config_reg = 0x3154,
83 	.mode_reg = 0x3140,
84 	.status_reg = 0x3158,
85 	.status_bit = 16,
86 	.clkr.hw.init = &(struct clk_init_data){
87 		.name = "pll8",
88 		.parent_names = (const char *[]){ "cxo" },
89 		.num_parents = 1,
90 		.ops = &clk_pll_ops,
91 	},
92 };
93 
94 static struct clk_regmap pll8_vote = {
95 	.enable_reg = 0x34c0,
96 	.enable_mask = BIT(8),
97 	.hw.init = &(struct clk_init_data){
98 		.name = "pll8_vote",
99 		.parent_names = (const char *[]){ "pll8" },
100 		.num_parents = 1,
101 		.ops = &clk_pll_vote_ops,
102 	},
103 };
104 
105 static struct clk_pll pll14 = {
106 	.l_reg = 0x31c4,
107 	.m_reg = 0x31c8,
108 	.n_reg = 0x31cc,
109 	.config_reg = 0x31d4,
110 	.mode_reg = 0x31c0,
111 	.status_reg = 0x31d8,
112 	.status_bit = 16,
113 	.clkr.hw.init = &(struct clk_init_data){
114 		.name = "pll14",
115 		.parent_names = (const char *[]){ "cxo" },
116 		.num_parents = 1,
117 		.ops = &clk_pll_ops,
118 	},
119 };
120 
121 static struct clk_regmap pll14_vote = {
122 	.enable_reg = 0x34c0,
123 	.enable_mask = BIT(11),
124 	.hw.init = &(struct clk_init_data){
125 		.name = "pll14_vote",
126 		.parent_names = (const char *[]){ "pll14" },
127 		.num_parents = 1,
128 		.ops = &clk_pll_vote_ops,
129 	},
130 };
131 
132 enum {
133 	P_CXO,
134 	P_PLL8,
135 	P_PLL14,
136 };
137 
138 static const struct parent_map gcc_cxo_pll8_map[] = {
139 	{ P_CXO, 0 },
140 	{ P_PLL8, 3 }
141 };
142 
143 static const char * const gcc_cxo_pll8[] = {
144 	"cxo",
145 	"pll8_vote",
146 };
147 
148 static const struct parent_map gcc_cxo_pll14_map[] = {
149 	{ P_CXO, 0 },
150 	{ P_PLL14, 4 }
151 };
152 
153 static const char * const gcc_cxo_pll14[] = {
154 	"cxo",
155 	"pll14_vote",
156 };
157 
158 static const struct parent_map gcc_cxo_map[] = {
159 	{ P_CXO, 0 },
160 };
161 
162 static const char * const gcc_cxo[] = {
163 	"cxo",
164 };
165 
166 static struct freq_tbl clk_tbl_gsbi_uart[] = {
167 	{  1843200, P_PLL8, 2,  6, 625 },
168 	{  3686400, P_PLL8, 2, 12, 625 },
169 	{  7372800, P_PLL8, 2, 24, 625 },
170 	{ 14745600, P_PLL8, 2, 48, 625 },
171 	{ 16000000, P_PLL8, 4,  1,   6 },
172 	{ 24000000, P_PLL8, 4,  1,   4 },
173 	{ 32000000, P_PLL8, 4,  1,   3 },
174 	{ 40000000, P_PLL8, 1,  5,  48 },
175 	{ 46400000, P_PLL8, 1, 29, 240 },
176 	{ 48000000, P_PLL8, 4,  1,   2 },
177 	{ 51200000, P_PLL8, 1,  2,  15 },
178 	{ 56000000, P_PLL8, 1,  7,  48 },
179 	{ 58982400, P_PLL8, 1, 96, 625 },
180 	{ 64000000, P_PLL8, 2,  1,   3 },
181 	{ }
182 };
183 
184 static struct clk_rcg gsbi1_uart_src = {
185 	.ns_reg = 0x29d4,
186 	.md_reg = 0x29d0,
187 	.mn = {
188 		.mnctr_en_bit = 8,
189 		.mnctr_reset_bit = 7,
190 		.mnctr_mode_shift = 5,
191 		.n_val_shift = 16,
192 		.m_val_shift = 16,
193 		.width = 16,
194 	},
195 	.p = {
196 		.pre_div_shift = 3,
197 		.pre_div_width = 2,
198 	},
199 	.s = {
200 		.src_sel_shift = 0,
201 		.parent_map = gcc_cxo_pll8_map,
202 	},
203 	.freq_tbl = clk_tbl_gsbi_uart,
204 	.clkr = {
205 		.enable_reg = 0x29d4,
206 		.enable_mask = BIT(11),
207 		.hw.init = &(struct clk_init_data){
208 			.name = "gsbi1_uart_src",
209 			.parent_names = gcc_cxo_pll8,
210 			.num_parents = 2,
211 			.ops = &clk_rcg_ops,
212 			.flags = CLK_SET_PARENT_GATE,
213 		},
214 	},
215 };
216 
217 static struct clk_branch gsbi1_uart_clk = {
218 	.halt_reg = 0x2fcc,
219 	.halt_bit = 10,
220 	.clkr = {
221 		.enable_reg = 0x29d4,
222 		.enable_mask = BIT(9),
223 		.hw.init = &(struct clk_init_data){
224 			.name = "gsbi1_uart_clk",
225 			.parent_names = (const char *[]){
226 				"gsbi1_uart_src",
227 			},
228 			.num_parents = 1,
229 			.ops = &clk_branch_ops,
230 			.flags = CLK_SET_RATE_PARENT,
231 		},
232 	},
233 };
234 
235 static struct clk_rcg gsbi2_uart_src = {
236 	.ns_reg = 0x29f4,
237 	.md_reg = 0x29f0,
238 	.mn = {
239 		.mnctr_en_bit = 8,
240 		.mnctr_reset_bit = 7,
241 		.mnctr_mode_shift = 5,
242 		.n_val_shift = 16,
243 		.m_val_shift = 16,
244 		.width = 16,
245 	},
246 	.p = {
247 		.pre_div_shift = 3,
248 		.pre_div_width = 2,
249 	},
250 	.s = {
251 		.src_sel_shift = 0,
252 		.parent_map = gcc_cxo_pll8_map,
253 	},
254 	.freq_tbl = clk_tbl_gsbi_uart,
255 	.clkr = {
256 		.enable_reg = 0x29f4,
257 		.enable_mask = BIT(11),
258 		.hw.init = &(struct clk_init_data){
259 			.name = "gsbi2_uart_src",
260 			.parent_names = gcc_cxo_pll8,
261 			.num_parents = 2,
262 			.ops = &clk_rcg_ops,
263 			.flags = CLK_SET_PARENT_GATE,
264 		},
265 	},
266 };
267 
268 static struct clk_branch gsbi2_uart_clk = {
269 	.halt_reg = 0x2fcc,
270 	.halt_bit = 6,
271 	.clkr = {
272 		.enable_reg = 0x29f4,
273 		.enable_mask = BIT(9),
274 		.hw.init = &(struct clk_init_data){
275 			.name = "gsbi2_uart_clk",
276 			.parent_names = (const char *[]){
277 				"gsbi2_uart_src",
278 			},
279 			.num_parents = 1,
280 			.ops = &clk_branch_ops,
281 			.flags = CLK_SET_RATE_PARENT,
282 		},
283 	},
284 };
285 
286 static struct clk_rcg gsbi3_uart_src = {
287 	.ns_reg = 0x2a14,
288 	.md_reg = 0x2a10,
289 	.mn = {
290 		.mnctr_en_bit = 8,
291 		.mnctr_reset_bit = 7,
292 		.mnctr_mode_shift = 5,
293 		.n_val_shift = 16,
294 		.m_val_shift = 16,
295 		.width = 16,
296 	},
297 	.p = {
298 		.pre_div_shift = 3,
299 		.pre_div_width = 2,
300 	},
301 	.s = {
302 		.src_sel_shift = 0,
303 		.parent_map = gcc_cxo_pll8_map,
304 	},
305 	.freq_tbl = clk_tbl_gsbi_uart,
306 	.clkr = {
307 		.enable_reg = 0x2a14,
308 		.enable_mask = BIT(11),
309 		.hw.init = &(struct clk_init_data){
310 			.name = "gsbi3_uart_src",
311 			.parent_names = gcc_cxo_pll8,
312 			.num_parents = 2,
313 			.ops = &clk_rcg_ops,
314 			.flags = CLK_SET_PARENT_GATE,
315 		},
316 	},
317 };
318 
319 static struct clk_branch gsbi3_uart_clk = {
320 	.halt_reg = 0x2fcc,
321 	.halt_bit = 2,
322 	.clkr = {
323 		.enable_reg = 0x2a14,
324 		.enable_mask = BIT(9),
325 		.hw.init = &(struct clk_init_data){
326 			.name = "gsbi3_uart_clk",
327 			.parent_names = (const char *[]){
328 				"gsbi3_uart_src",
329 			},
330 			.num_parents = 1,
331 			.ops = &clk_branch_ops,
332 			.flags = CLK_SET_RATE_PARENT,
333 		},
334 	},
335 };
336 
337 static struct clk_rcg gsbi4_uart_src = {
338 	.ns_reg = 0x2a34,
339 	.md_reg = 0x2a30,
340 	.mn = {
341 		.mnctr_en_bit = 8,
342 		.mnctr_reset_bit = 7,
343 		.mnctr_mode_shift = 5,
344 		.n_val_shift = 16,
345 		.m_val_shift = 16,
346 		.width = 16,
347 	},
348 	.p = {
349 		.pre_div_shift = 3,
350 		.pre_div_width = 2,
351 	},
352 	.s = {
353 		.src_sel_shift = 0,
354 		.parent_map = gcc_cxo_pll8_map,
355 	},
356 	.freq_tbl = clk_tbl_gsbi_uart,
357 	.clkr = {
358 		.enable_reg = 0x2a34,
359 		.enable_mask = BIT(11),
360 		.hw.init = &(struct clk_init_data){
361 			.name = "gsbi4_uart_src",
362 			.parent_names = gcc_cxo_pll8,
363 			.num_parents = 2,
364 			.ops = &clk_rcg_ops,
365 			.flags = CLK_SET_PARENT_GATE,
366 		},
367 	},
368 };
369 
370 static struct clk_branch gsbi4_uart_clk = {
371 	.halt_reg = 0x2fd0,
372 	.halt_bit = 26,
373 	.clkr = {
374 		.enable_reg = 0x2a34,
375 		.enable_mask = BIT(9),
376 		.hw.init = &(struct clk_init_data){
377 			.name = "gsbi4_uart_clk",
378 			.parent_names = (const char *[]){
379 				"gsbi4_uart_src",
380 			},
381 			.num_parents = 1,
382 			.ops = &clk_branch_ops,
383 			.flags = CLK_SET_RATE_PARENT,
384 		},
385 	},
386 };
387 
388 static struct clk_rcg gsbi5_uart_src = {
389 	.ns_reg = 0x2a54,
390 	.md_reg = 0x2a50,
391 	.mn = {
392 		.mnctr_en_bit = 8,
393 		.mnctr_reset_bit = 7,
394 		.mnctr_mode_shift = 5,
395 		.n_val_shift = 16,
396 		.m_val_shift = 16,
397 		.width = 16,
398 	},
399 	.p = {
400 		.pre_div_shift = 3,
401 		.pre_div_width = 2,
402 	},
403 	.s = {
404 		.src_sel_shift = 0,
405 		.parent_map = gcc_cxo_pll8_map,
406 	},
407 	.freq_tbl = clk_tbl_gsbi_uart,
408 	.clkr = {
409 		.enable_reg = 0x2a54,
410 		.enable_mask = BIT(11),
411 		.hw.init = &(struct clk_init_data){
412 			.name = "gsbi5_uart_src",
413 			.parent_names = gcc_cxo_pll8,
414 			.num_parents = 2,
415 			.ops = &clk_rcg_ops,
416 			.flags = CLK_SET_PARENT_GATE,
417 		},
418 	},
419 };
420 
421 static struct clk_branch gsbi5_uart_clk = {
422 	.halt_reg = 0x2fd0,
423 	.halt_bit = 22,
424 	.clkr = {
425 		.enable_reg = 0x2a54,
426 		.enable_mask = BIT(9),
427 		.hw.init = &(struct clk_init_data){
428 			.name = "gsbi5_uart_clk",
429 			.parent_names = (const char *[]){
430 				"gsbi5_uart_src",
431 			},
432 			.num_parents = 1,
433 			.ops = &clk_branch_ops,
434 			.flags = CLK_SET_RATE_PARENT,
435 		},
436 	},
437 };
438 
439 static struct freq_tbl clk_tbl_gsbi_qup[] = {
440 	{   960000, P_CXO,  4, 1,  5 },
441 	{  4800000, P_CXO,  4, 0,  1 },
442 	{  9600000, P_CXO,  2, 0,  1 },
443 	{ 15060000, P_PLL8, 1, 2, 51 },
444 	{ 24000000, P_PLL8, 4, 1,  4 },
445 	{ 25600000, P_PLL8, 1, 1, 15 },
446 	{ 48000000, P_PLL8, 4, 1,  2 },
447 	{ 51200000, P_PLL8, 1, 2, 15 },
448 	{ }
449 };
450 
451 static struct clk_rcg gsbi1_qup_src = {
452 	.ns_reg = 0x29cc,
453 	.md_reg = 0x29c8,
454 	.mn = {
455 		.mnctr_en_bit = 8,
456 		.mnctr_reset_bit = 7,
457 		.mnctr_mode_shift = 5,
458 		.n_val_shift = 16,
459 		.m_val_shift = 16,
460 		.width = 8,
461 	},
462 	.p = {
463 		.pre_div_shift = 3,
464 		.pre_div_width = 2,
465 	},
466 	.s = {
467 		.src_sel_shift = 0,
468 		.parent_map = gcc_cxo_pll8_map,
469 	},
470 	.freq_tbl = clk_tbl_gsbi_qup,
471 	.clkr = {
472 		.enable_reg = 0x29cc,
473 		.enable_mask = BIT(11),
474 		.hw.init = &(struct clk_init_data){
475 			.name = "gsbi1_qup_src",
476 			.parent_names = gcc_cxo_pll8,
477 			.num_parents = 2,
478 			.ops = &clk_rcg_ops,
479 			.flags = CLK_SET_PARENT_GATE,
480 		},
481 	},
482 };
483 
484 static struct clk_branch gsbi1_qup_clk = {
485 	.halt_reg = 0x2fcc,
486 	.halt_bit = 9,
487 	.clkr = {
488 		.enable_reg = 0x29cc,
489 		.enable_mask = BIT(9),
490 		.hw.init = &(struct clk_init_data){
491 			.name = "gsbi1_qup_clk",
492 			.parent_names = (const char *[]){ "gsbi1_qup_src" },
493 			.num_parents = 1,
494 			.ops = &clk_branch_ops,
495 			.flags = CLK_SET_RATE_PARENT,
496 		},
497 	},
498 };
499 
500 static struct clk_rcg gsbi2_qup_src = {
501 	.ns_reg = 0x29ec,
502 	.md_reg = 0x29e8,
503 	.mn = {
504 		.mnctr_en_bit = 8,
505 		.mnctr_reset_bit = 7,
506 		.mnctr_mode_shift = 5,
507 		.n_val_shift = 16,
508 		.m_val_shift = 16,
509 		.width = 8,
510 	},
511 	.p = {
512 		.pre_div_shift = 3,
513 		.pre_div_width = 2,
514 	},
515 	.s = {
516 		.src_sel_shift = 0,
517 		.parent_map = gcc_cxo_pll8_map,
518 	},
519 	.freq_tbl = clk_tbl_gsbi_qup,
520 	.clkr = {
521 		.enable_reg = 0x29ec,
522 		.enable_mask = BIT(11),
523 		.hw.init = &(struct clk_init_data){
524 			.name = "gsbi2_qup_src",
525 			.parent_names = gcc_cxo_pll8,
526 			.num_parents = 2,
527 			.ops = &clk_rcg_ops,
528 			.flags = CLK_SET_PARENT_GATE,
529 		},
530 	},
531 };
532 
533 static struct clk_branch gsbi2_qup_clk = {
534 	.halt_reg = 0x2fcc,
535 	.halt_bit = 4,
536 	.clkr = {
537 		.enable_reg = 0x29ec,
538 		.enable_mask = BIT(9),
539 		.hw.init = &(struct clk_init_data){
540 			.name = "gsbi2_qup_clk",
541 			.parent_names = (const char *[]){ "gsbi2_qup_src" },
542 			.num_parents = 1,
543 			.ops = &clk_branch_ops,
544 			.flags = CLK_SET_RATE_PARENT,
545 		},
546 	},
547 };
548 
549 static struct clk_rcg gsbi3_qup_src = {
550 	.ns_reg = 0x2a0c,
551 	.md_reg = 0x2a08,
552 	.mn = {
553 		.mnctr_en_bit = 8,
554 		.mnctr_reset_bit = 7,
555 		.mnctr_mode_shift = 5,
556 		.n_val_shift = 16,
557 		.m_val_shift = 16,
558 		.width = 8,
559 	},
560 	.p = {
561 		.pre_div_shift = 3,
562 		.pre_div_width = 2,
563 	},
564 	.s = {
565 		.src_sel_shift = 0,
566 		.parent_map = gcc_cxo_pll8_map,
567 	},
568 	.freq_tbl = clk_tbl_gsbi_qup,
569 	.clkr = {
570 		.enable_reg = 0x2a0c,
571 		.enable_mask = BIT(11),
572 		.hw.init = &(struct clk_init_data){
573 			.name = "gsbi3_qup_src",
574 			.parent_names = gcc_cxo_pll8,
575 			.num_parents = 2,
576 			.ops = &clk_rcg_ops,
577 			.flags = CLK_SET_PARENT_GATE,
578 		},
579 	},
580 };
581 
582 static struct clk_branch gsbi3_qup_clk = {
583 	.halt_reg = 0x2fcc,
584 	.halt_bit = 0,
585 	.clkr = {
586 		.enable_reg = 0x2a0c,
587 		.enable_mask = BIT(9),
588 		.hw.init = &(struct clk_init_data){
589 			.name = "gsbi3_qup_clk",
590 			.parent_names = (const char *[]){ "gsbi3_qup_src" },
591 			.num_parents = 1,
592 			.ops = &clk_branch_ops,
593 			.flags = CLK_SET_RATE_PARENT,
594 		},
595 	},
596 };
597 
598 static struct clk_rcg gsbi4_qup_src = {
599 	.ns_reg = 0x2a2c,
600 	.md_reg = 0x2a28,
601 	.mn = {
602 		.mnctr_en_bit = 8,
603 		.mnctr_reset_bit = 7,
604 		.mnctr_mode_shift = 5,
605 		.n_val_shift = 16,
606 		.m_val_shift = 16,
607 		.width = 8,
608 	},
609 	.p = {
610 		.pre_div_shift = 3,
611 		.pre_div_width = 2,
612 	},
613 	.s = {
614 		.src_sel_shift = 0,
615 		.parent_map = gcc_cxo_pll8_map,
616 	},
617 	.freq_tbl = clk_tbl_gsbi_qup,
618 	.clkr = {
619 		.enable_reg = 0x2a2c,
620 		.enable_mask = BIT(11),
621 		.hw.init = &(struct clk_init_data){
622 			.name = "gsbi4_qup_src",
623 			.parent_names = gcc_cxo_pll8,
624 			.num_parents = 2,
625 			.ops = &clk_rcg_ops,
626 			.flags = CLK_SET_PARENT_GATE,
627 		},
628 	},
629 };
630 
631 static struct clk_branch gsbi4_qup_clk = {
632 	.halt_reg = 0x2fd0,
633 	.halt_bit = 24,
634 	.clkr = {
635 		.enable_reg = 0x2a2c,
636 		.enable_mask = BIT(9),
637 		.hw.init = &(struct clk_init_data){
638 			.name = "gsbi4_qup_clk",
639 			.parent_names = (const char *[]){ "gsbi4_qup_src" },
640 			.num_parents = 1,
641 			.ops = &clk_branch_ops,
642 			.flags = CLK_SET_RATE_PARENT,
643 		},
644 	},
645 };
646 
647 static struct clk_rcg gsbi5_qup_src = {
648 	.ns_reg = 0x2a4c,
649 	.md_reg = 0x2a48,
650 	.mn = {
651 		.mnctr_en_bit = 8,
652 		.mnctr_reset_bit = 7,
653 		.mnctr_mode_shift = 5,
654 		.n_val_shift = 16,
655 		.m_val_shift = 16,
656 		.width = 8,
657 	},
658 	.p = {
659 		.pre_div_shift = 3,
660 		.pre_div_width = 2,
661 	},
662 	.s = {
663 		.src_sel_shift = 0,
664 		.parent_map = gcc_cxo_pll8_map,
665 	},
666 	.freq_tbl = clk_tbl_gsbi_qup,
667 	.clkr = {
668 		.enable_reg = 0x2a4c,
669 		.enable_mask = BIT(11),
670 		.hw.init = &(struct clk_init_data){
671 			.name = "gsbi5_qup_src",
672 			.parent_names = gcc_cxo_pll8,
673 			.num_parents = 2,
674 			.ops = &clk_rcg_ops,
675 			.flags = CLK_SET_PARENT_GATE,
676 		},
677 	},
678 };
679 
680 static struct clk_branch gsbi5_qup_clk = {
681 	.halt_reg = 0x2fd0,
682 	.halt_bit = 20,
683 	.clkr = {
684 		.enable_reg = 0x2a4c,
685 		.enable_mask = BIT(9),
686 		.hw.init = &(struct clk_init_data){
687 			.name = "gsbi5_qup_clk",
688 			.parent_names = (const char *[]){ "gsbi5_qup_src" },
689 			.num_parents = 1,
690 			.ops = &clk_branch_ops,
691 			.flags = CLK_SET_RATE_PARENT,
692 		},
693 	},
694 };
695 
696 static const struct freq_tbl clk_tbl_gp[] = {
697 	{ 9600000, P_CXO,  2, 0, 0 },
698 	{ 19200000, P_CXO,  1, 0, 0 },
699 	{ }
700 };
701 
702 static struct clk_rcg gp0_src = {
703 	.ns_reg = 0x2d24,
704 	.md_reg = 0x2d00,
705 	.mn = {
706 		.mnctr_en_bit = 8,
707 		.mnctr_reset_bit = 7,
708 		.mnctr_mode_shift = 5,
709 		.n_val_shift = 16,
710 		.m_val_shift = 16,
711 		.width = 8,
712 	},
713 	.p = {
714 		.pre_div_shift = 3,
715 		.pre_div_width = 2,
716 	},
717 	.s = {
718 		.src_sel_shift = 0,
719 		.parent_map = gcc_cxo_map,
720 	},
721 	.freq_tbl = clk_tbl_gp,
722 	.clkr = {
723 		.enable_reg = 0x2d24,
724 		.enable_mask = BIT(11),
725 		.hw.init = &(struct clk_init_data){
726 			.name = "gp0_src",
727 			.parent_names = gcc_cxo,
728 			.num_parents = 1,
729 			.ops = &clk_rcg_ops,
730 			.flags = CLK_SET_PARENT_GATE,
731 		},
732 	}
733 };
734 
735 static struct clk_branch gp0_clk = {
736 	.halt_reg = 0x2fd8,
737 	.halt_bit = 7,
738 	.clkr = {
739 		.enable_reg = 0x2d24,
740 		.enable_mask = BIT(9),
741 		.hw.init = &(struct clk_init_data){
742 			.name = "gp0_clk",
743 			.parent_names = (const char *[]){ "gp0_src" },
744 			.num_parents = 1,
745 			.ops = &clk_branch_ops,
746 			.flags = CLK_SET_RATE_PARENT,
747 		},
748 	},
749 };
750 
751 static struct clk_rcg gp1_src = {
752 	.ns_reg = 0x2d44,
753 	.md_reg = 0x2d40,
754 	.mn = {
755 		.mnctr_en_bit = 8,
756 		.mnctr_reset_bit = 7,
757 		.mnctr_mode_shift = 5,
758 		.n_val_shift = 16,
759 		.m_val_shift = 16,
760 		.width = 8,
761 	},
762 	.p = {
763 		.pre_div_shift = 3,
764 		.pre_div_width = 2,
765 	},
766 	.s = {
767 		.src_sel_shift = 0,
768 		.parent_map = gcc_cxo_map,
769 	},
770 	.freq_tbl = clk_tbl_gp,
771 	.clkr = {
772 		.enable_reg = 0x2d44,
773 		.enable_mask = BIT(11),
774 		.hw.init = &(struct clk_init_data){
775 			.name = "gp1_src",
776 			.parent_names = gcc_cxo,
777 			.num_parents = 1,
778 			.ops = &clk_rcg_ops,
779 			.flags = CLK_SET_RATE_GATE,
780 		},
781 	}
782 };
783 
784 static struct clk_branch gp1_clk = {
785 	.halt_reg = 0x2fd8,
786 	.halt_bit = 6,
787 	.clkr = {
788 		.enable_reg = 0x2d44,
789 		.enable_mask = BIT(9),
790 		.hw.init = &(struct clk_init_data){
791 			.name = "gp1_clk",
792 			.parent_names = (const char *[]){ "gp1_src" },
793 			.num_parents = 1,
794 			.ops = &clk_branch_ops,
795 			.flags = CLK_SET_RATE_PARENT,
796 		},
797 	},
798 };
799 
800 static struct clk_rcg gp2_src = {
801 	.ns_reg = 0x2d64,
802 	.md_reg = 0x2d60,
803 	.mn = {
804 		.mnctr_en_bit = 8,
805 		.mnctr_reset_bit = 7,
806 		.mnctr_mode_shift = 5,
807 		.n_val_shift = 16,
808 		.m_val_shift = 16,
809 		.width = 8,
810 	},
811 	.p = {
812 		.pre_div_shift = 3,
813 		.pre_div_width = 2,
814 	},
815 	.s = {
816 		.src_sel_shift = 0,
817 		.parent_map = gcc_cxo_map,
818 	},
819 	.freq_tbl = clk_tbl_gp,
820 	.clkr = {
821 		.enable_reg = 0x2d64,
822 		.enable_mask = BIT(11),
823 		.hw.init = &(struct clk_init_data){
824 			.name = "gp2_src",
825 			.parent_names = gcc_cxo,
826 			.num_parents = 1,
827 			.ops = &clk_rcg_ops,
828 			.flags = CLK_SET_RATE_GATE,
829 		},
830 	}
831 };
832 
833 static struct clk_branch gp2_clk = {
834 	.halt_reg = 0x2fd8,
835 	.halt_bit = 5,
836 	.clkr = {
837 		.enable_reg = 0x2d64,
838 		.enable_mask = BIT(9),
839 		.hw.init = &(struct clk_init_data){
840 			.name = "gp2_clk",
841 			.parent_names = (const char *[]){ "gp2_src" },
842 			.num_parents = 1,
843 			.ops = &clk_branch_ops,
844 			.flags = CLK_SET_RATE_PARENT,
845 		},
846 	},
847 };
848 
849 static struct clk_branch pmem_clk = {
850 	.hwcg_reg = 0x25a0,
851 	.hwcg_bit = 6,
852 	.halt_reg = 0x2fc8,
853 	.halt_bit = 20,
854 	.clkr = {
855 		.enable_reg = 0x25a0,
856 		.enable_mask = BIT(4),
857 		.hw.init = &(struct clk_init_data){
858 			.name = "pmem_clk",
859 			.ops = &clk_branch_ops,
860 		},
861 	},
862 };
863 
864 static struct clk_rcg prng_src = {
865 	.ns_reg = 0x2e80,
866 	.p = {
867 		.pre_div_shift = 3,
868 		.pre_div_width = 4,
869 	},
870 	.s = {
871 		.src_sel_shift = 0,
872 		.parent_map = gcc_cxo_pll8_map,
873 	},
874 	.clkr = {
875 		.hw.init = &(struct clk_init_data){
876 			.name = "prng_src",
877 			.parent_names = gcc_cxo_pll8,
878 			.num_parents = 2,
879 			.ops = &clk_rcg_ops,
880 		},
881 	},
882 };
883 
884 static struct clk_branch prng_clk = {
885 	.halt_reg = 0x2fd8,
886 	.halt_check = BRANCH_HALT_VOTED,
887 	.halt_bit = 10,
888 	.clkr = {
889 		.enable_reg = 0x3080,
890 		.enable_mask = BIT(10),
891 		.hw.init = &(struct clk_init_data){
892 			.name = "prng_clk",
893 			.parent_names = (const char *[]){ "prng_src" },
894 			.num_parents = 1,
895 			.ops = &clk_branch_ops,
896 		},
897 	},
898 };
899 
900 static const struct freq_tbl clk_tbl_sdc[] = {
901 	{    144000, P_CXO,   1, 1, 133 },
902 	{    400000, P_PLL8,  4, 1, 240 },
903 	{  16000000, P_PLL8,  4, 1,   6 },
904 	{  17070000, P_PLL8,  1, 2,  45 },
905 	{  20210000, P_PLL8,  1, 1,  19 },
906 	{  24000000, P_PLL8,  4, 1,   4 },
907 	{  38400000, P_PLL8,  2, 1,   5 },
908 	{  48000000, P_PLL8,  4, 1,   2 },
909 	{  64000000, P_PLL8,  3, 1,   2 },
910 	{  76800000, P_PLL8,  1, 1,   5 },
911 	{ }
912 };
913 
914 static struct clk_rcg sdc1_src = {
915 	.ns_reg = 0x282c,
916 	.md_reg = 0x2828,
917 	.mn = {
918 		.mnctr_en_bit = 8,
919 		.mnctr_reset_bit = 7,
920 		.mnctr_mode_shift = 5,
921 		.n_val_shift = 16,
922 		.m_val_shift = 16,
923 		.width = 8,
924 	},
925 	.p = {
926 		.pre_div_shift = 3,
927 		.pre_div_width = 2,
928 	},
929 	.s = {
930 		.src_sel_shift = 0,
931 		.parent_map = gcc_cxo_pll8_map,
932 	},
933 	.freq_tbl = clk_tbl_sdc,
934 	.clkr = {
935 		.enable_reg = 0x282c,
936 		.enable_mask = BIT(11),
937 		.hw.init = &(struct clk_init_data){
938 			.name = "sdc1_src",
939 			.parent_names = gcc_cxo_pll8,
940 			.num_parents = 2,
941 			.ops = &clk_rcg_ops,
942 		},
943 	}
944 };
945 
946 static struct clk_branch sdc1_clk = {
947 	.halt_reg = 0x2fc8,
948 	.halt_bit = 6,
949 	.clkr = {
950 		.enable_reg = 0x282c,
951 		.enable_mask = BIT(9),
952 		.hw.init = &(struct clk_init_data){
953 			.name = "sdc1_clk",
954 			.parent_names = (const char *[]){ "sdc1_src" },
955 			.num_parents = 1,
956 			.ops = &clk_branch_ops,
957 			.flags = CLK_SET_RATE_PARENT,
958 		},
959 	},
960 };
961 
962 static struct clk_rcg sdc2_src = {
963 	.ns_reg = 0x284c,
964 	.md_reg = 0x2848,
965 	.mn = {
966 		.mnctr_en_bit = 8,
967 		.mnctr_reset_bit = 7,
968 		.mnctr_mode_shift = 5,
969 		.n_val_shift = 16,
970 		.m_val_shift = 16,
971 		.width = 8,
972 	},
973 	.p = {
974 		.pre_div_shift = 3,
975 		.pre_div_width = 2,
976 	},
977 	.s = {
978 		.src_sel_shift = 0,
979 		.parent_map = gcc_cxo_pll8_map,
980 	},
981 	.freq_tbl = clk_tbl_sdc,
982 	.clkr = {
983 		.enable_reg = 0x284c,
984 		.enable_mask = BIT(11),
985 		.hw.init = &(struct clk_init_data){
986 			.name = "sdc2_src",
987 			.parent_names = gcc_cxo_pll8,
988 			.num_parents = 2,
989 			.ops = &clk_rcg_ops,
990 		},
991 	}
992 };
993 
994 static struct clk_branch sdc2_clk = {
995 	.halt_reg = 0x2fc8,
996 	.halt_bit = 5,
997 	.clkr = {
998 		.enable_reg = 0x284c,
999 		.enable_mask = BIT(9),
1000 		.hw.init = &(struct clk_init_data){
1001 			.name = "sdc2_clk",
1002 			.parent_names = (const char *[]){ "sdc2_src" },
1003 			.num_parents = 1,
1004 			.ops = &clk_branch_ops,
1005 			.flags = CLK_SET_RATE_PARENT,
1006 		},
1007 	},
1008 };
1009 
1010 static const struct freq_tbl clk_tbl_usb[] = {
1011 	{ 60000000, P_PLL8, 1, 5, 32 },
1012 	{ }
1013 };
1014 
1015 static struct clk_rcg usb_hs1_xcvr_src = {
1016 	.ns_reg = 0x290c,
1017 	.md_reg = 0x2908,
1018 	.mn = {
1019 		.mnctr_en_bit = 8,
1020 		.mnctr_reset_bit = 7,
1021 		.mnctr_mode_shift = 5,
1022 		.n_val_shift = 16,
1023 		.m_val_shift = 16,
1024 		.width = 8,
1025 	},
1026 	.p = {
1027 		.pre_div_shift = 3,
1028 		.pre_div_width = 2,
1029 	},
1030 	.s = {
1031 		.src_sel_shift = 0,
1032 		.parent_map = gcc_cxo_pll8_map,
1033 	},
1034 	.freq_tbl = clk_tbl_usb,
1035 	.clkr = {
1036 		.enable_reg = 0x290c,
1037 		.enable_mask = BIT(11),
1038 		.hw.init = &(struct clk_init_data){
1039 			.name = "usb_hs1_xcvr_src",
1040 			.parent_names = gcc_cxo_pll8,
1041 			.num_parents = 2,
1042 			.ops = &clk_rcg_ops,
1043 			.flags = CLK_SET_RATE_GATE,
1044 		},
1045 	}
1046 };
1047 
1048 static struct clk_branch usb_hs1_xcvr_clk = {
1049 	.halt_reg = 0x2fc8,
1050 	.halt_bit = 0,
1051 	.clkr = {
1052 		.enable_reg = 0x290c,
1053 		.enable_mask = BIT(9),
1054 		.hw.init = &(struct clk_init_data){
1055 			.name = "usb_hs1_xcvr_clk",
1056 			.parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
1057 			.num_parents = 1,
1058 			.ops = &clk_branch_ops,
1059 			.flags = CLK_SET_RATE_PARENT,
1060 		},
1061 	},
1062 };
1063 
1064 static struct clk_rcg usb_hsic_xcvr_fs_src = {
1065 	.ns_reg = 0x2928,
1066 	.md_reg = 0x2924,
1067 	.mn = {
1068 		.mnctr_en_bit = 8,
1069 		.mnctr_reset_bit = 7,
1070 		.mnctr_mode_shift = 5,
1071 		.n_val_shift = 16,
1072 		.m_val_shift = 16,
1073 		.width = 8,
1074 	},
1075 	.p = {
1076 		.pre_div_shift = 3,
1077 		.pre_div_width = 2,
1078 	},
1079 	.s = {
1080 		.src_sel_shift = 0,
1081 		.parent_map = gcc_cxo_pll8_map,
1082 	},
1083 	.freq_tbl = clk_tbl_usb,
1084 	.clkr = {
1085 		.enable_reg = 0x2928,
1086 		.enable_mask = BIT(11),
1087 		.hw.init = &(struct clk_init_data){
1088 			.name = "usb_hsic_xcvr_fs_src",
1089 			.parent_names = gcc_cxo_pll8,
1090 			.num_parents = 2,
1091 			.ops = &clk_rcg_ops,
1092 			.flags = CLK_SET_RATE_GATE,
1093 		},
1094 	}
1095 };
1096 
1097 static struct clk_branch usb_hsic_xcvr_fs_clk = {
1098 	.halt_reg = 0x2fc8,
1099 	.halt_bit = 9,
1100 	.clkr = {
1101 		.enable_reg = 0x2928,
1102 		.enable_mask = BIT(9),
1103 		.hw.init = &(struct clk_init_data){
1104 			.name = "usb_hsic_xcvr_fs_clk",
1105 			.parent_names =
1106 				(const char *[]){ "usb_hsic_xcvr_fs_src" },
1107 			.num_parents = 1,
1108 			.ops = &clk_branch_ops,
1109 			.flags = CLK_SET_RATE_PARENT,
1110 		},
1111 	},
1112 };
1113 
1114 static const struct freq_tbl clk_tbl_usb_hs1_system[] = {
1115 	{ 60000000, P_PLL8, 1, 5, 32 },
1116 	{ }
1117 };
1118 
1119 static struct clk_rcg usb_hs1_system_src = {
1120 	.ns_reg = 0x36a4,
1121 	.md_reg = 0x36a0,
1122 	.mn = {
1123 		.mnctr_en_bit = 8,
1124 		.mnctr_reset_bit = 7,
1125 		.mnctr_mode_shift = 5,
1126 		.n_val_shift = 16,
1127 		.m_val_shift = 16,
1128 		.width = 8,
1129 	},
1130 	.p = {
1131 		.pre_div_shift = 3,
1132 		.pre_div_width = 2,
1133 	},
1134 	.s = {
1135 		.src_sel_shift = 0,
1136 		.parent_map = gcc_cxo_pll8_map,
1137 	},
1138 	.freq_tbl = clk_tbl_usb_hs1_system,
1139 	.clkr = {
1140 		.enable_reg = 0x36a4,
1141 		.enable_mask = BIT(11),
1142 		.hw.init = &(struct clk_init_data){
1143 			.name = "usb_hs1_system_src",
1144 			.parent_names = gcc_cxo_pll8,
1145 			.num_parents = 2,
1146 			.ops = &clk_rcg_ops,
1147 			.flags = CLK_SET_RATE_GATE,
1148 		},
1149 	}
1150 };
1151 
1152 static struct clk_branch usb_hs1_system_clk = {
1153 	.halt_reg = 0x2fc8,
1154 	.halt_bit = 4,
1155 	.clkr = {
1156 		.enable_reg = 0x36a4,
1157 		.enable_mask = BIT(9),
1158 		.hw.init = &(struct clk_init_data){
1159 			.parent_names =
1160 				(const char *[]){ "usb_hs1_system_src" },
1161 			.num_parents = 1,
1162 			.name = "usb_hs1_system_clk",
1163 			.ops = &clk_branch_ops,
1164 			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1165 		},
1166 	},
1167 };
1168 
1169 static const struct freq_tbl clk_tbl_usb_hsic_system[] = {
1170 	{ 64000000, P_PLL8, 1, 1, 6 },
1171 	{ }
1172 };
1173 
1174 static struct clk_rcg usb_hsic_system_src = {
1175 	.ns_reg = 0x2b58,
1176 	.md_reg = 0x2b54,
1177 	.mn = {
1178 		.mnctr_en_bit = 8,
1179 		.mnctr_reset_bit = 7,
1180 		.mnctr_mode_shift = 5,
1181 		.n_val_shift = 16,
1182 		.m_val_shift = 16,
1183 		.width = 8,
1184 	},
1185 	.p = {
1186 		.pre_div_shift = 3,
1187 		.pre_div_width = 2,
1188 	},
1189 	.s = {
1190 		.src_sel_shift = 0,
1191 		.parent_map = gcc_cxo_pll8_map,
1192 	},
1193 	.freq_tbl = clk_tbl_usb_hsic_system,
1194 	.clkr = {
1195 		.enable_reg = 0x2b58,
1196 		.enable_mask = BIT(11),
1197 		.hw.init = &(struct clk_init_data){
1198 			.name = "usb_hsic_system_src",
1199 			.parent_names = gcc_cxo_pll8,
1200 			.num_parents = 2,
1201 			.ops = &clk_rcg_ops,
1202 			.flags = CLK_SET_RATE_GATE,
1203 		},
1204 	}
1205 };
1206 
1207 static struct clk_branch usb_hsic_system_clk = {
1208 	.halt_reg = 0x2fc8,
1209 	.halt_bit = 7,
1210 	.clkr = {
1211 		.enable_reg = 0x2b58,
1212 		.enable_mask = BIT(9),
1213 		.hw.init = &(struct clk_init_data){
1214 			.parent_names =
1215 				(const char *[]){ "usb_hsic_system_src" },
1216 			.num_parents = 1,
1217 			.name = "usb_hsic_system_clk",
1218 			.ops = &clk_branch_ops,
1219 			.flags = CLK_SET_RATE_PARENT,
1220 		},
1221 	},
1222 };
1223 
1224 static const struct freq_tbl clk_tbl_usb_hsic_hsic[] = {
1225 	{ 48000000, P_PLL14, 1, 0, 0 },
1226 	{ }
1227 };
1228 
1229 static struct clk_rcg usb_hsic_hsic_src = {
1230 	.ns_reg = 0x2b50,
1231 	.md_reg = 0x2b4c,
1232 	.mn = {
1233 		.mnctr_en_bit = 8,
1234 		.mnctr_reset_bit = 7,
1235 		.mnctr_mode_shift = 5,
1236 		.n_val_shift = 16,
1237 		.m_val_shift = 16,
1238 		.width = 8,
1239 	},
1240 	.p = {
1241 		.pre_div_shift = 3,
1242 		.pre_div_width = 2,
1243 	},
1244 	.s = {
1245 		.src_sel_shift = 0,
1246 		.parent_map = gcc_cxo_pll14_map,
1247 	},
1248 	.freq_tbl = clk_tbl_usb_hsic_hsic,
1249 	.clkr = {
1250 		.enable_reg = 0x2b50,
1251 		.enable_mask = BIT(11),
1252 		.hw.init = &(struct clk_init_data){
1253 			.name = "usb_hsic_hsic_src",
1254 			.parent_names = gcc_cxo_pll14,
1255 			.num_parents = 2,
1256 			.ops = &clk_rcg_ops,
1257 			.flags = CLK_SET_RATE_GATE,
1258 		},
1259 	}
1260 };
1261 
1262 static struct clk_branch usb_hsic_hsic_clk = {
1263 	.halt_check = BRANCH_HALT_DELAY,
1264 	.clkr = {
1265 		.enable_reg = 0x2b50,
1266 		.enable_mask = BIT(9),
1267 		.hw.init = &(struct clk_init_data){
1268 			.parent_names = (const char *[]){ "usb_hsic_hsic_src" },
1269 			.num_parents = 1,
1270 			.name = "usb_hsic_hsic_clk",
1271 			.ops = &clk_branch_ops,
1272 			.flags = CLK_SET_RATE_PARENT,
1273 		},
1274 	},
1275 };
1276 
1277 static struct clk_branch usb_hsic_hsio_cal_clk = {
1278 	.halt_reg = 0x2fc8,
1279 	.halt_bit = 8,
1280 	.clkr = {
1281 		.enable_reg = 0x2b48,
1282 		.enable_mask = BIT(0),
1283 		.hw.init = &(struct clk_init_data){
1284 			.parent_names = (const char *[]){ "cxo" },
1285 			.num_parents = 1,
1286 			.name = "usb_hsic_hsio_cal_clk",
1287 			.ops = &clk_branch_ops,
1288 		},
1289 	},
1290 };
1291 
1292 static struct clk_branch ce1_core_clk = {
1293 	.hwcg_reg = 0x2724,
1294 	.hwcg_bit = 6,
1295 	.halt_reg = 0x2fd4,
1296 	.halt_bit = 27,
1297 	.clkr = {
1298 		.enable_reg = 0x2724,
1299 		.enable_mask = BIT(4),
1300 		.hw.init = &(struct clk_init_data){
1301 			.name = "ce1_core_clk",
1302 			.ops = &clk_branch_ops,
1303 		},
1304 	},
1305 };
1306 
1307 static struct clk_branch ce1_h_clk = {
1308 	.halt_reg = 0x2fd4,
1309 	.halt_bit = 1,
1310 	.clkr = {
1311 		.enable_reg = 0x2720,
1312 		.enable_mask = BIT(4),
1313 		.hw.init = &(struct clk_init_data){
1314 			.name = "ce1_h_clk",
1315 			.ops = &clk_branch_ops,
1316 		},
1317 	},
1318 };
1319 
1320 static struct clk_branch dma_bam_h_clk = {
1321 	.hwcg_reg = 0x25c0,
1322 	.hwcg_bit = 6,
1323 	.halt_reg = 0x2fc8,
1324 	.halt_bit = 12,
1325 	.clkr = {
1326 		.enable_reg = 0x25c0,
1327 		.enable_mask = BIT(4),
1328 		.hw.init = &(struct clk_init_data){
1329 			.name = "dma_bam_h_clk",
1330 			.ops = &clk_branch_ops,
1331 		},
1332 	},
1333 };
1334 
1335 static struct clk_branch gsbi1_h_clk = {
1336 	.hwcg_reg = 0x29c0,
1337 	.hwcg_bit = 6,
1338 	.halt_reg = 0x2fcc,
1339 	.halt_bit = 11,
1340 	.clkr = {
1341 		.enable_reg = 0x29c0,
1342 		.enable_mask = BIT(4),
1343 		.hw.init = &(struct clk_init_data){
1344 			.name = "gsbi1_h_clk",
1345 			.ops = &clk_branch_ops,
1346 		},
1347 	},
1348 };
1349 
1350 static struct clk_branch gsbi2_h_clk = {
1351 	.hwcg_reg = 0x29e0,
1352 	.hwcg_bit = 6,
1353 	.halt_reg = 0x2fcc,
1354 	.halt_bit = 7,
1355 	.clkr = {
1356 		.enable_reg = 0x29e0,
1357 		.enable_mask = BIT(4),
1358 		.hw.init = &(struct clk_init_data){
1359 			.name = "gsbi2_h_clk",
1360 			.ops = &clk_branch_ops,
1361 		},
1362 	},
1363 };
1364 
1365 static struct clk_branch gsbi3_h_clk = {
1366 	.hwcg_reg = 0x2a00,
1367 	.hwcg_bit = 6,
1368 	.halt_reg = 0x2fcc,
1369 	.halt_bit = 3,
1370 	.clkr = {
1371 		.enable_reg = 0x2a00,
1372 		.enable_mask = BIT(4),
1373 		.hw.init = &(struct clk_init_data){
1374 			.name = "gsbi3_h_clk",
1375 			.ops = &clk_branch_ops,
1376 		},
1377 	},
1378 };
1379 
1380 static struct clk_branch gsbi4_h_clk = {
1381 	.hwcg_reg = 0x2a20,
1382 	.hwcg_bit = 6,
1383 	.halt_reg = 0x2fd0,
1384 	.halt_bit = 27,
1385 	.clkr = {
1386 		.enable_reg = 0x2a20,
1387 		.enable_mask = BIT(4),
1388 		.hw.init = &(struct clk_init_data){
1389 			.name = "gsbi4_h_clk",
1390 			.ops = &clk_branch_ops,
1391 		},
1392 	},
1393 };
1394 
1395 static struct clk_branch gsbi5_h_clk = {
1396 	.hwcg_reg = 0x2a40,
1397 	.hwcg_bit = 6,
1398 	.halt_reg = 0x2fd0,
1399 	.halt_bit = 23,
1400 	.clkr = {
1401 		.enable_reg = 0x2a40,
1402 		.enable_mask = BIT(4),
1403 		.hw.init = &(struct clk_init_data){
1404 			.name = "gsbi5_h_clk",
1405 			.ops = &clk_branch_ops,
1406 		},
1407 	},
1408 };
1409 
1410 static struct clk_branch usb_hs1_h_clk = {
1411 	.hwcg_reg = 0x2900,
1412 	.hwcg_bit = 6,
1413 	.halt_reg = 0x2fc8,
1414 	.halt_bit = 1,
1415 	.clkr = {
1416 		.enable_reg = 0x2900,
1417 		.enable_mask = BIT(4),
1418 		.hw.init = &(struct clk_init_data){
1419 			.name = "usb_hs1_h_clk",
1420 			.ops = &clk_branch_ops,
1421 		},
1422 	},
1423 };
1424 
1425 static struct clk_branch usb_hsic_h_clk = {
1426 	.halt_reg = 0x2fcc,
1427 	.halt_bit = 28,
1428 	.clkr = {
1429 		.enable_reg = 0x2920,
1430 		.enable_mask = BIT(4),
1431 		.hw.init = &(struct clk_init_data){
1432 			.name = "usb_hsic_h_clk",
1433 			.ops = &clk_branch_ops,
1434 		},
1435 	},
1436 };
1437 
1438 static struct clk_branch sdc1_h_clk = {
1439 	.hwcg_reg = 0x2820,
1440 	.hwcg_bit = 6,
1441 	.halt_reg = 0x2fc8,
1442 	.halt_bit = 11,
1443 	.clkr = {
1444 		.enable_reg = 0x2820,
1445 		.enable_mask = BIT(4),
1446 		.hw.init = &(struct clk_init_data){
1447 			.name = "sdc1_h_clk",
1448 			.ops = &clk_branch_ops,
1449 		},
1450 	},
1451 };
1452 
1453 static struct clk_branch sdc2_h_clk = {
1454 	.hwcg_reg = 0x2840,
1455 	.hwcg_bit = 6,
1456 	.halt_reg = 0x2fc8,
1457 	.halt_bit = 10,
1458 	.clkr = {
1459 		.enable_reg = 0x2840,
1460 		.enable_mask = BIT(4),
1461 		.hw.init = &(struct clk_init_data){
1462 			.name = "sdc2_h_clk",
1463 			.ops = &clk_branch_ops,
1464 		},
1465 	},
1466 };
1467 
1468 static struct clk_branch adm0_clk = {
1469 	.halt_reg = 0x2fdc,
1470 	.halt_check = BRANCH_HALT_VOTED,
1471 	.halt_bit = 14,
1472 	.clkr = {
1473 		.enable_reg = 0x3080,
1474 		.enable_mask = BIT(2),
1475 		.hw.init = &(struct clk_init_data){
1476 			.name = "adm0_clk",
1477 			.ops = &clk_branch_ops,
1478 		},
1479 	},
1480 };
1481 
1482 static struct clk_branch adm0_pbus_clk = {
1483 	.hwcg_reg = 0x2208,
1484 	.hwcg_bit = 6,
1485 	.halt_reg = 0x2fdc,
1486 	.halt_check = BRANCH_HALT_VOTED,
1487 	.halt_bit = 13,
1488 	.clkr = {
1489 		.enable_reg = 0x3080,
1490 		.enable_mask = BIT(3),
1491 		.hw.init = &(struct clk_init_data){
1492 			.name = "adm0_pbus_clk",
1493 			.ops = &clk_branch_ops,
1494 		},
1495 	},
1496 };
1497 
1498 static struct clk_branch pmic_arb0_h_clk = {
1499 	.halt_reg = 0x2fd8,
1500 	.halt_check = BRANCH_HALT_VOTED,
1501 	.halt_bit = 22,
1502 	.clkr = {
1503 		.enable_reg = 0x3080,
1504 		.enable_mask = BIT(8),
1505 		.hw.init = &(struct clk_init_data){
1506 			.name = "pmic_arb0_h_clk",
1507 			.ops = &clk_branch_ops,
1508 		},
1509 	},
1510 };
1511 
1512 static struct clk_branch pmic_arb1_h_clk = {
1513 	.halt_reg = 0x2fd8,
1514 	.halt_check = BRANCH_HALT_VOTED,
1515 	.halt_bit = 21,
1516 	.clkr = {
1517 		.enable_reg = 0x3080,
1518 		.enable_mask = BIT(9),
1519 		.hw.init = &(struct clk_init_data){
1520 			.name = "pmic_arb1_h_clk",
1521 			.ops = &clk_branch_ops,
1522 		},
1523 	},
1524 };
1525 
1526 static struct clk_branch pmic_ssbi2_clk = {
1527 	.halt_reg = 0x2fd8,
1528 	.halt_check = BRANCH_HALT_VOTED,
1529 	.halt_bit = 23,
1530 	.clkr = {
1531 		.enable_reg = 0x3080,
1532 		.enable_mask = BIT(7),
1533 		.hw.init = &(struct clk_init_data){
1534 			.name = "pmic_ssbi2_clk",
1535 			.ops = &clk_branch_ops,
1536 		},
1537 	},
1538 };
1539 
1540 static struct clk_branch rpm_msg_ram_h_clk = {
1541 	.hwcg_reg = 0x27e0,
1542 	.hwcg_bit = 6,
1543 	.halt_reg = 0x2fd8,
1544 	.halt_check = BRANCH_HALT_VOTED,
1545 	.halt_bit = 12,
1546 	.clkr = {
1547 		.enable_reg = 0x3080,
1548 		.enable_mask = BIT(6),
1549 		.hw.init = &(struct clk_init_data){
1550 			.name = "rpm_msg_ram_h_clk",
1551 			.ops = &clk_branch_ops,
1552 		},
1553 	},
1554 };
1555 
1556 static struct clk_branch ebi2_clk = {
1557 	.hwcg_reg = 0x2664,
1558 	.hwcg_bit = 6,
1559 	.halt_reg = 0x2fcc,
1560 	.halt_bit = 24,
1561 	.clkr = {
1562 		.enable_reg = 0x2664,
1563 		.enable_mask = BIT(6) | BIT(4),
1564 		.hw.init = &(struct clk_init_data){
1565 			.name = "ebi2_clk",
1566 			.ops = &clk_branch_ops,
1567 		},
1568 	},
1569 };
1570 
1571 static struct clk_branch ebi2_aon_clk = {
1572 	.halt_reg = 0x2fcc,
1573 	.halt_bit = 23,
1574 	.clkr = {
1575 		.enable_reg = 0x2664,
1576 		.enable_mask = BIT(8),
1577 		.hw.init = &(struct clk_init_data){
1578 			.name = "ebi2_aon_clk",
1579 			.ops = &clk_branch_ops,
1580 		},
1581 	},
1582 };
1583 
1584 static struct clk_hw *gcc_mdm9615_hws[] = {
1585 	&cxo.hw,
1586 };
1587 
1588 static struct clk_regmap *gcc_mdm9615_clks[] = {
1589 	[PLL0] = &pll0.clkr,
1590 	[PLL0_VOTE] = &pll0_vote,
1591 	[PLL4_VOTE] = &pll4_vote,
1592 	[PLL8] = &pll8.clkr,
1593 	[PLL8_VOTE] = &pll8_vote,
1594 	[PLL14] = &pll14.clkr,
1595 	[PLL14_VOTE] = &pll14_vote,
1596 	[GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
1597 	[GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
1598 	[GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
1599 	[GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
1600 	[GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
1601 	[GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
1602 	[GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
1603 	[GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
1604 	[GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
1605 	[GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
1606 	[GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
1607 	[GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
1608 	[GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
1609 	[GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
1610 	[GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
1611 	[GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
1612 	[GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
1613 	[GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
1614 	[GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
1615 	[GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
1616 	[GP0_SRC] = &gp0_src.clkr,
1617 	[GP0_CLK] = &gp0_clk.clkr,
1618 	[GP1_SRC] = &gp1_src.clkr,
1619 	[GP1_CLK] = &gp1_clk.clkr,
1620 	[GP2_SRC] = &gp2_src.clkr,
1621 	[GP2_CLK] = &gp2_clk.clkr,
1622 	[PMEM_A_CLK] = &pmem_clk.clkr,
1623 	[PRNG_SRC] = &prng_src.clkr,
1624 	[PRNG_CLK] = &prng_clk.clkr,
1625 	[SDC1_SRC] = &sdc1_src.clkr,
1626 	[SDC1_CLK] = &sdc1_clk.clkr,
1627 	[SDC2_SRC] = &sdc2_src.clkr,
1628 	[SDC2_CLK] = &sdc2_clk.clkr,
1629 	[USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
1630 	[USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
1631 	[USB_HS1_SYSTEM_CLK_SRC] = &usb_hs1_system_src.clkr,
1632 	[USB_HS1_SYSTEM_CLK] = &usb_hs1_system_clk.clkr,
1633 	[USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
1634 	[USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
1635 	[USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_src.clkr,
1636 	[USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
1637 	[USB_HSIC_HSIC_CLK_SRC] = &usb_hsic_hsic_src.clkr,
1638 	[USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
1639 	[USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
1640 	[CE1_CORE_CLK] = &ce1_core_clk.clkr,
1641 	[CE1_H_CLK] = &ce1_h_clk.clkr,
1642 	[DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
1643 	[GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
1644 	[GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
1645 	[GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
1646 	[GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
1647 	[GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
1648 	[USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
1649 	[USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
1650 	[SDC1_H_CLK] = &sdc1_h_clk.clkr,
1651 	[SDC2_H_CLK] = &sdc2_h_clk.clkr,
1652 	[ADM0_CLK] = &adm0_clk.clkr,
1653 	[ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
1654 	[PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
1655 	[PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
1656 	[PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
1657 	[RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
1658 	[EBI2_CLK] = &ebi2_clk.clkr,
1659 	[EBI2_AON_CLK] = &ebi2_aon_clk.clkr,
1660 };
1661 
1662 static const struct qcom_reset_map gcc_mdm9615_resets[] = {
1663 	[DMA_BAM_RESET] = { 0x25c0, 7 },
1664 	[CE1_H_RESET] = { 0x2720, 7 },
1665 	[CE1_CORE_RESET] = { 0x2724, 7 },
1666 	[SDC1_RESET] = { 0x2830 },
1667 	[SDC2_RESET] = { 0x2850 },
1668 	[ADM0_C2_RESET] = { 0x220c, 4 },
1669 	[ADM0_C1_RESET] = { 0x220c, 3 },
1670 	[ADM0_C0_RESET] = { 0x220c, 2 },
1671 	[ADM0_PBUS_RESET] = { 0x220c, 1 },
1672 	[ADM0_RESET] = { 0x220c },
1673 	[USB_HS1_RESET] = { 0x2910 },
1674 	[USB_HSIC_RESET] = { 0x2934 },
1675 	[GSBI1_RESET] = { 0x29dc },
1676 	[GSBI2_RESET] = { 0x29fc },
1677 	[GSBI3_RESET] = { 0x2a1c },
1678 	[GSBI4_RESET] = { 0x2a3c },
1679 	[GSBI5_RESET] = { 0x2a5c },
1680 	[PDM_RESET] = { 0x2CC0, 12 },
1681 };
1682 
1683 static const struct regmap_config gcc_mdm9615_regmap_config = {
1684 	.reg_bits	= 32,
1685 	.reg_stride	= 4,
1686 	.val_bits	= 32,
1687 	.max_register	= 0x3660,
1688 	.fast_io	= true,
1689 };
1690 
1691 static const struct qcom_cc_desc gcc_mdm9615_desc = {
1692 	.config = &gcc_mdm9615_regmap_config,
1693 	.clks = gcc_mdm9615_clks,
1694 	.num_clks = ARRAY_SIZE(gcc_mdm9615_clks),
1695 	.resets = gcc_mdm9615_resets,
1696 	.num_resets = ARRAY_SIZE(gcc_mdm9615_resets),
1697 	.clk_hws = gcc_mdm9615_hws,
1698 	.num_clk_hws = ARRAY_SIZE(gcc_mdm9615_hws),
1699 };
1700 
1701 static const struct of_device_id gcc_mdm9615_match_table[] = {
1702 	{ .compatible = "qcom,gcc-mdm9615" },
1703 	{ }
1704 };
1705 MODULE_DEVICE_TABLE(of, gcc_mdm9615_match_table);
1706 
gcc_mdm9615_probe(struct platform_device * pdev)1707 static int gcc_mdm9615_probe(struct platform_device *pdev)
1708 {
1709 	struct regmap *regmap;
1710 
1711 	regmap = qcom_cc_map(pdev, &gcc_mdm9615_desc);
1712 	if (IS_ERR(regmap))
1713 		return PTR_ERR(regmap);
1714 
1715 	return qcom_cc_really_probe(pdev, &gcc_mdm9615_desc, regmap);
1716 }
1717 
1718 static struct platform_driver gcc_mdm9615_driver = {
1719 	.probe		= gcc_mdm9615_probe,
1720 	.driver		= {
1721 		.name	= "gcc-mdm9615",
1722 		.of_match_table = gcc_mdm9615_match_table,
1723 	},
1724 };
1725 
gcc_mdm9615_init(void)1726 static int __init gcc_mdm9615_init(void)
1727 {
1728 	return platform_driver_register(&gcc_mdm9615_driver);
1729 }
1730 core_initcall(gcc_mdm9615_init);
1731 
gcc_mdm9615_exit(void)1732 static void __exit gcc_mdm9615_exit(void)
1733 {
1734 	platform_driver_unregister(&gcc_mdm9615_driver);
1735 }
1736 module_exit(gcc_mdm9615_exit);
1737 
1738 MODULE_DESCRIPTION("QCOM GCC MDM9615 Driver");
1739 MODULE_LICENSE("GPL v2");
1740 MODULE_ALIAS("platform:gcc-mdm9615");
1741