1 /*
2  * AM43XX Clock init
3  *
4  * Copyright (C) 2013 Texas Instruments, Inc
5  *     Tero Kristo (t-kristo@ti.com)
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation version 2.
10  *
11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12  * kind, whether express or implied; without even the implied warranty
13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  */
16 
17 #include <linux/kernel.h>
18 #include <linux/list.h>
19 #include <linux/clk.h>
20 #include <linux/clk-provider.h>
21 #include <linux/clk/ti.h>
22 #include <dt-bindings/clock/am4.h>
23 
24 #include "clock.h"
25 
26 static const char * const am4_synctimer_32kclk_parents[] __initconst = {
27 	"mux_synctimer32k_ck",
28 	NULL,
29 };
30 
31 static const struct omap_clkctrl_bit_data am4_counter_32k_bit_data[] __initconst = {
32 	{ 8, TI_CLK_GATE, am4_synctimer_32kclk_parents, NULL },
33 	{ 0 },
34 };
35 
36 static const char * const am4_gpio0_dbclk_parents[] __initconst = {
37 	"gpio0_dbclk_mux_ck",
38 	NULL,
39 };
40 
41 static const struct omap_clkctrl_bit_data am4_gpio1_bit_data[] __initconst = {
42 	{ 8, TI_CLK_GATE, am4_gpio0_dbclk_parents, NULL },
43 	{ 0 },
44 };
45 
46 static const struct omap_clkctrl_reg_data am4_l4_wkup_clkctrl_regs[] __initconst = {
47 	{ AM4_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck", "l3s_tsc_clkdm" },
48 	{ AM4_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
49 	{ AM4_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "sys_clkin_ck" },
50 	{ AM4_COUNTER_32K_CLKCTRL, am4_counter_32k_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0210:8" },
51 	{ AM4_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck", "l4_wkup_clkdm" },
52 	{ AM4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck", "l4_wkup_clkdm" },
53 	{ AM4_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck", "l4_wkup_clkdm" },
54 	{ AM4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck", "l4_wkup_clkdm" },
55 	{ AM4_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck", "l4_wkup_clkdm" },
56 	{ AM4_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck", "l4_wkup_clkdm" },
57 	{ AM4_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
58 	{ AM4_GPIO1_CLKCTRL, am4_gpio1_bit_data, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
59 	{ 0 },
60 };
61 
62 static const struct omap_clkctrl_reg_data am4_mpu_clkctrl_regs[] __initconst = {
63 	{ AM4_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
64 	{ 0 },
65 };
66 
67 static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = {
68 	{ AM4_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
69 	{ 0 },
70 };
71 
72 static const struct omap_clkctrl_reg_data am4_l4_rtc_clkctrl_regs[] __initconst = {
73 	{ AM4_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
74 	{ 0 },
75 };
76 
77 static const char * const am4_usb_otg_ss0_refclk960m_parents[] __initconst = {
78 	"dpll_per_clkdcoldo",
79 	NULL,
80 };
81 
82 static const struct omap_clkctrl_bit_data am4_usb_otg_ss0_bit_data[] __initconst = {
83 	{ 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
84 	{ 0 },
85 };
86 
87 static const struct omap_clkctrl_bit_data am4_usb_otg_ss1_bit_data[] __initconst = {
88 	{ 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
89 	{ 0 },
90 };
91 
92 static const char * const am4_gpio1_dbclk_parents[] __initconst = {
93 	"clkdiv32k_ick",
94 	NULL,
95 };
96 
97 static const struct omap_clkctrl_bit_data am4_gpio2_bit_data[] __initconst = {
98 	{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
99 	{ 0 },
100 };
101 
102 static const struct omap_clkctrl_bit_data am4_gpio3_bit_data[] __initconst = {
103 	{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
104 	{ 0 },
105 };
106 
107 static const struct omap_clkctrl_bit_data am4_gpio4_bit_data[] __initconst = {
108 	{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
109 	{ 0 },
110 };
111 
112 static const struct omap_clkctrl_bit_data am4_gpio5_bit_data[] __initconst = {
113 	{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
114 	{ 0 },
115 };
116 
117 static const struct omap_clkctrl_bit_data am4_gpio6_bit_data[] __initconst = {
118 	{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
119 	{ 0 },
120 };
121 
122 static const struct omap_clkctrl_reg_data am4_l4_per_clkctrl_regs[] __initconst = {
123 	{ AM4_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
124 	{ AM4_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" },
125 	{ AM4_DES_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
126 	{ AM4_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
127 	{ AM4_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
128 	{ AM4_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
129 	{ AM4_VPFE0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3s_clkdm" },
130 	{ AM4_VPFE1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3s_clkdm" },
131 	{ AM4_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
132 	{ AM4_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
133 	{ AM4_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
134 	{ AM4_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
135 	{ AM4_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l3_clkdm" },
136 	{ AM4_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
137 	{ AM4_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" },
138 	{ AM4_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" },
139 	{ AM4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" },
140 	{ AM4_QSPI_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
141 	{ AM4_USB_OTG_SS0_CLKCTRL, am4_usb_otg_ss0_bit_data, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
142 	{ AM4_USB_OTG_SS1_CLKCTRL, am4_usb_otg_ss1_bit_data, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
143 	{ AM4_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" },
144 	{ AM4_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
145 	{ AM4_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
146 	{ AM4_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
147 	{ AM4_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
148 	{ AM4_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
149 	{ AM4_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
150 	{ AM4_EPWMSS3_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
151 	{ AM4_EPWMSS4_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
152 	{ AM4_EPWMSS5_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
153 	{ AM4_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
154 	{ AM4_GPIO2_CLKCTRL, am4_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
155 	{ AM4_GPIO3_CLKCTRL, am4_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
156 	{ AM4_GPIO4_CLKCTRL, am4_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
157 	{ AM4_GPIO5_CLKCTRL, am4_gpio5_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
158 	{ AM4_GPIO6_CLKCTRL, am4_gpio6_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
159 	{ AM4_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_clk" },
160 	{ AM4_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
161 	{ AM4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
162 	{ AM4_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
163 	{ AM4_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
164 	{ AM4_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
165 	{ AM4_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
166 	{ AM4_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
167 	{ AM4_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
168 	{ AM4_SPI2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
169 	{ AM4_SPI3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
170 	{ AM4_SPI4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
171 	{ AM4_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
172 	{ AM4_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
173 	{ AM4_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
174 	{ AM4_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
175 	{ AM4_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
176 	{ AM4_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
177 	{ AM4_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
178 	{ AM4_TIMER8_CLKCTRL, NULL, CLKF_SW_SUP, "timer8_fck" },
179 	{ AM4_TIMER9_CLKCTRL, NULL, CLKF_SW_SUP, "timer9_fck" },
180 	{ AM4_TIMER10_CLKCTRL, NULL, CLKF_SW_SUP, "timer10_fck" },
181 	{ AM4_TIMER11_CLKCTRL, NULL, CLKF_SW_SUP, "timer11_fck" },
182 	{ AM4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
183 	{ AM4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
184 	{ AM4_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
185 	{ AM4_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
186 	{ AM4_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
187 	{ AM4_OCP2SCP0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
188 	{ AM4_OCP2SCP1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
189 	{ AM4_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_ck", "emif_clkdm" },
190 	{ AM4_DSS_CORE_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "disp_clk", "dss_clkdm" },
191 	{ AM4_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" },
192 	{ 0 },
193 };
194 
195 const struct omap_clkctrl_data am4_clkctrl_compat_data[] __initconst = {
196 	{ 0x44df2820, am4_l4_wkup_clkctrl_regs },
197 	{ 0x44df8320, am4_mpu_clkctrl_regs },
198 	{ 0x44df8420, am4_gfx_l3_clkctrl_regs },
199 	{ 0x44df8520, am4_l4_rtc_clkctrl_regs },
200 	{ 0x44df8820, am4_l4_per_clkctrl_regs },
201 	{ 0 },
202 };
203 
204 const struct omap_clkctrl_data am438x_clkctrl_compat_data[] __initconst = {
205 	{ 0x44df2820, am4_l4_wkup_clkctrl_regs },
206 	{ 0x44df8320, am4_mpu_clkctrl_regs },
207 	{ 0x44df8420, am4_gfx_l3_clkctrl_regs },
208 	{ 0x44df8820, am4_l4_per_clkctrl_regs },
209 	{ 0 },
210 };
211 
212 struct ti_dt_clk am43xx_compat_clks[] = {
213 	DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
214 	DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
215 	DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0348:8"),
216 	DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0458:8"),
217 	DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:0460:8"),
218 	DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:0468:8"),
219 	DT_CLK(NULL, "gpio4_dbclk", "l4_per_cm:0470:8"),
220 	DT_CLK(NULL, "gpio5_dbclk", "l4_per_cm:0478:8"),
221 	DT_CLK(NULL, "synctimer_32kclk", "l4_wkup_cm:0210:8"),
222 	DT_CLK(NULL, "usb_otg_ss0_refclk960m", "l4_per_cm:0240:8"),
223 	DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l4_per_cm:0248:8"),
224 	{ .node_name = NULL },
225 };
226