1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2019 David Lechner <david@lechnology.com>
4 *
5 * Counter driver for Texas Instruments Enhanced Quadrature Encoder Pulse (eQEP)
6 */
7
8 #include <linux/bitops.h>
9 #include <linux/counter.h>
10 #include <linux/kernel.h>
11 #include <linux/mod_devicetable.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regmap.h>
16 #include <linux/types.h>
17
18 /* 32-bit registers */
19 #define QPOSCNT 0x0
20 #define QPOSINIT 0x4
21 #define QPOSMAX 0x8
22 #define QPOSCMP 0xc
23 #define QPOSILAT 0x10
24 #define QPOSSLAT 0x14
25 #define QPOSLAT 0x18
26 #define QUTMR 0x1c
27 #define QUPRD 0x20
28
29 /* 16-bit registers */
30 #define QWDTMR 0x0 /* 0x24 */
31 #define QWDPRD 0x2 /* 0x26 */
32 #define QDECCTL 0x4 /* 0x28 */
33 #define QEPCTL 0x6 /* 0x2a */
34 #define QCAPCTL 0x8 /* 0x2c */
35 #define QPOSCTL 0xa /* 0x2e */
36 #define QEINT 0xc /* 0x30 */
37 #define QFLG 0xe /* 0x32 */
38 #define QCLR 0x10 /* 0x34 */
39 #define QFRC 0x12 /* 0x36 */
40 #define QEPSTS 0x14 /* 0x38 */
41 #define QCTMR 0x16 /* 0x3a */
42 #define QCPRD 0x18 /* 0x3c */
43 #define QCTMRLAT 0x1a /* 0x3e */
44 #define QCPRDLAT 0x1c /* 0x40 */
45
46 #define QDECCTL_QSRC_SHIFT 14
47 #define QDECCTL_QSRC GENMASK(15, 14)
48 #define QDECCTL_SOEN BIT(13)
49 #define QDECCTL_SPSEL BIT(12)
50 #define QDECCTL_XCR BIT(11)
51 #define QDECCTL_SWAP BIT(10)
52 #define QDECCTL_IGATE BIT(9)
53 #define QDECCTL_QAP BIT(8)
54 #define QDECCTL_QBP BIT(7)
55 #define QDECCTL_QIP BIT(6)
56 #define QDECCTL_QSP BIT(5)
57
58 #define QEPCTL_FREE_SOFT GENMASK(15, 14)
59 #define QEPCTL_PCRM GENMASK(13, 12)
60 #define QEPCTL_SEI GENMASK(11, 10)
61 #define QEPCTL_IEI GENMASK(9, 8)
62 #define QEPCTL_SWI BIT(7)
63 #define QEPCTL_SEL BIT(6)
64 #define QEPCTL_IEL GENMASK(5, 4)
65 #define QEPCTL_PHEN BIT(3)
66 #define QEPCTL_QCLM BIT(2)
67 #define QEPCTL_UTE BIT(1)
68 #define QEPCTL_WDE BIT(0)
69
70 /* EQEP Inputs */
71 enum {
72 TI_EQEP_SIGNAL_QEPA, /* QEPA/XCLK */
73 TI_EQEP_SIGNAL_QEPB, /* QEPB/XDIR */
74 };
75
76 /* Position Counter Input Modes */
77 enum ti_eqep_count_func {
78 TI_EQEP_COUNT_FUNC_QUAD_COUNT,
79 TI_EQEP_COUNT_FUNC_DIR_COUNT,
80 TI_EQEP_COUNT_FUNC_UP_COUNT,
81 TI_EQEP_COUNT_FUNC_DOWN_COUNT,
82 };
83
84 struct ti_eqep_cnt {
85 struct counter_device counter;
86 struct regmap *regmap32;
87 struct regmap *regmap16;
88 };
89
ti_eqep_count_read(struct counter_device * counter,struct counter_count * count,u64 * val)90 static int ti_eqep_count_read(struct counter_device *counter,
91 struct counter_count *count, u64 *val)
92 {
93 struct ti_eqep_cnt *priv = counter->priv;
94 u32 cnt;
95
96 regmap_read(priv->regmap32, QPOSCNT, &cnt);
97 *val = cnt;
98
99 return 0;
100 }
101
ti_eqep_count_write(struct counter_device * counter,struct counter_count * count,u64 val)102 static int ti_eqep_count_write(struct counter_device *counter,
103 struct counter_count *count, u64 val)
104 {
105 struct ti_eqep_cnt *priv = counter->priv;
106 u32 max;
107
108 regmap_read(priv->regmap32, QPOSMAX, &max);
109 if (val > max)
110 return -EINVAL;
111
112 return regmap_write(priv->regmap32, QPOSCNT, val);
113 }
114
ti_eqep_function_read(struct counter_device * counter,struct counter_count * count,enum counter_function * function)115 static int ti_eqep_function_read(struct counter_device *counter,
116 struct counter_count *count,
117 enum counter_function *function)
118 {
119 struct ti_eqep_cnt *priv = counter->priv;
120 u32 qdecctl;
121
122 regmap_read(priv->regmap16, QDECCTL, &qdecctl);
123
124 switch ((qdecctl & QDECCTL_QSRC) >> QDECCTL_QSRC_SHIFT) {
125 case TI_EQEP_COUNT_FUNC_QUAD_COUNT:
126 *function = COUNTER_FUNCTION_QUADRATURE_X4;
127 break;
128 case TI_EQEP_COUNT_FUNC_DIR_COUNT:
129 *function = COUNTER_FUNCTION_PULSE_DIRECTION;
130 break;
131 case TI_EQEP_COUNT_FUNC_UP_COUNT:
132 *function = COUNTER_FUNCTION_INCREASE;
133 break;
134 case TI_EQEP_COUNT_FUNC_DOWN_COUNT:
135 *function = COUNTER_FUNCTION_DECREASE;
136 break;
137 }
138
139 return 0;
140 }
141
ti_eqep_function_write(struct counter_device * counter,struct counter_count * count,enum counter_function function)142 static int ti_eqep_function_write(struct counter_device *counter,
143 struct counter_count *count,
144 enum counter_function function)
145 {
146 struct ti_eqep_cnt *priv = counter->priv;
147 enum ti_eqep_count_func qsrc;
148
149 switch (function) {
150 case COUNTER_FUNCTION_QUADRATURE_X4:
151 qsrc = TI_EQEP_COUNT_FUNC_QUAD_COUNT;
152 break;
153 case COUNTER_FUNCTION_PULSE_DIRECTION:
154 qsrc = TI_EQEP_COUNT_FUNC_DIR_COUNT;
155 break;
156 case COUNTER_FUNCTION_INCREASE:
157 qsrc = TI_EQEP_COUNT_FUNC_UP_COUNT;
158 break;
159 case COUNTER_FUNCTION_DECREASE:
160 qsrc = TI_EQEP_COUNT_FUNC_DOWN_COUNT;
161 break;
162 default:
163 /* should never reach this path */
164 return -EINVAL;
165 }
166
167 return regmap_write_bits(priv->regmap16, QDECCTL, QDECCTL_QSRC,
168 qsrc << QDECCTL_QSRC_SHIFT);
169 }
170
ti_eqep_action_read(struct counter_device * counter,struct counter_count * count,struct counter_synapse * synapse,enum counter_synapse_action * action)171 static int ti_eqep_action_read(struct counter_device *counter,
172 struct counter_count *count,
173 struct counter_synapse *synapse,
174 enum counter_synapse_action *action)
175 {
176 struct ti_eqep_cnt *priv = counter->priv;
177 enum counter_function function;
178 u32 qdecctl;
179 int err;
180
181 err = ti_eqep_function_read(counter, count, &function);
182 if (err)
183 return err;
184
185 switch (function) {
186 case COUNTER_FUNCTION_QUADRATURE_X4:
187 /* In quadrature mode, the rising and falling edge of both
188 * QEPA and QEPB trigger QCLK.
189 */
190 *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
191 return 0;
192 case COUNTER_FUNCTION_PULSE_DIRECTION:
193 /* In direction-count mode only rising edge of QEPA is counted
194 * and QEPB gives direction.
195 */
196 switch (synapse->signal->id) {
197 case TI_EQEP_SIGNAL_QEPA:
198 *action = COUNTER_SYNAPSE_ACTION_RISING_EDGE;
199 return 0;
200 case TI_EQEP_SIGNAL_QEPB:
201 *action = COUNTER_SYNAPSE_ACTION_NONE;
202 return 0;
203 default:
204 /* should never reach this path */
205 return -EINVAL;
206 }
207 case COUNTER_FUNCTION_INCREASE:
208 case COUNTER_FUNCTION_DECREASE:
209 /* In up/down-count modes only QEPA is counted and QEPB is not
210 * used.
211 */
212 switch (synapse->signal->id) {
213 case TI_EQEP_SIGNAL_QEPA:
214 err = regmap_read(priv->regmap16, QDECCTL, &qdecctl);
215 if (err)
216 return err;
217
218 if (qdecctl & QDECCTL_XCR)
219 *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
220 else
221 *action = COUNTER_SYNAPSE_ACTION_RISING_EDGE;
222 return 0;
223 case TI_EQEP_SIGNAL_QEPB:
224 *action = COUNTER_SYNAPSE_ACTION_NONE;
225 return 0;
226 default:
227 /* should never reach this path */
228 return -EINVAL;
229 }
230 default:
231 /* should never reach this path */
232 return -EINVAL;
233 }
234 }
235
236 static const struct counter_ops ti_eqep_counter_ops = {
237 .count_read = ti_eqep_count_read,
238 .count_write = ti_eqep_count_write,
239 .function_read = ti_eqep_function_read,
240 .function_write = ti_eqep_function_write,
241 .action_read = ti_eqep_action_read,
242 };
243
ti_eqep_position_ceiling_read(struct counter_device * counter,struct counter_count * count,u64 * ceiling)244 static int ti_eqep_position_ceiling_read(struct counter_device *counter,
245 struct counter_count *count,
246 u64 *ceiling)
247 {
248 struct ti_eqep_cnt *priv = counter->priv;
249 u32 qposmax;
250
251 regmap_read(priv->regmap32, QPOSMAX, &qposmax);
252
253 *ceiling = qposmax;
254
255 return 0;
256 }
257
ti_eqep_position_ceiling_write(struct counter_device * counter,struct counter_count * count,u64 ceiling)258 static int ti_eqep_position_ceiling_write(struct counter_device *counter,
259 struct counter_count *count,
260 u64 ceiling)
261 {
262 struct ti_eqep_cnt *priv = counter->priv;
263
264 if (ceiling != (u32)ceiling)
265 return -ERANGE;
266
267 regmap_write(priv->regmap32, QPOSMAX, ceiling);
268
269 return 0;
270 }
271
ti_eqep_position_enable_read(struct counter_device * counter,struct counter_count * count,u8 * enable)272 static int ti_eqep_position_enable_read(struct counter_device *counter,
273 struct counter_count *count, u8 *enable)
274 {
275 struct ti_eqep_cnt *priv = counter->priv;
276 u32 qepctl;
277
278 regmap_read(priv->regmap16, QEPCTL, &qepctl);
279
280 *enable = !!(qepctl & QEPCTL_PHEN);
281
282 return 0;
283 }
284
ti_eqep_position_enable_write(struct counter_device * counter,struct counter_count * count,u8 enable)285 static int ti_eqep_position_enable_write(struct counter_device *counter,
286 struct counter_count *count, u8 enable)
287 {
288 struct ti_eqep_cnt *priv = counter->priv;
289
290 regmap_write_bits(priv->regmap16, QEPCTL, QEPCTL_PHEN, enable ? -1 : 0);
291
292 return 0;
293 }
294
295 static struct counter_comp ti_eqep_position_ext[] = {
296 COUNTER_COMP_CEILING(ti_eqep_position_ceiling_read,
297 ti_eqep_position_ceiling_write),
298 COUNTER_COMP_ENABLE(ti_eqep_position_enable_read,
299 ti_eqep_position_enable_write),
300 };
301
302 static struct counter_signal ti_eqep_signals[] = {
303 [TI_EQEP_SIGNAL_QEPA] = {
304 .id = TI_EQEP_SIGNAL_QEPA,
305 .name = "QEPA"
306 },
307 [TI_EQEP_SIGNAL_QEPB] = {
308 .id = TI_EQEP_SIGNAL_QEPB,
309 .name = "QEPB"
310 },
311 };
312
313 static const enum counter_function ti_eqep_position_functions[] = {
314 COUNTER_FUNCTION_QUADRATURE_X4,
315 COUNTER_FUNCTION_PULSE_DIRECTION,
316 COUNTER_FUNCTION_INCREASE,
317 COUNTER_FUNCTION_DECREASE,
318 };
319
320 static const enum counter_synapse_action ti_eqep_position_synapse_actions[] = {
321 COUNTER_SYNAPSE_ACTION_BOTH_EDGES,
322 COUNTER_SYNAPSE_ACTION_RISING_EDGE,
323 COUNTER_SYNAPSE_ACTION_NONE,
324 };
325
326 static struct counter_synapse ti_eqep_position_synapses[] = {
327 {
328 .actions_list = ti_eqep_position_synapse_actions,
329 .num_actions = ARRAY_SIZE(ti_eqep_position_synapse_actions),
330 .signal = &ti_eqep_signals[TI_EQEP_SIGNAL_QEPA],
331 },
332 {
333 .actions_list = ti_eqep_position_synapse_actions,
334 .num_actions = ARRAY_SIZE(ti_eqep_position_synapse_actions),
335 .signal = &ti_eqep_signals[TI_EQEP_SIGNAL_QEPB],
336 },
337 };
338
339 static struct counter_count ti_eqep_counts[] = {
340 {
341 .id = 0,
342 .name = "QPOSCNT",
343 .functions_list = ti_eqep_position_functions,
344 .num_functions = ARRAY_SIZE(ti_eqep_position_functions),
345 .synapses = ti_eqep_position_synapses,
346 .num_synapses = ARRAY_SIZE(ti_eqep_position_synapses),
347 .ext = ti_eqep_position_ext,
348 .num_ext = ARRAY_SIZE(ti_eqep_position_ext),
349 },
350 };
351
352 static const struct regmap_config ti_eqep_regmap32_config = {
353 .name = "32-bit",
354 .reg_bits = 32,
355 .val_bits = 32,
356 .reg_stride = 4,
357 .max_register = QUPRD,
358 };
359
360 static const struct regmap_config ti_eqep_regmap16_config = {
361 .name = "16-bit",
362 .reg_bits = 16,
363 .val_bits = 16,
364 .reg_stride = 2,
365 .max_register = QCPRDLAT,
366 };
367
ti_eqep_probe(struct platform_device * pdev)368 static int ti_eqep_probe(struct platform_device *pdev)
369 {
370 struct device *dev = &pdev->dev;
371 struct ti_eqep_cnt *priv;
372 void __iomem *base;
373 int err;
374
375 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
376 if (!priv)
377 return -ENOMEM;
378
379 base = devm_platform_ioremap_resource(pdev, 0);
380 if (IS_ERR(base))
381 return PTR_ERR(base);
382
383 priv->regmap32 = devm_regmap_init_mmio(dev, base,
384 &ti_eqep_regmap32_config);
385 if (IS_ERR(priv->regmap32))
386 return PTR_ERR(priv->regmap32);
387
388 priv->regmap16 = devm_regmap_init_mmio(dev, base + 0x24,
389 &ti_eqep_regmap16_config);
390 if (IS_ERR(priv->regmap16))
391 return PTR_ERR(priv->regmap16);
392
393 priv->counter.name = dev_name(dev);
394 priv->counter.parent = dev;
395 priv->counter.ops = &ti_eqep_counter_ops;
396 priv->counter.counts = ti_eqep_counts;
397 priv->counter.num_counts = ARRAY_SIZE(ti_eqep_counts);
398 priv->counter.signals = ti_eqep_signals;
399 priv->counter.num_signals = ARRAY_SIZE(ti_eqep_signals);
400 priv->counter.priv = priv;
401
402 platform_set_drvdata(pdev, priv);
403
404 /*
405 * Need to make sure power is turned on. On AM33xx, this comes from the
406 * parent PWMSS bus driver. On AM17xx, this comes from the PSC power
407 * domain.
408 */
409 pm_runtime_enable(dev);
410 pm_runtime_get_sync(dev);
411
412 err = counter_register(&priv->counter);
413 if (err < 0) {
414 pm_runtime_put_sync(dev);
415 pm_runtime_disable(dev);
416 return err;
417 }
418
419 return 0;
420 }
421
ti_eqep_remove(struct platform_device * pdev)422 static int ti_eqep_remove(struct platform_device *pdev)
423 {
424 struct ti_eqep_cnt *priv = platform_get_drvdata(pdev);
425 struct device *dev = &pdev->dev;
426
427 counter_unregister(&priv->counter);
428 pm_runtime_put_sync(dev);
429 pm_runtime_disable(dev);
430
431 return 0;
432 }
433
434 static const struct of_device_id ti_eqep_of_match[] = {
435 { .compatible = "ti,am3352-eqep", },
436 { },
437 };
438 MODULE_DEVICE_TABLE(of, ti_eqep_of_match);
439
440 static struct platform_driver ti_eqep_driver = {
441 .probe = ti_eqep_probe,
442 .remove = ti_eqep_remove,
443 .driver = {
444 .name = "ti-eqep-cnt",
445 .of_match_table = ti_eqep_of_match,
446 },
447 };
448 module_platform_driver(ti_eqep_driver);
449
450 MODULE_AUTHOR("David Lechner <david@lechnology.com>");
451 MODULE_DESCRIPTION("TI eQEP counter driver");
452 MODULE_LICENSE("GPL v2");
453