1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */ 2 /* Copyright(c) 2014 - 2020 Intel Corporation */ 3 #ifndef ADF_4XXX_HW_DATA_H_ 4 #define ADF_4XXX_HW_DATA_H_ 5 6 #include <adf_accel_devices.h> 7 8 /* PCIe configuration space */ 9 #define ADF_4XXX_SRAM_BAR 0 10 #define ADF_4XXX_PMISC_BAR 1 11 #define ADF_4XXX_ETR_BAR 2 12 #define ADF_4XXX_RX_RINGS_OFFSET 1 13 #define ADF_4XXX_TX_RINGS_MASK 0x1 14 #define ADF_4XXX_MAX_ACCELERATORS 1 15 #define ADF_4XXX_MAX_ACCELENGINES 9 16 #define ADF_4XXX_BAR_MASK (BIT(0) | BIT(2) | BIT(4)) 17 18 /* Physical function fuses */ 19 #define ADF_4XXX_FUSECTL0_OFFSET (0x2C8) 20 #define ADF_4XXX_FUSECTL1_OFFSET (0x2CC) 21 #define ADF_4XXX_FUSECTL2_OFFSET (0x2D0) 22 #define ADF_4XXX_FUSECTL3_OFFSET (0x2D4) 23 #define ADF_4XXX_FUSECTL4_OFFSET (0x2D8) 24 #define ADF_4XXX_FUSECTL5_OFFSET (0x2DC) 25 26 #define ADF_4XXX_ACCELERATORS_MASK (0x1) 27 #define ADF_4XXX_ACCELENGINES_MASK (0x1FF) 28 #define ADF_4XXX_ADMIN_AE_MASK (0x100) 29 30 #define ADF_4XXX_ETR_MAX_BANKS 64 31 32 /* MSIX interrupt */ 33 #define ADF_4XXX_SMIAPF_RP_X0_MASK_OFFSET (0x41A040) 34 #define ADF_4XXX_SMIAPF_RP_X1_MASK_OFFSET (0x41A044) 35 #define ADF_4XXX_SMIAPF_MASK_OFFSET (0x41A084) 36 #define ADF_4XXX_MSIX_RTTABLE_OFFSET(i) (0x409000 + ((i) * 0x04)) 37 38 /* Bank and ring configuration */ 39 #define ADF_4XXX_NUM_RINGS_PER_BANK 2 40 41 /* Error source registers */ 42 #define ADF_4XXX_ERRSOU0 (0x41A200) 43 #define ADF_4XXX_ERRSOU1 (0x41A204) 44 #define ADF_4XXX_ERRSOU2 (0x41A208) 45 #define ADF_4XXX_ERRSOU3 (0x41A20C) 46 47 /* Error source mask registers */ 48 #define ADF_4XXX_ERRMSK0 (0x41A210) 49 #define ADF_4XXX_ERRMSK1 (0x41A214) 50 #define ADF_4XXX_ERRMSK2 (0x41A218) 51 #define ADF_4XXX_ERRMSK3 (0x41A21C) 52 53 #define ADF_4XXX_VFLNOTIFY BIT(7) 54 55 /* Arbiter configuration */ 56 #define ADF_4XXX_ARB_CONFIG (BIT(31) | BIT(6) | BIT(0)) 57 #define ADF_4XXX_ARB_OFFSET (0x0) 58 #define ADF_4XXX_ARB_WRK_2_SER_MAP_OFFSET (0x400) 59 60 /* Admin Interface Reg Offset */ 61 #define ADF_4XXX_ADMINMSGUR_OFFSET (0x500574) 62 #define ADF_4XXX_ADMINMSGLR_OFFSET (0x500578) 63 #define ADF_4XXX_MAILBOX_BASE_OFFSET (0x600970) 64 65 /* Power management */ 66 #define ADF_4XXX_PM_POLL_DELAY_US 20 67 #define ADF_4XXX_PM_POLL_TIMEOUT_US USEC_PER_SEC 68 #define ADF_4XXX_PM_STATUS (0x50A00C) 69 #define ADF_4XXX_PM_INTERRUPT (0x50A028) 70 #define ADF_4XXX_PM_DRV_ACTIVE BIT(20) 71 #define ADF_4XXX_PM_INIT_STATE BIT(21) 72 /* Power management source in ERRSOU2 and ERRMSK2 */ 73 #define ADF_4XXX_PM_SOU BIT(18) 74 75 /* Firmware Binaries */ 76 #define ADF_4XXX_FW "qat_4xxx.bin" 77 #define ADF_4XXX_MMP "qat_4xxx_mmp.bin" 78 #define ADF_4XXX_SYM_OBJ "qat_4xxx_sym.bin" 79 #define ADF_4XXX_ASYM_OBJ "qat_4xxx_asym.bin" 80 #define ADF_4XXX_ADMIN_OBJ "qat_4xxx_admin.bin" 81 82 /* qat_4xxx fuse bits are different from old GENs, redefine them */ 83 enum icp_qat_4xxx_slice_mask { 84 ICP_ACCEL_4XXX_MASK_CIPHER_SLICE = BIT(0), 85 ICP_ACCEL_4XXX_MASK_AUTH_SLICE = BIT(1), 86 ICP_ACCEL_4XXX_MASK_PKE_SLICE = BIT(2), 87 ICP_ACCEL_4XXX_MASK_COMPRESS_SLICE = BIT(3), 88 ICP_ACCEL_4XXX_MASK_UCS_SLICE = BIT(4), 89 ICP_ACCEL_4XXX_MASK_EIA3_SLICE = BIT(5), 90 ICP_ACCEL_4XXX_MASK_SMX_SLICE = BIT(6), 91 }; 92 93 void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data); 94 void adf_clean_hw_data_4xxx(struct adf_hw_device_data *hw_data); 95 96 #endif 97