1 # SPDX-License-Identifier: GPL-2.0-only
2 menuconfig CXL_BUS
3 	tristate "CXL (Compute Express Link) Devices Support"
4 	depends on PCI
5 	help
6 	  CXL is a bus that is electrically compatible with PCI Express, but
7 	  layers three protocols on that signalling (CXL.io, CXL.cache, and
8 	  CXL.mem). The CXL.cache protocol allows devices to hold cachelines
9 	  locally, the CXL.mem protocol allows devices to be fully coherent
10 	  memory targets, the CXL.io protocol is equivalent to PCI Express.
11 	  Say 'y' to enable support for the configuration and management of
12 	  devices supporting these protocols.
13 
14 if CXL_BUS
15 
16 config CXL_MEM
17 	tristate "CXL.mem: Memory Devices"
18 	default CXL_BUS
19 	help
20 	  The CXL.mem protocol allows a device to act as a provider of
21 	  "System RAM" and/or "Persistent Memory" that is fully coherent
22 	  as if the memory was attached to the typical CPU memory
23 	  controller.
24 
25 	  Say 'y/m' to enable a driver that will attach to CXL.mem devices for
26 	  configuration and management primarily via the mailbox interface. See
27 	  Chapter 2.3 Type 3 CXL Device in the CXL 2.0 specification for more
28 	  details.
29 
30 	  If unsure say 'm'.
31 
32 config CXL_MEM_RAW_COMMANDS
33 	bool "RAW Command Interface for Memory Devices"
34 	depends on CXL_MEM
35 	help
36 	  Enable CXL RAW command interface.
37 
38 	  The CXL driver ioctl interface may assign a kernel ioctl command
39 	  number for each specification defined opcode. At any given point in
40 	  time the number of opcodes that the specification defines and a device
41 	  may implement may exceed the kernel's set of associated ioctl function
42 	  numbers. The mismatch is either by omission, specification is too new,
43 	  or by design. When prototyping new hardware, or developing / debugging
44 	  the driver it is useful to be able to submit any possible command to
45 	  the hardware, even commands that may crash the kernel due to their
46 	  potential impact to memory currently in use by the kernel.
47 
48 	  If developing CXL hardware or the driver say Y, otherwise say N.
49 
50 config CXL_ACPI
51 	tristate "CXL ACPI: Platform Support"
52 	depends on ACPI
53 	default CXL_BUS
54 	help
55 	  Enable support for host managed device memory (HDM) resources
56 	  published by a platform's ACPI CXL memory layout description.  See
57 	  Chapter 9.14.1 CXL Early Discovery Table (CEDT) in the CXL 2.0
58 	  specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS)
59 	  (https://www.computeexpresslink.org/spec-landing). The CXL core
60 	  consumes these resource to publish the root of a cxl_port decode
61 	  hierarchy to map regions that represent System RAM, or Persistent
62 	  Memory regions to be managed by LIBNVDIMM.
63 
64 	  If unsure say 'm'.
65 
66 config CXL_PMEM
67 	tristate "CXL PMEM: Persistent Memory Support"
68 	depends on LIBNVDIMM
69 	default CXL_BUS
70 	help
71 	  In addition to typical memory resources a platform may also advertise
72 	  support for persistent memory attached via CXL. This support is
73 	  managed via a bridge driver from CXL to the LIBNVDIMM system
74 	  subsystem. Say 'y/m' to enable support for enumerating and
75 	  provisioning the persistent memory capacity of CXL memory expanders.
76 
77 	  If unsure say 'm'.
78 endif
79