1#
2#	EDAC Kconfig
3#	Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
4#	Licensed and distributed under the GPL
5
6config EDAC_ATOMIC_SCRUB
7	bool
8
9config EDAC_SUPPORT
10	bool
11
12menuconfig EDAC
13	tristate "EDAC (Error Detection And Correction) reporting"
14	depends on HAS_IOMEM && EDAC_SUPPORT && RAS
15	help
16	  EDAC is a subsystem along with hardware-specific drivers designed to
17	  report hardware errors. These are low-level errors that are reported
18	  in the CPU or supporting chipset or other subsystems:
19	  memory errors, cache errors, PCI errors, thermal throttling, etc..
20	  If unsure, select 'Y'.
21
22	  The mailing list for the EDAC project is linux-edac@vger.kernel.org.
23
24if EDAC
25
26config EDAC_LEGACY_SYSFS
27	bool "EDAC legacy sysfs"
28	default y
29	help
30	  Enable the compatibility sysfs nodes.
31	  Use 'Y' if your edac utilities aren't ported to work with the newer
32	  structures.
33
34config EDAC_DEBUG
35	bool "Debugging"
36	select DEBUG_FS
37	help
38	  This turns on debugging information for the entire EDAC subsystem.
39	  You do so by inserting edac_module with "edac_debug_level=x." Valid
40	  levels are 0-4 (from low to high) and by default it is set to 2.
41	  Usually you should select 'N' here.
42
43config EDAC_DECODE_MCE
44	tristate "Decode MCEs in human-readable form (only on AMD for now)"
45	depends on CPU_SUP_AMD && X86_MCE_AMD
46	default y
47	help
48	  Enable this option if you want to decode Machine Check Exceptions
49	  occurring on your machine in human-readable form.
50
51	  You should definitely say Y here in case you want to decode MCEs
52	  which occur really early upon boot, before the module infrastructure
53	  has been initialized.
54
55config EDAC_GHES
56	bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
57	depends on ACPI_APEI_GHES && (EDAC=y)
58	help
59	  Not all machines support hardware-driven error report. Some of those
60	  provide a BIOS-driven error report mechanism via ACPI, using the
61	  APEI/GHES driver. By enabling this option, the error reports provided
62	  by GHES are sent to userspace via the EDAC API.
63
64	  When this option is enabled, it will disable the hardware-driven
65	  mechanisms, if a GHES BIOS is detected, entering into the
66	  "Firmware First" mode.
67
68	  It should be noticed that keeping both GHES and a hardware-driven
69	  error mechanism won't work well, as BIOS will race with OS, while
70	  reading the error registers. So, if you want to not use "Firmware
71	  first" GHES error mechanism, you should disable GHES either at
72	  compilation time or by passing "ghes.disable=1" Kernel parameter
73	  at boot time.
74
75	  In doubt, say 'Y'.
76
77config EDAC_AMD64
78	tristate "AMD64 (Opteron, Athlon64)"
79	depends on AMD_NB && EDAC_DECODE_MCE
80	help
81	  Support for error detection and correction of DRAM ECC errors on
82	  the AMD64 families (>= K8) of memory controllers.
83
84	  When EDAC_DEBUG is enabled, hardware error injection facilities
85	  through sysfs are available:
86
87	  AMD CPUs up to and excluding family 0x17 provide for Memory
88	  Error Injection into the ECC detection circuits. The amd64_edac
89	  module allows the operator/user to inject Uncorrectable and
90	  Correctable errors into DRAM.
91
92	  When enabled, in each of the respective memory controller directories
93	  (/sys/devices/system/edac/mc/mcX), there are 3 input files:
94
95	  - inject_section (0..3, 16-byte section of 64-byte cacheline),
96	  - inject_word (0..8, 16-bit word of 16-byte section),
97	  - inject_ecc_vector (hex ecc vector: select bits of inject word)
98
99	  In addition, there are two control files, inject_read and inject_write,
100	  which trigger the DRAM ECC Read and Write respectively.
101
102config EDAC_AL_MC
103	tristate "Amazon's Annapurna Lab Memory Controller"
104	depends on (ARCH_ALPINE || COMPILE_TEST)
105	help
106	  Support for error detection and correction for Amazon's Annapurna
107	  Labs Alpine chips which allow 1 bit correction and 2 bits detection.
108
109config EDAC_AMD76X
110	tristate "AMD 76x (760, 762, 768)"
111	depends on PCI && X86_32
112	help
113	  Support for error detection and correction on the AMD 76x
114	  series of chipsets used with the Athlon processor.
115
116config EDAC_E7XXX
117	tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
118	depends on PCI && X86_32
119	help
120	  Support for error detection and correction on the Intel
121	  E7205, E7500, E7501 and E7505 server chipsets.
122
123config EDAC_E752X
124	tristate "Intel e752x (e7520, e7525, e7320) and 3100"
125	depends on PCI && X86
126	help
127	  Support for error detection and correction on the Intel
128	  E7520, E7525, E7320 server chipsets.
129
130config EDAC_I82443BXGX
131	tristate "Intel 82443BX/GX (440BX/GX)"
132	depends on PCI && X86_32
133	depends on BROKEN
134	help
135	  Support for error detection and correction on the Intel
136	  82443BX/GX memory controllers (440BX/GX chipsets).
137
138config EDAC_I82875P
139	tristate "Intel 82875p (D82875P, E7210)"
140	depends on PCI && X86_32
141	help
142	  Support for error detection and correction on the Intel
143	  DP82785P and E7210 server chipsets.
144
145config EDAC_I82975X
146	tristate "Intel 82975x (D82975x)"
147	depends on PCI && X86
148	help
149	  Support for error detection and correction on the Intel
150	  DP82975x server chipsets.
151
152config EDAC_I3000
153	tristate "Intel 3000/3010"
154	depends on PCI && X86
155	help
156	  Support for error detection and correction on the Intel
157	  3000 and 3010 server chipsets.
158
159config EDAC_I3200
160	tristate "Intel 3200"
161	depends on PCI && X86
162	help
163	  Support for error detection and correction on the Intel
164	  3200 and 3210 server chipsets.
165
166config EDAC_IE31200
167	tristate "Intel e312xx"
168	depends on PCI && X86
169	help
170	  Support for error detection and correction on the Intel
171	  E3-1200 based DRAM controllers.
172
173config EDAC_X38
174	tristate "Intel X38"
175	depends on PCI && X86
176	help
177	  Support for error detection and correction on the Intel
178	  X38 server chipsets.
179
180config EDAC_I5400
181	tristate "Intel 5400 (Seaburg) chipsets"
182	depends on PCI && X86
183	help
184	  Support for error detection and correction the Intel
185	  i5400 MCH chipset (Seaburg).
186
187config EDAC_I7CORE
188	tristate "Intel i7 Core (Nehalem) processors"
189	depends on PCI && X86 && X86_MCE_INTEL
190	help
191	  Support for error detection and correction the Intel
192	  i7 Core (Nehalem) Integrated Memory Controller that exists on
193	  newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
194	  and Xeon 55xx processors.
195
196config EDAC_I82860
197	tristate "Intel 82860"
198	depends on PCI && X86_32
199	help
200	  Support for error detection and correction on the Intel
201	  82860 chipset.
202
203config EDAC_R82600
204	tristate "Radisys 82600 embedded chipset"
205	depends on PCI && X86_32
206	help
207	  Support for error detection and correction on the Radisys
208	  82600 embedded chipset.
209
210config EDAC_I5000
211	tristate "Intel Greencreek/Blackford chipset"
212	depends on X86 && PCI
213	help
214	  Support for error detection and correction the Intel
215	  Greekcreek/Blackford chipsets.
216
217config EDAC_I5100
218	tristate "Intel San Clemente MCH"
219	depends on X86 && PCI
220	help
221	  Support for error detection and correction the Intel
222	  San Clemente MCH.
223
224config EDAC_I7300
225	tristate "Intel Clarksboro MCH"
226	depends on X86 && PCI
227	help
228	  Support for error detection and correction the Intel
229	  Clarksboro MCH (Intel 7300 chipset).
230
231config EDAC_SBRIDGE
232	tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
233	depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
234	help
235	  Support for error detection and correction the Intel
236	  Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
237
238config EDAC_SKX
239	tristate "Intel Skylake server Integrated MC"
240	depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
241	depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y
242	select DMI
243	select ACPI_ADXL
244	help
245	  Support for error detection and correction the Intel
246	  Skylake server Integrated Memory Controllers. If your
247	  system has non-volatile DIMMs you should also manually
248	  select CONFIG_ACPI_NFIT.
249
250config EDAC_I10NM
251	tristate "Intel 10nm server Integrated MC"
252	depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
253	depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y
254	select DMI
255	select ACPI_ADXL
256	help
257	  Support for error detection and correction the Intel
258	  10nm server Integrated Memory Controllers. If your
259	  system has non-volatile DIMMs you should also manually
260	  select CONFIG_ACPI_NFIT.
261
262config EDAC_PND2
263	tristate "Intel Pondicherry2"
264	depends on PCI && X86_64 && X86_MCE_INTEL
265	help
266	  Support for error detection and correction on the Intel
267	  Pondicherry2 Integrated Memory Controller. This SoC IP is
268	  first used on the Apollo Lake platform and Denverton
269	  micro-server but may appear on others in the future.
270
271config EDAC_IGEN6
272	tristate "Intel client SoC Integrated MC"
273	depends on PCI && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG
274	depends on X86_64 && X86_MCE_INTEL
275	help
276	  Support for error detection and correction on the Intel
277	  client SoC Integrated Memory Controller using In-Band ECC IP.
278	  This In-Band ECC is first used on the Elkhart Lake SoC but
279	  may appear on others in the future.
280
281config EDAC_MPC85XX
282	bool "Freescale MPC83xx / MPC85xx"
283	depends on FSL_SOC && EDAC=y
284	help
285	  Support for error detection and correction on the Freescale
286	  MPC8349, MPC8560, MPC8540, MPC8548, T4240
287
288config EDAC_LAYERSCAPE
289	tristate "Freescale Layerscape DDR"
290	depends on ARCH_LAYERSCAPE || SOC_LS1021A
291	help
292	  Support for error detection and correction on Freescale memory
293	  controllers on Layerscape SoCs.
294
295config EDAC_PASEMI
296	tristate "PA Semi PWRficient"
297	depends on PPC_PASEMI && PCI
298	help
299	  Support for error detection and correction on PA Semi
300	  PWRficient.
301
302config EDAC_CELL
303	tristate "Cell Broadband Engine memory controller"
304	depends on PPC_CELL_COMMON
305	help
306	  Support for error detection and correction on the
307	  Cell Broadband Engine internal memory controller
308	  on platform without a hypervisor
309
310config EDAC_PPC4XX
311	tristate "PPC4xx IBM DDR2 Memory Controller"
312	depends on 4xx
313	help
314	  This enables support for EDAC on the ECC memory used
315	  with the IBM DDR2 memory controller found in various
316	  PowerPC 4xx embedded processors such as the 405EX[r],
317	  440SP, 440SPe, 460EX, 460GT and 460SX.
318
319config EDAC_AMD8131
320	tristate "AMD8131 HyperTransport PCI-X Tunnel"
321	depends on PCI && PPC_MAPLE
322	help
323	  Support for error detection and correction on the
324	  AMD8131 HyperTransport PCI-X Tunnel chip.
325	  Note, add more Kconfig dependency if it's adopted
326	  on some machine other than Maple.
327
328config EDAC_AMD8111
329	tristate "AMD8111 HyperTransport I/O Hub"
330	depends on PCI && PPC_MAPLE
331	help
332	  Support for error detection and correction on the
333	  AMD8111 HyperTransport I/O Hub chip.
334	  Note, add more Kconfig dependency if it's adopted
335	  on some machine other than Maple.
336
337config EDAC_CPC925
338	tristate "IBM CPC925 Memory Controller (PPC970FX)"
339	depends on PPC64
340	help
341	  Support for error detection and correction on the
342	  IBM CPC925 Bridge and Memory Controller, which is
343	  a companion chip to the PowerPC 970 family of
344	  processors.
345
346config EDAC_HIGHBANK_MC
347	tristate "Highbank Memory Controller"
348	depends on ARCH_HIGHBANK
349	help
350	  Support for error detection and correction on the
351	  Calxeda Highbank memory controller.
352
353config EDAC_HIGHBANK_L2
354	tristate "Highbank L2 Cache"
355	depends on ARCH_HIGHBANK
356	help
357	  Support for error detection and correction on the
358	  Calxeda Highbank memory controller.
359
360config EDAC_OCTEON_PC
361	tristate "Cavium Octeon Primary Caches"
362	depends on CPU_CAVIUM_OCTEON
363	help
364	  Support for error detection and correction on the primary caches of
365	  the cnMIPS cores of Cavium Octeon family SOCs.
366
367config EDAC_OCTEON_L2C
368	tristate "Cavium Octeon Secondary Caches (L2C)"
369	depends on CAVIUM_OCTEON_SOC
370	help
371	  Support for error detection and correction on the
372	  Cavium Octeon family of SOCs.
373
374config EDAC_OCTEON_LMC
375	tristate "Cavium Octeon DRAM Memory Controller (LMC)"
376	depends on CAVIUM_OCTEON_SOC
377	help
378	  Support for error detection and correction on the
379	  Cavium Octeon family of SOCs.
380
381config EDAC_OCTEON_PCI
382	tristate "Cavium Octeon PCI Controller"
383	depends on PCI && CAVIUM_OCTEON_SOC
384	help
385	  Support for error detection and correction on the
386	  Cavium Octeon family of SOCs.
387
388config EDAC_THUNDERX
389	tristate "Cavium ThunderX EDAC"
390	depends on ARM64
391	depends on PCI
392	help
393	  Support for error detection and correction on the
394	  Cavium ThunderX memory controllers (LMC), Cache
395	  Coherent Processor Interconnect (CCPI) and L2 cache
396	  blocks (TAD, CBC, MCI).
397
398config EDAC_ALTERA
399	bool "Altera SOCFPGA ECC"
400	depends on EDAC=y && ARCH_INTEL_SOCFPGA
401	help
402	  Support for error detection and correction on the
403	  Altera SOCs. This is the global enable for the
404	  various Altera peripherals.
405
406config EDAC_ALTERA_SDRAM
407	bool "Altera SDRAM ECC"
408	depends on EDAC_ALTERA=y
409	help
410	  Support for error detection and correction on the
411	  Altera SDRAM Memory for Altera SoCs. Note that the
412	  preloader must initialize the SDRAM before loading
413	  the kernel.
414
415config EDAC_ALTERA_L2C
416	bool "Altera L2 Cache ECC"
417	depends on EDAC_ALTERA=y && CACHE_L2X0
418	help
419	  Support for error detection and correction on the
420	  Altera L2 cache Memory for Altera SoCs. This option
421	  requires L2 cache.
422
423config EDAC_ALTERA_OCRAM
424	bool "Altera On-Chip RAM ECC"
425	depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR
426	help
427	  Support for error detection and correction on the
428	  Altera On-Chip RAM Memory for Altera SoCs.
429
430config EDAC_ALTERA_ETHERNET
431	bool "Altera Ethernet FIFO ECC"
432	depends on EDAC_ALTERA=y
433	help
434	  Support for error detection and correction on the
435	  Altera Ethernet FIFO Memory for Altera SoCs.
436
437config EDAC_ALTERA_NAND
438	bool "Altera NAND FIFO ECC"
439	depends on EDAC_ALTERA=y && MTD_NAND_DENALI
440	help
441	  Support for error detection and correction on the
442	  Altera NAND FIFO Memory for Altera SoCs.
443
444config EDAC_ALTERA_DMA
445	bool "Altera DMA FIFO ECC"
446	depends on EDAC_ALTERA=y && PL330_DMA=y
447	help
448	  Support for error detection and correction on the
449	  Altera DMA FIFO Memory for Altera SoCs.
450
451config EDAC_ALTERA_USB
452	bool "Altera USB FIFO ECC"
453	depends on EDAC_ALTERA=y && USB_DWC2
454	help
455	  Support for error detection and correction on the
456	  Altera USB FIFO Memory for Altera SoCs.
457
458config EDAC_ALTERA_QSPI
459	bool "Altera QSPI FIFO ECC"
460	depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI
461	help
462	  Support for error detection and correction on the
463	  Altera QSPI FIFO Memory for Altera SoCs.
464
465config EDAC_ALTERA_SDMMC
466	bool "Altera SDMMC FIFO ECC"
467	depends on EDAC_ALTERA=y && MMC_DW
468	help
469	  Support for error detection and correction on the
470	  Altera SDMMC FIFO Memory for Altera SoCs.
471
472config EDAC_SIFIVE
473	bool "Sifive platform EDAC driver"
474	depends on EDAC=y && SIFIVE_L2
475	help
476	  Support for error detection and correction on the SiFive SoCs.
477
478config EDAC_ARMADA_XP
479	bool "Marvell Armada XP DDR and L2 Cache ECC"
480	depends on MACH_MVEBU_V7
481	help
482	  Support for error correction and detection on the Marvell Aramada XP
483	  DDR RAM and L2 cache controllers.
484
485config EDAC_SYNOPSYS
486	tristate "Synopsys DDR Memory Controller"
487	depends on ARCH_ZYNQ || ARCH_ZYNQMP
488	help
489	  Support for error detection and correction on the Synopsys DDR
490	  memory controller.
491
492config EDAC_XGENE
493	tristate "APM X-Gene SoC"
494	depends on (ARM64 || COMPILE_TEST)
495	help
496	  Support for error detection and correction on the
497	  APM X-Gene family of SOCs.
498
499config EDAC_TI
500	tristate "Texas Instruments DDR3 ECC Controller"
501	depends on ARCH_KEYSTONE || SOC_DRA7XX
502	help
503	  Support for error detection and correction on the TI SoCs.
504
505config EDAC_QCOM
506	tristate "QCOM EDAC Controller"
507	depends on ARCH_QCOM && QCOM_LLCC
508	help
509	  Support for error detection and correction on the
510	  Qualcomm Technologies, Inc. SoCs.
511
512	  This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs).
513	  As of now, it supports error reporting for Last Level Cache Controller (LLCC)
514	  of Tag RAM and Data RAM.
515
516	  For debugging issues having to do with stability and overall system
517	  health, you should probably say 'Y' here.
518
519config EDAC_ASPEED
520	tristate "Aspeed AST BMC SoC"
521	depends on ARCH_ASPEED
522	help
523	  Support for error detection and correction on the Aspeed AST BMC SoC.
524
525	  First, ECC must be configured in the bootloader. Then, this driver
526	  will expose error counters via the EDAC kernel framework.
527
528config EDAC_BLUEFIELD
529	tristate "Mellanox BlueField Memory ECC"
530	depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST)
531	help
532	  Support for error detection and correction on the
533	  Mellanox BlueField SoCs.
534
535config EDAC_DMC520
536	tristate "ARM DMC-520 ECC"
537	depends on ARM64
538	help
539	  Support for error detection and correction on the
540	  SoCs with ARM DMC-520 DRAM controller.
541
542endif # EDAC
543