1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * GPIO driver for the WinSystems WS16C48
4  * Copyright (C) 2016 William Breathitt Gray
5  */
6 #include <linux/bitmap.h>
7 #include <linux/bitops.h>
8 #include <linux/device.h>
9 #include <linux/errno.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/io.h>
12 #include <linux/ioport.h>
13 #include <linux/interrupt.h>
14 #include <linux/irqdesc.h>
15 #include <linux/isa.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/moduleparam.h>
19 #include <linux/spinlock.h>
20 
21 #define WS16C48_EXTENT 16
22 #define MAX_NUM_WS16C48 max_num_isa_dev(WS16C48_EXTENT)
23 
24 static unsigned int base[MAX_NUM_WS16C48];
25 static unsigned int num_ws16c48;
26 module_param_hw_array(base, uint, ioport, &num_ws16c48, 0);
27 MODULE_PARM_DESC(base, "WinSystems WS16C48 base addresses");
28 
29 static unsigned int irq[MAX_NUM_WS16C48];
30 module_param_hw_array(irq, uint, irq, NULL, 0);
31 MODULE_PARM_DESC(irq, "WinSystems WS16C48 interrupt line numbers");
32 
33 /**
34  * struct ws16c48_gpio - GPIO device private data structure
35  * @chip:	instance of the gpio_chip
36  * @io_state:	bit I/O state (whether bit is set to input or output)
37  * @out_state:	output bits state
38  * @lock:	synchronization lock to prevent I/O race conditions
39  * @irq_mask:	I/O bits affected by interrupts
40  * @flow_mask:	IRQ flow type mask for the respective I/O bits
41  * @base:	base port address of the GPIO device
42  */
43 struct ws16c48_gpio {
44 	struct gpio_chip chip;
45 	unsigned char io_state[6];
46 	unsigned char out_state[6];
47 	raw_spinlock_t lock;
48 	unsigned long irq_mask;
49 	unsigned long flow_mask;
50 	unsigned base;
51 };
52 
ws16c48_gpio_get_direction(struct gpio_chip * chip,unsigned offset)53 static int ws16c48_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
54 {
55 	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
56 	const unsigned port = offset / 8;
57 	const unsigned mask = BIT(offset % 8);
58 
59 	if (ws16c48gpio->io_state[port] & mask)
60 		return GPIO_LINE_DIRECTION_IN;
61 
62 	return GPIO_LINE_DIRECTION_OUT;
63 }
64 
ws16c48_gpio_direction_input(struct gpio_chip * chip,unsigned offset)65 static int ws16c48_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
66 {
67 	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
68 	const unsigned port = offset / 8;
69 	const unsigned mask = BIT(offset % 8);
70 	unsigned long flags;
71 
72 	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
73 
74 	ws16c48gpio->io_state[port] |= mask;
75 	ws16c48gpio->out_state[port] &= ~mask;
76 	outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
77 
78 	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
79 
80 	return 0;
81 }
82 
ws16c48_gpio_direction_output(struct gpio_chip * chip,unsigned offset,int value)83 static int ws16c48_gpio_direction_output(struct gpio_chip *chip,
84 	unsigned offset, int value)
85 {
86 	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
87 	const unsigned port = offset / 8;
88 	const unsigned mask = BIT(offset % 8);
89 	unsigned long flags;
90 
91 	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
92 
93 	ws16c48gpio->io_state[port] &= ~mask;
94 	if (value)
95 		ws16c48gpio->out_state[port] |= mask;
96 	else
97 		ws16c48gpio->out_state[port] &= ~mask;
98 	outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
99 
100 	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
101 
102 	return 0;
103 }
104 
ws16c48_gpio_get(struct gpio_chip * chip,unsigned offset)105 static int ws16c48_gpio_get(struct gpio_chip *chip, unsigned offset)
106 {
107 	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
108 	const unsigned port = offset / 8;
109 	const unsigned mask = BIT(offset % 8);
110 	unsigned long flags;
111 	unsigned port_state;
112 
113 	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
114 
115 	/* ensure that GPIO is set for input */
116 	if (!(ws16c48gpio->io_state[port] & mask)) {
117 		raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
118 		return -EINVAL;
119 	}
120 
121 	port_state = inb(ws16c48gpio->base + port);
122 
123 	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
124 
125 	return !!(port_state & mask);
126 }
127 
ws16c48_gpio_get_multiple(struct gpio_chip * chip,unsigned long * mask,unsigned long * bits)128 static int ws16c48_gpio_get_multiple(struct gpio_chip *chip,
129 	unsigned long *mask, unsigned long *bits)
130 {
131 	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
132 	unsigned long offset;
133 	unsigned long gpio_mask;
134 	unsigned int port_addr;
135 	unsigned long port_state;
136 
137 	/* clear bits array to a clean slate */
138 	bitmap_zero(bits, chip->ngpio);
139 
140 	for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) {
141 		port_addr = ws16c48gpio->base + offset / 8;
142 		port_state = inb(port_addr) & gpio_mask;
143 
144 		bitmap_set_value8(bits, port_state, offset);
145 	}
146 
147 	return 0;
148 }
149 
ws16c48_gpio_set(struct gpio_chip * chip,unsigned offset,int value)150 static void ws16c48_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
151 {
152 	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
153 	const unsigned port = offset / 8;
154 	const unsigned mask = BIT(offset % 8);
155 	unsigned long flags;
156 
157 	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
158 
159 	/* ensure that GPIO is set for output */
160 	if (ws16c48gpio->io_state[port] & mask) {
161 		raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
162 		return;
163 	}
164 
165 	if (value)
166 		ws16c48gpio->out_state[port] |= mask;
167 	else
168 		ws16c48gpio->out_state[port] &= ~mask;
169 	outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
170 
171 	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
172 }
173 
ws16c48_gpio_set_multiple(struct gpio_chip * chip,unsigned long * mask,unsigned long * bits)174 static void ws16c48_gpio_set_multiple(struct gpio_chip *chip,
175 	unsigned long *mask, unsigned long *bits)
176 {
177 	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
178 	unsigned long offset;
179 	unsigned long gpio_mask;
180 	size_t index;
181 	unsigned int port_addr;
182 	unsigned long bitmask;
183 	unsigned long flags;
184 
185 	for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) {
186 		index = offset / 8;
187 		port_addr = ws16c48gpio->base + index;
188 
189 		/* mask out GPIO configured for input */
190 		gpio_mask &= ~ws16c48gpio->io_state[index];
191 		bitmask = bitmap_get_value8(bits, offset) & gpio_mask;
192 
193 		raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
194 
195 		/* update output state data and set device gpio register */
196 		ws16c48gpio->out_state[index] &= ~gpio_mask;
197 		ws16c48gpio->out_state[index] |= bitmask;
198 		outb(ws16c48gpio->out_state[index], port_addr);
199 
200 		raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
201 	}
202 }
203 
ws16c48_irq_ack(struct irq_data * data)204 static void ws16c48_irq_ack(struct irq_data *data)
205 {
206 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
207 	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
208 	const unsigned long offset = irqd_to_hwirq(data);
209 	const unsigned port = offset / 8;
210 	const unsigned mask = BIT(offset % 8);
211 	unsigned long flags;
212 	unsigned port_state;
213 
214 	/* only the first 3 ports support interrupts */
215 	if (port > 2)
216 		return;
217 
218 	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
219 
220 	port_state = ws16c48gpio->irq_mask >> (8*port);
221 
222 	outb(0x80, ws16c48gpio->base + 7);
223 	outb(port_state & ~mask, ws16c48gpio->base + 8 + port);
224 	outb(port_state | mask, ws16c48gpio->base + 8 + port);
225 	outb(0xC0, ws16c48gpio->base + 7);
226 
227 	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
228 }
229 
ws16c48_irq_mask(struct irq_data * data)230 static void ws16c48_irq_mask(struct irq_data *data)
231 {
232 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
233 	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
234 	const unsigned long offset = irqd_to_hwirq(data);
235 	const unsigned long mask = BIT(offset);
236 	const unsigned port = offset / 8;
237 	unsigned long flags;
238 
239 	/* only the first 3 ports support interrupts */
240 	if (port > 2)
241 		return;
242 
243 	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
244 
245 	ws16c48gpio->irq_mask &= ~mask;
246 
247 	outb(0x80, ws16c48gpio->base + 7);
248 	outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
249 	outb(0xC0, ws16c48gpio->base + 7);
250 
251 	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
252 }
253 
ws16c48_irq_unmask(struct irq_data * data)254 static void ws16c48_irq_unmask(struct irq_data *data)
255 {
256 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
257 	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
258 	const unsigned long offset = irqd_to_hwirq(data);
259 	const unsigned long mask = BIT(offset);
260 	const unsigned port = offset / 8;
261 	unsigned long flags;
262 
263 	/* only the first 3 ports support interrupts */
264 	if (port > 2)
265 		return;
266 
267 	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
268 
269 	ws16c48gpio->irq_mask |= mask;
270 
271 	outb(0x80, ws16c48gpio->base + 7);
272 	outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
273 	outb(0xC0, ws16c48gpio->base + 7);
274 
275 	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
276 }
277 
ws16c48_irq_set_type(struct irq_data * data,unsigned flow_type)278 static int ws16c48_irq_set_type(struct irq_data *data, unsigned flow_type)
279 {
280 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
281 	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
282 	const unsigned long offset = irqd_to_hwirq(data);
283 	const unsigned long mask = BIT(offset);
284 	const unsigned port = offset / 8;
285 	unsigned long flags;
286 
287 	/* only the first 3 ports support interrupts */
288 	if (port > 2)
289 		return -EINVAL;
290 
291 	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
292 
293 	switch (flow_type) {
294 	case IRQ_TYPE_NONE:
295 		break;
296 	case IRQ_TYPE_EDGE_RISING:
297 		ws16c48gpio->flow_mask |= mask;
298 		break;
299 	case IRQ_TYPE_EDGE_FALLING:
300 		ws16c48gpio->flow_mask &= ~mask;
301 		break;
302 	default:
303 		raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
304 		return -EINVAL;
305 	}
306 
307 	outb(0x40, ws16c48gpio->base + 7);
308 	outb(ws16c48gpio->flow_mask >> (8*port), ws16c48gpio->base + 8 + port);
309 	outb(0xC0, ws16c48gpio->base + 7);
310 
311 	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
312 
313 	return 0;
314 }
315 
316 static struct irq_chip ws16c48_irqchip = {
317 	.name = "ws16c48",
318 	.irq_ack = ws16c48_irq_ack,
319 	.irq_mask = ws16c48_irq_mask,
320 	.irq_unmask = ws16c48_irq_unmask,
321 	.irq_set_type = ws16c48_irq_set_type
322 };
323 
ws16c48_irq_handler(int irq,void * dev_id)324 static irqreturn_t ws16c48_irq_handler(int irq, void *dev_id)
325 {
326 	struct ws16c48_gpio *const ws16c48gpio = dev_id;
327 	struct gpio_chip *const chip = &ws16c48gpio->chip;
328 	unsigned long int_pending;
329 	unsigned long port;
330 	unsigned long int_id;
331 	unsigned long gpio;
332 
333 	int_pending = inb(ws16c48gpio->base + 6) & 0x7;
334 	if (!int_pending)
335 		return IRQ_NONE;
336 
337 	/* loop until all pending interrupts are handled */
338 	do {
339 		for_each_set_bit(port, &int_pending, 3) {
340 			int_id = inb(ws16c48gpio->base + 8 + port);
341 			for_each_set_bit(gpio, &int_id, 8)
342 				generic_handle_domain_irq(chip->irq.domain,
343 							  gpio + 8*port);
344 		}
345 
346 		int_pending = inb(ws16c48gpio->base + 6) & 0x7;
347 	} while (int_pending);
348 
349 	return IRQ_HANDLED;
350 }
351 
352 #define WS16C48_NGPIO 48
353 static const char *ws16c48_names[WS16C48_NGPIO] = {
354 	"Port 0 Bit 0", "Port 0 Bit 1", "Port 0 Bit 2", "Port 0 Bit 3",
355 	"Port 0 Bit 4", "Port 0 Bit 5", "Port 0 Bit 6", "Port 0 Bit 7",
356 	"Port 1 Bit 0", "Port 1 Bit 1", "Port 1 Bit 2", "Port 1 Bit 3",
357 	"Port 1 Bit 4", "Port 1 Bit 5", "Port 1 Bit 6", "Port 1 Bit 7",
358 	"Port 2 Bit 0", "Port 2 Bit 1", "Port 2 Bit 2", "Port 2 Bit 3",
359 	"Port 2 Bit 4", "Port 2 Bit 5", "Port 2 Bit 6", "Port 2 Bit 7",
360 	"Port 3 Bit 0", "Port 3 Bit 1", "Port 3 Bit 2", "Port 3 Bit 3",
361 	"Port 3 Bit 4", "Port 3 Bit 5", "Port 3 Bit 6", "Port 3 Bit 7",
362 	"Port 4 Bit 0", "Port 4 Bit 1", "Port 4 Bit 2", "Port 4 Bit 3",
363 	"Port 4 Bit 4", "Port 4 Bit 5", "Port 4 Bit 6", "Port 4 Bit 7",
364 	"Port 5 Bit 0", "Port 5 Bit 1", "Port 5 Bit 2", "Port 5 Bit 3",
365 	"Port 5 Bit 4", "Port 5 Bit 5", "Port 5 Bit 6", "Port 5 Bit 7"
366 };
367 
ws16c48_irq_init_hw(struct gpio_chip * gc)368 static int ws16c48_irq_init_hw(struct gpio_chip *gc)
369 {
370 	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(gc);
371 
372 	/* Disable IRQ by default */
373 	outb(0x80, ws16c48gpio->base + 7);
374 	outb(0, ws16c48gpio->base + 8);
375 	outb(0, ws16c48gpio->base + 9);
376 	outb(0, ws16c48gpio->base + 10);
377 	outb(0xC0, ws16c48gpio->base + 7);
378 
379 	return 0;
380 }
381 
ws16c48_probe(struct device * dev,unsigned int id)382 static int ws16c48_probe(struct device *dev, unsigned int id)
383 {
384 	struct ws16c48_gpio *ws16c48gpio;
385 	const char *const name = dev_name(dev);
386 	struct gpio_irq_chip *girq;
387 	int err;
388 
389 	ws16c48gpio = devm_kzalloc(dev, sizeof(*ws16c48gpio), GFP_KERNEL);
390 	if (!ws16c48gpio)
391 		return -ENOMEM;
392 
393 	if (!devm_request_region(dev, base[id], WS16C48_EXTENT, name)) {
394 		dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
395 			base[id], base[id] + WS16C48_EXTENT);
396 		return -EBUSY;
397 	}
398 
399 	ws16c48gpio->chip.label = name;
400 	ws16c48gpio->chip.parent = dev;
401 	ws16c48gpio->chip.owner = THIS_MODULE;
402 	ws16c48gpio->chip.base = -1;
403 	ws16c48gpio->chip.ngpio = WS16C48_NGPIO;
404 	ws16c48gpio->chip.names = ws16c48_names;
405 	ws16c48gpio->chip.get_direction = ws16c48_gpio_get_direction;
406 	ws16c48gpio->chip.direction_input = ws16c48_gpio_direction_input;
407 	ws16c48gpio->chip.direction_output = ws16c48_gpio_direction_output;
408 	ws16c48gpio->chip.get = ws16c48_gpio_get;
409 	ws16c48gpio->chip.get_multiple = ws16c48_gpio_get_multiple;
410 	ws16c48gpio->chip.set = ws16c48_gpio_set;
411 	ws16c48gpio->chip.set_multiple = ws16c48_gpio_set_multiple;
412 	ws16c48gpio->base = base[id];
413 
414 	girq = &ws16c48gpio->chip.irq;
415 	girq->chip = &ws16c48_irqchip;
416 	/* This will let us handle the parent IRQ in the driver */
417 	girq->parent_handler = NULL;
418 	girq->num_parents = 0;
419 	girq->parents = NULL;
420 	girq->default_type = IRQ_TYPE_NONE;
421 	girq->handler = handle_edge_irq;
422 	girq->init_hw = ws16c48_irq_init_hw;
423 
424 	raw_spin_lock_init(&ws16c48gpio->lock);
425 
426 	err = devm_gpiochip_add_data(dev, &ws16c48gpio->chip, ws16c48gpio);
427 	if (err) {
428 		dev_err(dev, "GPIO registering failed (%d)\n", err);
429 		return err;
430 	}
431 
432 	err = devm_request_irq(dev, irq[id], ws16c48_irq_handler, IRQF_SHARED,
433 		name, ws16c48gpio);
434 	if (err) {
435 		dev_err(dev, "IRQ handler registering failed (%d)\n", err);
436 		return err;
437 	}
438 
439 	return 0;
440 }
441 
442 static struct isa_driver ws16c48_driver = {
443 	.probe = ws16c48_probe,
444 	.driver = {
445 		.name = "ws16c48"
446 	},
447 };
448 
449 module_isa_driver(ws16c48_driver, num_ws16c48);
450 
451 MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
452 MODULE_DESCRIPTION("WinSystems WS16C48 GPIO driver");
453 MODULE_LICENSE("GPL v2");
454