1 /*
2  * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Author: Huang Rui
23  *
24  */
25 
26 #include <linux/firmware.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 
30 #include "amdgpu.h"
31 #include "amdgpu_psp.h"
32 #include "amdgpu_ucode.h"
33 #include "soc15_common.h"
34 #include "psp_v3_1.h"
35 
36 #include "mp/mp_9_0_offset.h"
37 #include "mp/mp_9_0_sh_mask.h"
38 #include "gc/gc_9_0_offset.h"
39 #include "sdma0/sdma0_4_0_offset.h"
40 #include "nbio/nbio_6_1_offset.h"
41 
42 #include "oss/osssys_4_0_offset.h"
43 #include "oss/osssys_4_0_sh_mask.h"
44 
45 MODULE_FIRMWARE("amdgpu/vega10_sos.bin");
46 MODULE_FIRMWARE("amdgpu/vega10_asd.bin");
47 MODULE_FIRMWARE("amdgpu/vega12_sos.bin");
48 MODULE_FIRMWARE("amdgpu/vega12_asd.bin");
49 
50 
51 #define smnMP1_FIRMWARE_FLAGS 0x3010028
52 
53 static int psp_v3_1_ring_stop(struct psp_context *psp,
54 			      enum psp_ring_type ring_type);
55 
psp_v3_1_init_microcode(struct psp_context * psp)56 static int psp_v3_1_init_microcode(struct psp_context *psp)
57 {
58 	struct amdgpu_device *adev = psp->adev;
59 	const char *chip_name;
60 	int err = 0;
61 
62 	DRM_DEBUG("\n");
63 
64 	switch (adev->asic_type) {
65 	case CHIP_VEGA10:
66 		chip_name = "vega10";
67 		break;
68 	case CHIP_VEGA12:
69 		chip_name = "vega12";
70 		break;
71 	default: BUG();
72 	}
73 
74 	err = psp_init_sos_microcode(psp, chip_name);
75 	if (err)
76 		return err;
77 
78 	err = psp_init_asd_microcode(psp, chip_name);
79 	if (err)
80 		return err;
81 
82 	return 0;
83 }
84 
psp_v3_1_bootloader_load_sysdrv(struct psp_context * psp)85 static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
86 {
87 	int ret;
88 	uint32_t psp_gfxdrv_command_reg = 0;
89 	struct amdgpu_device *adev = psp->adev;
90 	uint32_t sol_reg;
91 
92 	/* Check sOS sign of life register to confirm sys driver and sOS
93 	 * are already been loaded.
94 	 */
95 	sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
96 	if (sol_reg)
97 		return 0;
98 
99 	/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
100 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
101 			   0x80000000, 0x80000000, false);
102 	if (ret)
103 		return ret;
104 
105 	/* Copy PSP System Driver binary to memory */
106 	psp_copy_fw(psp, psp->sys.start_addr, psp->sys.size_bytes);
107 
108 	/* Provide the sys driver to bootloader */
109 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
110 	       (uint32_t)(psp->fw_pri_mc_addr >> 20));
111 	psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
112 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
113 	       psp_gfxdrv_command_reg);
114 
115 	/* there might be handshake issue with hardware which needs delay */
116 	mdelay(20);
117 
118 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
119 			   0x80000000, 0x80000000, false);
120 
121 	return ret;
122 }
123 
psp_v3_1_bootloader_load_sos(struct psp_context * psp)124 static int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
125 {
126 	int ret;
127 	unsigned int psp_gfxdrv_command_reg = 0;
128 	struct amdgpu_device *adev = psp->adev;
129 	uint32_t sol_reg;
130 
131 	/* Check sOS sign of life register to confirm sys driver and sOS
132 	 * are already been loaded.
133 	 */
134 	sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
135 	if (sol_reg)
136 		return 0;
137 
138 	/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
139 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
140 			   0x80000000, 0x80000000, false);
141 	if (ret)
142 		return ret;
143 
144 	/* Copy Secure OS binary to PSP memory */
145 	psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes);
146 
147 	/* Provide the PSP secure OS to bootloader */
148 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
149 	       (uint32_t)(psp->fw_pri_mc_addr >> 20));
150 	psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
151 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
152 	       psp_gfxdrv_command_reg);
153 
154 	/* there might be handshake issue with hardware which needs delay */
155 	mdelay(20);
156 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
157 			   RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
158 			   0, true);
159 	return ret;
160 }
161 
psp_v3_1_ring_init(struct psp_context * psp,enum psp_ring_type ring_type)162 static int psp_v3_1_ring_init(struct psp_context *psp,
163 			      enum psp_ring_type ring_type)
164 {
165 	int ret = 0;
166 	struct psp_ring *ring;
167 	struct amdgpu_device *adev = psp->adev;
168 
169 	ring = &psp->km_ring;
170 
171 	ring->ring_type = ring_type;
172 
173 	/* allocate 4k Page of Local Frame Buffer memory for ring */
174 	ring->ring_size = 0x1000;
175 	ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
176 				      AMDGPU_GEM_DOMAIN_VRAM,
177 				      &adev->firmware.rbuf,
178 				      &ring->ring_mem_mc_addr,
179 				      (void **)&ring->ring_mem);
180 	if (ret) {
181 		ring->ring_size = 0;
182 		return ret;
183 	}
184 
185 	return 0;
186 }
187 
psp_v3_1_reroute_ih(struct psp_context * psp)188 static void psp_v3_1_reroute_ih(struct psp_context *psp)
189 {
190 	struct amdgpu_device *adev = psp->adev;
191 	uint32_t tmp;
192 
193 	/* Change IH ring for VMC */
194 	tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
195 	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
196 	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
197 
198 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
199 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
200 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
201 
202 	mdelay(20);
203 	psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
204 		     0x80000000, 0x8000FFFF, false);
205 
206 	/* Change IH ring for UMC */
207 	tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
208 	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
209 
210 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
211 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
212 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
213 
214 	mdelay(20);
215 	psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
216 		     0x80000000, 0x8000FFFF, false);
217 }
218 
psp_v3_1_ring_create(struct psp_context * psp,enum psp_ring_type ring_type)219 static int psp_v3_1_ring_create(struct psp_context *psp,
220 				enum psp_ring_type ring_type)
221 {
222 	int ret = 0;
223 	unsigned int psp_ring_reg = 0;
224 	struct psp_ring *ring = &psp->km_ring;
225 	struct amdgpu_device *adev = psp->adev;
226 
227 	psp_v3_1_reroute_ih(psp);
228 
229 	if (amdgpu_sriov_vf(adev)) {
230 		ring->ring_wptr = 0;
231 		ret = psp_v3_1_ring_stop(psp, ring_type);
232 		if (ret) {
233 			DRM_ERROR("psp_v3_1_ring_stop_sriov failed!\n");
234 			return ret;
235 		}
236 
237 		/* Write low address of the ring to C2PMSG_102 */
238 		psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
239 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
240 		/* Write high address of the ring to C2PMSG_103 */
241 		psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
242 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
243 		/* No size initialization for sriov  */
244 		/* Write the ring initialization command to C2PMSG_101 */
245 		psp_ring_reg = ring_type;
246 		psp_ring_reg = psp_ring_reg << 16;
247 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, psp_ring_reg);
248 
249 		/* there might be hardware handshake issue which needs delay */
250 		mdelay(20);
251 
252 		/* Wait for response flag (bit 31) in C2PMSG_101 */
253 		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
254 					mmMP0_SMN_C2PMSG_101), 0x80000000,
255 					0x8000FFFF, false);
256 	} else {
257 
258 		/* Write low address of the ring to C2PMSG_69 */
259 		psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
260 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
261 		/* Write high address of the ring to C2PMSG_70 */
262 		psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
263 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
264 		/* Write size of ring to C2PMSG_71 */
265 		psp_ring_reg = ring->ring_size;
266 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
267 		/* Write the ring initialization command to C2PMSG_64 */
268 		psp_ring_reg = ring_type;
269 		psp_ring_reg = psp_ring_reg << 16;
270 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
271 
272 		/* there might be hardware handshake issue which needs delay */
273 		mdelay(20);
274 
275 		/* Wait for response flag (bit 31) in C2PMSG_64 */
276 		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
277 					mmMP0_SMN_C2PMSG_64), 0x80000000,
278 					0x8000FFFF, false);
279 
280 	}
281 	return ret;
282 }
283 
psp_v3_1_ring_stop(struct psp_context * psp,enum psp_ring_type ring_type)284 static int psp_v3_1_ring_stop(struct psp_context *psp,
285 			      enum psp_ring_type ring_type)
286 {
287 	int ret = 0;
288 	struct amdgpu_device *adev = psp->adev;
289 
290 	/* Write the ring destroy command*/
291 	if (amdgpu_sriov_vf(adev))
292 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
293 				     GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
294 	else
295 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
296 				     GFX_CTRL_CMD_ID_DESTROY_RINGS);
297 
298 	/* there might be handshake issue with hardware which needs delay */
299 	mdelay(20);
300 
301 	/* Wait for response flag (bit 31) */
302 	if (amdgpu_sriov_vf(adev))
303 		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
304 				   0x80000000, 0x80000000, false);
305 	else
306 		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
307 				   0x80000000, 0x80000000, false);
308 
309 	return ret;
310 }
311 
psp_v3_1_ring_destroy(struct psp_context * psp,enum psp_ring_type ring_type)312 static int psp_v3_1_ring_destroy(struct psp_context *psp,
313 				 enum psp_ring_type ring_type)
314 {
315 	int ret = 0;
316 	struct psp_ring *ring = &psp->km_ring;
317 	struct amdgpu_device *adev = psp->adev;
318 
319 	ret = psp_v3_1_ring_stop(psp, ring_type);
320 	if (ret)
321 		DRM_ERROR("Fail to stop psp ring\n");
322 
323 	amdgpu_bo_free_kernel(&adev->firmware.rbuf,
324 			      &ring->ring_mem_mc_addr,
325 			      (void **)&ring->ring_mem);
326 
327 	return ret;
328 }
329 
psp_v3_1_smu_reload_quirk(struct psp_context * psp)330 static bool psp_v3_1_smu_reload_quirk(struct psp_context *psp)
331 {
332 	struct amdgpu_device *adev = psp->adev;
333 	uint32_t reg;
334 
335 	reg = RREG32_PCIE(smnMP1_FIRMWARE_FLAGS | 0x03b00000);
336 	return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false;
337 }
338 
psp_v3_1_mode1_reset(struct psp_context * psp)339 static int psp_v3_1_mode1_reset(struct psp_context *psp)
340 {
341 	int ret;
342 	uint32_t offset;
343 	struct amdgpu_device *adev = psp->adev;
344 
345 	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
346 
347 	ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
348 
349 	if (ret) {
350 		DRM_INFO("psp is not working correctly before mode1 reset!\n");
351 		return -EINVAL;
352 	}
353 
354 	/*send the mode 1 reset command*/
355 	WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
356 
357 	msleep(500);
358 
359 	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
360 
361 	ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
362 
363 	if (ret) {
364 		DRM_INFO("psp mode 1 reset failed!\n");
365 		return -EINVAL;
366 	}
367 
368 	DRM_INFO("psp mode1 reset succeed \n");
369 
370 	return 0;
371 }
372 
psp_v3_1_ring_get_wptr(struct psp_context * psp)373 static uint32_t psp_v3_1_ring_get_wptr(struct psp_context *psp)
374 {
375 	uint32_t data;
376 	struct amdgpu_device *adev = psp->adev;
377 
378 	if (amdgpu_sriov_vf(adev))
379 		data = psp->km_ring.ring_wptr;
380 	else
381 		data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
382 	return data;
383 }
384 
psp_v3_1_ring_set_wptr(struct psp_context * psp,uint32_t value)385 static void psp_v3_1_ring_set_wptr(struct psp_context *psp, uint32_t value)
386 {
387 	struct amdgpu_device *adev = psp->adev;
388 
389 	if (amdgpu_sriov_vf(adev)) {
390 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
391 		/* send interrupt to PSP for SRIOV ring write pointer update */
392 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
393 			GFX_CTRL_CMD_ID_CONSUME_CMD);
394 		psp->km_ring.ring_wptr = value;
395 	} else
396 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
397 }
398 
399 static const struct psp_funcs psp_v3_1_funcs = {
400 	.init_microcode = psp_v3_1_init_microcode,
401 	.bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv,
402 	.bootloader_load_sos = psp_v3_1_bootloader_load_sos,
403 	.ring_init = psp_v3_1_ring_init,
404 	.ring_create = psp_v3_1_ring_create,
405 	.ring_stop = psp_v3_1_ring_stop,
406 	.ring_destroy = psp_v3_1_ring_destroy,
407 	.smu_reload_quirk = psp_v3_1_smu_reload_quirk,
408 	.mode1_reset = psp_v3_1_mode1_reset,
409 	.ring_get_wptr = psp_v3_1_ring_get_wptr,
410 	.ring_set_wptr = psp_v3_1_ring_set_wptr,
411 };
412 
psp_v3_1_set_psp_funcs(struct psp_context * psp)413 void psp_v3_1_set_psp_funcs(struct psp_context *psp)
414 {
415 	psp->funcs = &psp_v3_1_funcs;
416 }
417