1 /*
2 * Copyright 2016-2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "kfd_device_queue_manager.h"
25 #include "vega10_enum.h"
26 #include "gc/gc_9_0_offset.h"
27 #include "gc/gc_9_0_sh_mask.h"
28 #include "sdma0/sdma0_4_0_sh_mask.h"
29
30 static int update_qpd_v9(struct device_queue_manager *dqm,
31 struct qcm_process_device *qpd);
32 static void init_sdma_vm_v9(struct device_queue_manager *dqm, struct queue *q,
33 struct qcm_process_device *qpd);
34
device_queue_manager_init_v9(struct device_queue_manager_asic_ops * asic_ops)35 void device_queue_manager_init_v9(
36 struct device_queue_manager_asic_ops *asic_ops)
37 {
38 asic_ops->update_qpd = update_qpd_v9;
39 asic_ops->init_sdma_vm = init_sdma_vm_v9;
40 asic_ops->mqd_manager_init = mqd_manager_init_v9;
41 }
42
compute_sh_mem_bases_64bit(struct kfd_process_device * pdd)43 static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd)
44 {
45 uint32_t shared_base = pdd->lds_base >> 48;
46 uint32_t private_base = pdd->scratch_base >> 48;
47
48 return (shared_base << SH_MEM_BASES__SHARED_BASE__SHIFT) |
49 private_base;
50 }
51
update_qpd_v9(struct device_queue_manager * dqm,struct qcm_process_device * qpd)52 static int update_qpd_v9(struct device_queue_manager *dqm,
53 struct qcm_process_device *qpd)
54 {
55 struct kfd_process_device *pdd;
56
57 pdd = qpd_to_pdd(qpd);
58
59 /* check if sh_mem_config register already configured */
60 if (qpd->sh_mem_config == 0) {
61 qpd->sh_mem_config =
62 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
63 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
64
65 if (dqm->dev->device_info->asic_family == CHIP_ALDEBARAN) {
66 /* Aldebaran can safely support different XNACK modes
67 * per process
68 */
69 if (!pdd->process->xnack_enabled)
70 qpd->sh_mem_config |=
71 1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT;
72 } else if (dqm->dev->noretry &&
73 !dqm->dev->use_iommu_v2) {
74 qpd->sh_mem_config |=
75 1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT;
76 }
77
78 qpd->sh_mem_ape1_limit = 0;
79 qpd->sh_mem_ape1_base = 0;
80 }
81
82 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd);
83
84 pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases);
85
86 return 0;
87 }
88
init_sdma_vm_v9(struct device_queue_manager * dqm,struct queue * q,struct qcm_process_device * qpd)89 static void init_sdma_vm_v9(struct device_queue_manager *dqm, struct queue *q,
90 struct qcm_process_device *qpd)
91 {
92 /* Not needed on SDMAv4 any more */
93 q->properties.sdma_vm_addr = 0;
94 }
95