1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef KFD_PM4_HEADERS_DIQ_H_ 25 #define KFD_PM4_HEADERS_DIQ_H_ 26 27 /*--------------------_INDIRECT_BUFFER-------------------- */ 28 29 #ifndef _PM4__INDIRECT_BUFFER_DEFINED 30 #define _PM4__INDIRECT_BUFFER_DEFINED 31 enum _INDIRECT_BUFFER_cache_policy_enum { 32 cache_policy___indirect_buffer__lru = 0, 33 cache_policy___indirect_buffer__stream = 1, 34 cache_policy___indirect_buffer__bypass = 2 35 }; 36 37 enum { 38 IT_INDIRECT_BUFFER_PASID = 0x5C 39 }; 40 41 struct pm4__indirect_buffer_pasid { 42 union { 43 union PM4_MES_TYPE_3_HEADER header; /* header */ 44 unsigned int ordinal1; 45 }; 46 47 union { 48 struct { 49 unsigned int reserved1:2; 50 unsigned int ib_base_lo:30; 51 } bitfields2; 52 unsigned int ordinal2; 53 }; 54 55 union { 56 struct { 57 unsigned int ib_base_hi:16; 58 unsigned int reserved2:16; 59 } bitfields3; 60 unsigned int ordinal3; 61 }; 62 63 union { 64 unsigned int control; 65 unsigned int ordinal4; 66 }; 67 68 union { 69 struct { 70 unsigned int pasid:10; 71 unsigned int reserved4:22; 72 } bitfields5; 73 unsigned int ordinal5; 74 }; 75 76 }; 77 78 #endif 79 80 /*--------------------_RELEASE_MEM-------------------- */ 81 82 #ifndef _PM4__RELEASE_MEM_DEFINED 83 #define _PM4__RELEASE_MEM_DEFINED 84 enum _RELEASE_MEM_event_index_enum { 85 event_index___release_mem__end_of_pipe = 5, 86 event_index___release_mem__shader_done = 6 87 }; 88 89 enum _RELEASE_MEM_cache_policy_enum { 90 cache_policy___release_mem__lru = 0, 91 cache_policy___release_mem__stream = 1, 92 cache_policy___release_mem__bypass = 2 93 }; 94 95 enum _RELEASE_MEM_dst_sel_enum { 96 dst_sel___release_mem__memory_controller = 0, 97 dst_sel___release_mem__tc_l2 = 1, 98 dst_sel___release_mem__queue_write_pointer_register = 2, 99 dst_sel___release_mem__queue_write_pointer_poll_mask_bit = 3 100 }; 101 102 enum _RELEASE_MEM_int_sel_enum { 103 int_sel___release_mem__none = 0, 104 int_sel___release_mem__send_interrupt_only = 1, 105 int_sel___release_mem__send_interrupt_after_write_confirm = 2, 106 int_sel___release_mem__send_data_after_write_confirm = 3 107 }; 108 109 enum _RELEASE_MEM_data_sel_enum { 110 data_sel___release_mem__none = 0, 111 data_sel___release_mem__send_32_bit_low = 1, 112 data_sel___release_mem__send_64_bit_data = 2, 113 data_sel___release_mem__send_gpu_clock_counter = 3, 114 data_sel___release_mem__send_cp_perfcounter_hi_lo = 4, 115 data_sel___release_mem__store_gds_data_to_memory = 5 116 }; 117 118 struct pm4__release_mem { 119 union { 120 union PM4_MES_TYPE_3_HEADER header; /*header */ 121 unsigned int ordinal1; 122 }; 123 124 union { 125 struct { 126 unsigned int event_type:6; 127 unsigned int reserved1:2; 128 enum _RELEASE_MEM_event_index_enum event_index:4; 129 unsigned int tcl1_vol_action_ena:1; 130 unsigned int tc_vol_action_ena:1; 131 unsigned int reserved2:1; 132 unsigned int tc_wb_action_ena:1; 133 unsigned int tcl1_action_ena:1; 134 unsigned int tc_action_ena:1; 135 unsigned int reserved3:6; 136 unsigned int atc:1; 137 enum _RELEASE_MEM_cache_policy_enum cache_policy:2; 138 unsigned int reserved4:5; 139 } bitfields2; 140 unsigned int ordinal2; 141 }; 142 143 union { 144 struct { 145 unsigned int reserved5:16; 146 enum _RELEASE_MEM_dst_sel_enum dst_sel:2; 147 unsigned int reserved6:6; 148 enum _RELEASE_MEM_int_sel_enum int_sel:3; 149 unsigned int reserved7:2; 150 enum _RELEASE_MEM_data_sel_enum data_sel:3; 151 } bitfields3; 152 unsigned int ordinal3; 153 }; 154 155 union { 156 struct { 157 unsigned int reserved8:2; 158 unsigned int address_lo_32b:30; 159 } bitfields4; 160 struct { 161 unsigned int reserved9:3; 162 unsigned int address_lo_64b:29; 163 } bitfields5; 164 unsigned int ordinal4; 165 }; 166 167 unsigned int address_hi; 168 169 unsigned int data_lo; 170 171 unsigned int data_hi; 172 173 }; 174 #endif 175 176 177 /*--------------------_SET_CONFIG_REG-------------------- */ 178 179 #ifndef _PM4__SET_CONFIG_REG_DEFINED 180 #define _PM4__SET_CONFIG_REG_DEFINED 181 182 struct pm4__set_config_reg { 183 union { 184 union PM4_MES_TYPE_3_HEADER header; /*header */ 185 unsigned int ordinal1; 186 }; 187 188 union { 189 struct { 190 unsigned int reg_offset:16; 191 unsigned int reserved1:7; 192 unsigned int vmid_shift:5; 193 unsigned int insert_vmid:1; 194 unsigned int reserved2:3; 195 } bitfields2; 196 unsigned int ordinal2; 197 }; 198 199 unsigned int reg_data[1]; /*1..N of these fields */ 200 201 }; 202 #endif 203 204 /*--------------------_WAIT_REG_MEM-------------------- */ 205 206 #ifndef _PM4__WAIT_REG_MEM_DEFINED 207 #define _PM4__WAIT_REG_MEM_DEFINED 208 enum _WAIT_REG_MEM_function_enum { 209 function___wait_reg_mem__always_pass = 0, 210 function___wait_reg_mem__less_than_ref_value = 1, 211 function___wait_reg_mem__less_than_equal_to_the_ref_value = 2, 212 function___wait_reg_mem__equal_to_the_reference_value = 3, 213 function___wait_reg_mem__not_equal_reference_value = 4, 214 function___wait_reg_mem__greater_than_or_equal_reference_value = 5, 215 function___wait_reg_mem__greater_than_reference_value = 6, 216 function___wait_reg_mem__reserved = 7 217 }; 218 219 enum _WAIT_REG_MEM_mem_space_enum { 220 mem_space___wait_reg_mem__register_space = 0, 221 mem_space___wait_reg_mem__memory_space = 1 222 }; 223 224 enum _WAIT_REG_MEM_operation_enum { 225 operation___wait_reg_mem__wait_reg_mem = 0, 226 operation___wait_reg_mem__wr_wait_wr_reg = 1 227 }; 228 229 struct pm4__wait_reg_mem { 230 union { 231 union PM4_MES_TYPE_3_HEADER header; /*header */ 232 unsigned int ordinal1; 233 }; 234 235 union { 236 struct { 237 enum _WAIT_REG_MEM_function_enum function:3; 238 unsigned int reserved1:1; 239 enum _WAIT_REG_MEM_mem_space_enum mem_space:2; 240 enum _WAIT_REG_MEM_operation_enum operation:2; 241 unsigned int reserved2:24; 242 } bitfields2; 243 unsigned int ordinal2; 244 }; 245 246 union { 247 struct { 248 unsigned int reserved3:2; 249 unsigned int memory_poll_addr_lo:30; 250 } bitfields3; 251 struct { 252 unsigned int register_poll_addr:16; 253 unsigned int reserved4:16; 254 } bitfields4; 255 struct { 256 unsigned int register_write_addr:16; 257 unsigned int reserved5:16; 258 } bitfields5; 259 unsigned int ordinal3; 260 }; 261 262 union { 263 struct { 264 unsigned int poll_address_hi:16; 265 unsigned int reserved6:16; 266 } bitfields6; 267 struct { 268 unsigned int register_write_addr:16; 269 unsigned int reserved7:16; 270 } bitfields7; 271 unsigned int ordinal4; 272 }; 273 274 unsigned int reference; 275 276 unsigned int mask; 277 278 union { 279 struct { 280 unsigned int poll_interval:16; 281 unsigned int reserved8:16; 282 } bitfields8; 283 unsigned int ordinal7; 284 }; 285 286 }; 287 #endif 288 289 290 #endif /* KFD_PM4_HEADERS_DIQ_H_ */ 291