1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #ifndef SMU_11_0_7_PPTABLE_H 23 #define SMU_11_0_7_PPTABLE_H 24 25 26 #define SMU_11_0_7_TABLE_FORMAT_REVISION 15 27 28 //// POWERPLAYTABLE::ulPlatformCaps 29 #define SMU_11_0_7_PP_PLATFORM_CAP_POWERPLAY 0x1 // This cap indicates whether CCC need to show Powerplay page. 30 #define SMU_11_0_7_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 0x2 // This cap indicates whether power source notificaiton is done by SBIOS instead of OS. 31 #define SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC 0x4 // This cap indicates whether DC mode notificaiton is done by GPIO pin directly. 32 #define SMU_11_0_7_PP_PLATFORM_CAP_BACO 0x8 // This cap indicates whether board supports the BACO circuitry. 33 #define SMU_11_0_7_PP_PLATFORM_CAP_MACO 0x10 // This cap indicates whether board supports the MACO circuitry. 34 #define SMU_11_0_7_PP_PLATFORM_CAP_SHADOWPSTATE 0x20 // This cap indicates whether board supports the Shadow Pstate. 35 36 // SMU_11_0_7_PP_THERMALCONTROLLER - Thermal Controller Type 37 #define SMU_11_0_7_PP_THERMALCONTROLLER_NONE 0 38 #define SMU_11_0_7_PP_THERMALCONTROLLER_SIENNA_CICHLID 28 39 40 #define SMU_11_0_7_PP_OVERDRIVE_VERSION 0x81 // OverDrive 8 Table Version 0.2 41 #define SMU_11_0_7_PP_POWERSAVINGCLOCK_VERSION 0x01 // Power Saving Clock Table Version 1.00 42 43 enum SMU_11_0_7_ODFEATURE_CAP { 44 SMU_11_0_7_ODCAP_GFXCLK_LIMITS = 0, 45 SMU_11_0_7_ODCAP_GFXCLK_CURVE, 46 SMU_11_0_7_ODCAP_UCLK_LIMITS, 47 SMU_11_0_7_ODCAP_POWER_LIMIT, 48 SMU_11_0_7_ODCAP_FAN_ACOUSTIC_LIMIT, 49 SMU_11_0_7_ODCAP_FAN_SPEED_MIN, 50 SMU_11_0_7_ODCAP_TEMPERATURE_FAN, 51 SMU_11_0_7_ODCAP_TEMPERATURE_SYSTEM, 52 SMU_11_0_7_ODCAP_MEMORY_TIMING_TUNE, 53 SMU_11_0_7_ODCAP_FAN_ZERO_RPM_CONTROL, 54 SMU_11_0_7_ODCAP_AUTO_UV_ENGINE, 55 SMU_11_0_7_ODCAP_AUTO_OC_ENGINE, 56 SMU_11_0_7_ODCAP_AUTO_OC_MEMORY, 57 SMU_11_0_7_ODCAP_FAN_CURVE, 58 SMU_11_0_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT, 59 SMU_11_0_7_ODCAP_POWER_MODE, 60 SMU_11_0_7_ODCAP_COUNT, 61 }; 62 63 enum SMU_11_0_7_ODFEATURE_ID { 64 SMU_11_0_7_ODFEATURE_GFXCLK_LIMITS = 1 << SMU_11_0_7_ODCAP_GFXCLK_LIMITS, //GFXCLK Limit feature 65 SMU_11_0_7_ODFEATURE_GFXCLK_CURVE = 1 << SMU_11_0_7_ODCAP_GFXCLK_CURVE, //GFXCLK Curve feature 66 SMU_11_0_7_ODFEATURE_UCLK_LIMITS = 1 << SMU_11_0_7_ODCAP_UCLK_LIMITS, //UCLK Limit feature 67 SMU_11_0_7_ODFEATURE_POWER_LIMIT = 1 << SMU_11_0_7_ODCAP_POWER_LIMIT, //Power Limit feature 68 SMU_11_0_7_ODFEATURE_FAN_ACOUSTIC_LIMIT = 1 << SMU_11_0_7_ODCAP_FAN_ACOUSTIC_LIMIT, //Fan Acoustic RPM feature 69 SMU_11_0_7_ODFEATURE_FAN_SPEED_MIN = 1 << SMU_11_0_7_ODCAP_FAN_SPEED_MIN, //Minimum Fan Speed feature 70 SMU_11_0_7_ODFEATURE_TEMPERATURE_FAN = 1 << SMU_11_0_7_ODCAP_TEMPERATURE_FAN, //Fan Target Temperature Limit feature 71 SMU_11_0_7_ODFEATURE_TEMPERATURE_SYSTEM = 1 << SMU_11_0_7_ODCAP_TEMPERATURE_SYSTEM, //Operating Temperature Limit feature 72 SMU_11_0_7_ODFEATURE_MEMORY_TIMING_TUNE = 1 << SMU_11_0_7_ODCAP_MEMORY_TIMING_TUNE, //AC Timing Tuning feature 73 SMU_11_0_7_ODFEATURE_FAN_ZERO_RPM_CONTROL = 1 << SMU_11_0_7_ODCAP_FAN_ZERO_RPM_CONTROL, //Zero RPM feature 74 SMU_11_0_7_ODFEATURE_AUTO_UV_ENGINE = 1 << SMU_11_0_7_ODCAP_AUTO_UV_ENGINE, //Auto Under Volt GFXCLK feature 75 SMU_11_0_7_ODFEATURE_AUTO_OC_ENGINE = 1 << SMU_11_0_7_ODCAP_AUTO_OC_ENGINE, //Auto Over Clock GFXCLK feature 76 SMU_11_0_7_ODFEATURE_AUTO_OC_MEMORY = 1 << SMU_11_0_7_ODCAP_AUTO_OC_MEMORY, //Auto Over Clock MCLK feature 77 SMU_11_0_7_ODFEATURE_FAN_CURVE = 1 << SMU_11_0_7_ODCAP_FAN_CURVE, //Fan Curve feature 78 SMU_11_0_ODFEATURE_AUTO_FAN_ACOUSTIC_LIMIT = 1 << SMU_11_0_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT, //Auto Fan Acoustic RPM feature 79 SMU_11_0_7_ODFEATURE_POWER_MODE = 1 << SMU_11_0_7_ODCAP_POWER_MODE, //Optimized GPU Power Mode feature 80 SMU_11_0_7_ODFEATURE_COUNT = 16, 81 }; 82 83 #define SMU_11_0_7_MAX_ODFEATURE 32 //Maximum Number of OD Features 84 85 enum SMU_11_0_7_ODSETTING_ID { 86 SMU_11_0_7_ODSETTING_GFXCLKFMAX = 0, 87 SMU_11_0_7_ODSETTING_GFXCLKFMIN, 88 SMU_11_0_7_ODSETTING_CUSTOM_GFX_VF_CURVE_A, 89 SMU_11_0_7_ODSETTING_CUSTOM_GFX_VF_CURVE_B, 90 SMU_11_0_7_ODSETTING_CUSTOM_GFX_VF_CURVE_C, 91 SMU_11_0_7_ODSETTING_CUSTOM_CURVE_VFT_FMIN, 92 SMU_11_0_7_ODSETTING_UCLKFMIN, 93 SMU_11_0_7_ODSETTING_UCLKFMAX, 94 SMU_11_0_7_ODSETTING_POWERPERCENTAGE, 95 SMU_11_0_7_ODSETTING_FANRPMMIN, 96 SMU_11_0_7_ODSETTING_FANRPMACOUSTICLIMIT, 97 SMU_11_0_7_ODSETTING_FANTARGETTEMPERATURE, 98 SMU_11_0_7_ODSETTING_OPERATINGTEMPMAX, 99 SMU_11_0_7_ODSETTING_ACTIMING, 100 SMU_11_0_7_ODSETTING_FAN_ZERO_RPM_CONTROL, 101 SMU_11_0_7_ODSETTING_AUTOUVENGINE, 102 SMU_11_0_7_ODSETTING_AUTOOCENGINE, 103 SMU_11_0_7_ODSETTING_AUTOOCMEMORY, 104 SMU_11_0_7_ODSETTING_FAN_CURVE_TEMPERATURE_1, 105 SMU_11_0_7_ODSETTING_FAN_CURVE_SPEED_1, 106 SMU_11_0_7_ODSETTING_FAN_CURVE_TEMPERATURE_2, 107 SMU_11_0_7_ODSETTING_FAN_CURVE_SPEED_2, 108 SMU_11_0_7_ODSETTING_FAN_CURVE_TEMPERATURE_3, 109 SMU_11_0_7_ODSETTING_FAN_CURVE_SPEED_3, 110 SMU_11_0_7_ODSETTING_FAN_CURVE_TEMPERATURE_4, 111 SMU_11_0_7_ODSETTING_FAN_CURVE_SPEED_4, 112 SMU_11_0_7_ODSETTING_FAN_CURVE_TEMPERATURE_5, 113 SMU_11_0_7_ODSETTING_FAN_CURVE_SPEED_5, 114 SMU_11_0_7_ODSETTING_AUTO_FAN_ACOUSTIC_LIMIT, 115 SMU_11_0_7_ODSETTING_POWER_MODE, 116 SMU_11_0_7_ODSETTING_COUNT, 117 }; 118 #define SMU_11_0_7_MAX_ODSETTING 64 //Maximum Number of ODSettings 119 120 enum SMU_11_0_7_PWRMODE_SETTING { 121 SMU_11_0_7_PMSETTING_POWER_LIMIT_QUIET = 0, 122 SMU_11_0_7_PMSETTING_POWER_LIMIT_BALANCE, 123 SMU_11_0_7_PMSETTING_POWER_LIMIT_TURBO, 124 SMU_11_0_7_PMSETTING_POWER_LIMIT_RAGE, 125 SMU_11_0_7_PMSETTING_ACOUSTIC_TEMP_QUIET, 126 SMU_11_0_7_PMSETTING_ACOUSTIC_TEMP_BALANCE, 127 SMU_11_0_7_PMSETTING_ACOUSTIC_TEMP_TURBO, 128 SMU_11_0_7_PMSETTING_ACOUSTIC_TEMP_RAGE, 129 }; 130 #define SMU_11_0_7_MAX_PMSETTING 32 //Maximum Number of PowerMode Settings 131 132 struct smu_11_0_7_overdrive_table 133 { 134 uint8_t revision; //Revision = SMU_11_0_7_PP_OVERDRIVE_VERSION 135 uint8_t reserve[3]; //Zero filled field reserved for future use 136 uint32_t feature_count; //Total number of supported features 137 uint32_t setting_count; //Total number of supported settings 138 uint8_t cap[SMU_11_0_7_MAX_ODFEATURE]; //OD feature support flags 139 uint32_t max[SMU_11_0_7_MAX_ODSETTING]; //default maximum settings 140 uint32_t min[SMU_11_0_7_MAX_ODSETTING]; //default minimum settings 141 int16_t pm_setting[SMU_11_0_7_MAX_PMSETTING]; //Optimized power mode feature settings 142 } __attribute__((packed)); 143 144 enum SMU_11_0_7_PPCLOCK_ID { 145 SMU_11_0_7_PPCLOCK_GFXCLK = 0, 146 SMU_11_0_7_PPCLOCK_SOCCLK, 147 SMU_11_0_7_PPCLOCK_UCLK, 148 SMU_11_0_7_PPCLOCK_FCLK, 149 SMU_11_0_7_PPCLOCK_DCLK_0, 150 SMU_11_0_7_PPCLOCK_VCLK_0, 151 SMU_11_0_7_PPCLOCK_DCLK_1, 152 SMU_11_0_7_PPCLOCK_VCLK_1, 153 SMU_11_0_7_PPCLOCK_DCEFCLK, 154 SMU_11_0_7_PPCLOCK_DISPCLK, 155 SMU_11_0_7_PPCLOCK_PIXCLK, 156 SMU_11_0_7_PPCLOCK_PHYCLK, 157 SMU_11_0_7_PPCLOCK_DTBCLK, 158 SMU_11_0_7_PPCLOCK_COUNT, 159 }; 160 #define SMU_11_0_7_MAX_PPCLOCK 16 //Maximum Number of PP Clocks 161 162 struct smu_11_0_7_power_saving_clock_table 163 { 164 uint8_t revision; //Revision = SMU_11_0_7_PP_POWERSAVINGCLOCK_VERSION 165 uint8_t reserve[3]; //Zero filled field reserved for future use 166 uint32_t count; //power_saving_clock_count = SMU_11_0_7_PPCLOCK_COUNT 167 uint32_t max[SMU_11_0_7_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Maximum array In MHz 168 uint32_t min[SMU_11_0_7_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Minimum array In MHz 169 } __attribute__((packed)); 170 171 struct smu_11_0_7_powerplay_table 172 { 173 struct atom_common_table_header header; //For sienna_cichlid, header.format_revision = 15, header.content_revision = 0 174 uint8_t table_revision; //For sienna_cichlid, table_revision = 2 175 uint16_t table_size; //Driver portion table size. The offset to smc_pptable including header size 176 uint32_t golden_pp_id; //PPGen use only: PP Table ID on the Golden Data Base 177 uint32_t golden_revision; //PPGen use only: PP Table Revision on the Golden Data Base 178 uint16_t format_id; //PPGen use only: PPTable for different ASICs. For sienna_cichlid this should be 0x80 179 uint32_t platform_caps; //POWERPLAYABLE::ulPlatformCaps 180 181 uint8_t thermal_controller_type; //one of SMU_11_0_7_PP_THERMALCONTROLLER 182 183 uint16_t small_power_limit1; 184 uint16_t small_power_limit2; 185 uint16_t boost_power_limit; //For Gemini Board, when the slave adapter is in BACO mode, the master adapter will use this boost power limit instead of the default power limit to boost the power limit. 186 uint16_t software_shutdown_temp; 187 188 uint16_t reserve[8]; //Zero filled field reserved for future use 189 190 struct smu_11_0_7_power_saving_clock_table power_saving_clock; 191 struct smu_11_0_7_overdrive_table overdrive_table; 192 193 PPTable_t smc_pptable; //PPTable_t in smu11_driver_if.h 194 } __attribute__((packed)); 195 196 #endif 197