1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * i.MX8 NWL MIPI DSI host driver
4 *
5 * Copyright (C) 2017 NXP
6 * Copyright (C) 2020 Purism SPC
7 */
8
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
11 #include <linux/irq.h>
12 #include <linux/math64.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
15 #include <linux/mux/consumer.h>
16 #include <linux/of.h>
17 #include <linux/of_platform.h>
18 #include <linux/phy/phy.h>
19 #include <linux/regmap.h>
20 #include <linux/reset.h>
21 #include <linux/sys_soc.h>
22 #include <linux/time64.h>
23
24 #include <drm/drm_atomic_state_helper.h>
25 #include <drm/drm_bridge.h>
26 #include <drm/drm_mipi_dsi.h>
27 #include <drm/drm_of.h>
28 #include <drm/drm_panel.h>
29 #include <drm/drm_print.h>
30
31 #include <video/mipi_display.h>
32
33 #include "nwl-dsi.h"
34
35 #define DRV_NAME "nwl-dsi"
36
37 /* i.MX8 NWL quirks */
38 /* i.MX8MQ errata E11418 */
39 #define E11418_HS_MODE_QUIRK BIT(0)
40
41 #define NWL_DSI_MIPI_FIFO_TIMEOUT msecs_to_jiffies(500)
42
43 enum transfer_direction {
44 DSI_PACKET_SEND,
45 DSI_PACKET_RECEIVE,
46 };
47
48 #define NWL_DSI_ENDPOINT_LCDIF 0
49 #define NWL_DSI_ENDPOINT_DCSS 1
50
51 struct nwl_dsi_transfer {
52 const struct mipi_dsi_msg *msg;
53 struct mipi_dsi_packet packet;
54 struct completion completed;
55
56 int status; /* status of transmission */
57 enum transfer_direction direction;
58 bool need_bta;
59 u8 cmd;
60 u16 rx_word_count;
61 size_t tx_len; /* in bytes */
62 size_t rx_len; /* in bytes */
63 };
64
65 struct nwl_dsi {
66 struct drm_bridge bridge;
67 struct mipi_dsi_host dsi_host;
68 struct drm_bridge *panel_bridge;
69 struct device *dev;
70 struct phy *phy;
71 union phy_configure_opts phy_cfg;
72 unsigned int quirks;
73
74 struct regmap *regmap;
75 int irq;
76 /*
77 * The DSI host controller needs this reset sequence according to NWL:
78 * 1. Deassert pclk reset to get access to DSI regs
79 * 2. Configure DSI Host and DPHY and enable DPHY
80 * 3. Deassert ESC and BYTE resets to allow host TX operations)
81 * 4. Send DSI cmds to configure peripheral (handled by panel drv)
82 * 5. Deassert DPI reset so DPI receives pixels and starts sending
83 * DSI data
84 *
85 * TODO: Since panel_bridges do their DSI setup in enable we
86 * currently have 4. and 5. swapped.
87 */
88 struct reset_control *rst_byte;
89 struct reset_control *rst_esc;
90 struct reset_control *rst_dpi;
91 struct reset_control *rst_pclk;
92 struct mux_control *mux;
93
94 /* DSI clocks */
95 struct clk *phy_ref_clk;
96 struct clk *rx_esc_clk;
97 struct clk *tx_esc_clk;
98 struct clk *core_clk;
99 /*
100 * hardware bug: the i.MX8MQ needs this clock on during reset
101 * even when not using LCDIF.
102 */
103 struct clk *lcdif_clk;
104
105 /* dsi lanes */
106 u32 lanes;
107 enum mipi_dsi_pixel_format format;
108 struct drm_display_mode mode;
109 unsigned long dsi_mode_flags;
110 int error;
111
112 struct nwl_dsi_transfer *xfer;
113 };
114
115 static const struct regmap_config nwl_dsi_regmap_config = {
116 .reg_bits = 16,
117 .val_bits = 32,
118 .reg_stride = 4,
119 .max_register = NWL_DSI_IRQ_MASK2,
120 .name = DRV_NAME,
121 };
122
bridge_to_dsi(struct drm_bridge * bridge)123 static inline struct nwl_dsi *bridge_to_dsi(struct drm_bridge *bridge)
124 {
125 return container_of(bridge, struct nwl_dsi, bridge);
126 }
127
nwl_dsi_clear_error(struct nwl_dsi * dsi)128 static int nwl_dsi_clear_error(struct nwl_dsi *dsi)
129 {
130 int ret = dsi->error;
131
132 dsi->error = 0;
133 return ret;
134 }
135
nwl_dsi_write(struct nwl_dsi * dsi,unsigned int reg,u32 val)136 static void nwl_dsi_write(struct nwl_dsi *dsi, unsigned int reg, u32 val)
137 {
138 int ret;
139
140 if (dsi->error)
141 return;
142
143 ret = regmap_write(dsi->regmap, reg, val);
144 if (ret < 0) {
145 DRM_DEV_ERROR(dsi->dev,
146 "Failed to write NWL DSI reg 0x%x: %d\n", reg,
147 ret);
148 dsi->error = ret;
149 }
150 }
151
nwl_dsi_read(struct nwl_dsi * dsi,u32 reg)152 static u32 nwl_dsi_read(struct nwl_dsi *dsi, u32 reg)
153 {
154 unsigned int val;
155 int ret;
156
157 if (dsi->error)
158 return 0;
159
160 ret = regmap_read(dsi->regmap, reg, &val);
161 if (ret < 0) {
162 DRM_DEV_ERROR(dsi->dev, "Failed to read NWL DSI reg 0x%x: %d\n",
163 reg, ret);
164 dsi->error = ret;
165 }
166 return val;
167 }
168
nwl_dsi_get_dpi_pixel_format(enum mipi_dsi_pixel_format format)169 static int nwl_dsi_get_dpi_pixel_format(enum mipi_dsi_pixel_format format)
170 {
171 switch (format) {
172 case MIPI_DSI_FMT_RGB565:
173 return NWL_DSI_PIXEL_FORMAT_16;
174 case MIPI_DSI_FMT_RGB666:
175 return NWL_DSI_PIXEL_FORMAT_18L;
176 case MIPI_DSI_FMT_RGB666_PACKED:
177 return NWL_DSI_PIXEL_FORMAT_18;
178 case MIPI_DSI_FMT_RGB888:
179 return NWL_DSI_PIXEL_FORMAT_24;
180 default:
181 return -EINVAL;
182 }
183 }
184
185 /*
186 * ps2bc - Picoseconds to byte clock cycles
187 */
ps2bc(struct nwl_dsi * dsi,unsigned long long ps)188 static u32 ps2bc(struct nwl_dsi *dsi, unsigned long long ps)
189 {
190 u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
191
192 return DIV64_U64_ROUND_UP(ps * dsi->mode.clock * bpp,
193 dsi->lanes * 8ULL * NSEC_PER_SEC);
194 }
195
196 /*
197 * ui2bc - UI time periods to byte clock cycles
198 */
ui2bc(struct nwl_dsi * dsi,unsigned long long ui)199 static u32 ui2bc(struct nwl_dsi *dsi, unsigned long long ui)
200 {
201 u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
202
203 return DIV64_U64_ROUND_UP(ui * dsi->lanes,
204 dsi->mode.clock * 1000 * bpp);
205 }
206
207 /*
208 * us2bc - micro seconds to lp clock cycles
209 */
us2lp(u32 lp_clk_rate,unsigned long us)210 static u32 us2lp(u32 lp_clk_rate, unsigned long us)
211 {
212 return DIV_ROUND_UP(us * lp_clk_rate, USEC_PER_SEC);
213 }
214
nwl_dsi_config_host(struct nwl_dsi * dsi)215 static int nwl_dsi_config_host(struct nwl_dsi *dsi)
216 {
217 u32 cycles;
218 struct phy_configure_opts_mipi_dphy *cfg = &dsi->phy_cfg.mipi_dphy;
219
220 if (dsi->lanes < 1 || dsi->lanes > 4)
221 return -EINVAL;
222
223 DRM_DEV_DEBUG_DRIVER(dsi->dev, "DSI Lanes %d\n", dsi->lanes);
224 nwl_dsi_write(dsi, NWL_DSI_CFG_NUM_LANES, dsi->lanes - 1);
225
226 if (dsi->dsi_mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
227 nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x01);
228 nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x01);
229 } else {
230 nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x00);
231 nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x00);
232 }
233
234 /* values in byte clock cycles */
235 cycles = ui2bc(dsi, cfg->clk_pre);
236 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_pre: 0x%x\n", cycles);
237 nwl_dsi_write(dsi, NWL_DSI_CFG_T_PRE, cycles);
238 cycles = ps2bc(dsi, cfg->lpx + cfg->clk_prepare + cfg->clk_zero);
239 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap (pre): 0x%x\n", cycles);
240 cycles += ui2bc(dsi, cfg->clk_pre);
241 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_post: 0x%x\n", cycles);
242 nwl_dsi_write(dsi, NWL_DSI_CFG_T_POST, cycles);
243 cycles = ps2bc(dsi, cfg->hs_exit);
244 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap: 0x%x\n", cycles);
245 nwl_dsi_write(dsi, NWL_DSI_CFG_TX_GAP, cycles);
246
247 nwl_dsi_write(dsi, NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP, 0x01);
248 nwl_dsi_write(dsi, NWL_DSI_CFG_HTX_TO_COUNT, 0x00);
249 nwl_dsi_write(dsi, NWL_DSI_CFG_LRX_H_TO_COUNT, 0x00);
250 nwl_dsi_write(dsi, NWL_DSI_CFG_BTA_H_TO_COUNT, 0x00);
251 /* In LP clock cycles */
252 cycles = us2lp(cfg->lp_clk_rate, cfg->wakeup);
253 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_twakeup: 0x%x\n", cycles);
254 nwl_dsi_write(dsi, NWL_DSI_CFG_TWAKEUP, cycles);
255
256 return nwl_dsi_clear_error(dsi);
257 }
258
nwl_dsi_config_dpi(struct nwl_dsi * dsi)259 static int nwl_dsi_config_dpi(struct nwl_dsi *dsi)
260 {
261 u32 mode;
262 int color_format;
263 bool burst_mode;
264 int hfront_porch, hback_porch, vfront_porch, vback_porch;
265 int hsync_len, vsync_len;
266
267 hfront_porch = dsi->mode.hsync_start - dsi->mode.hdisplay;
268 hsync_len = dsi->mode.hsync_end - dsi->mode.hsync_start;
269 hback_porch = dsi->mode.htotal - dsi->mode.hsync_end;
270
271 vfront_porch = dsi->mode.vsync_start - dsi->mode.vdisplay;
272 vsync_len = dsi->mode.vsync_end - dsi->mode.vsync_start;
273 vback_porch = dsi->mode.vtotal - dsi->mode.vsync_end;
274
275 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hfront_porch = %d\n", hfront_porch);
276 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hback_porch = %d\n", hback_porch);
277 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hsync_len = %d\n", hsync_len);
278 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hdisplay = %d\n", dsi->mode.hdisplay);
279 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vfront_porch = %d\n", vfront_porch);
280 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vback_porch = %d\n", vback_porch);
281 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vsync_len = %d\n", vsync_len);
282 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vactive = %d\n", dsi->mode.vdisplay);
283 DRM_DEV_DEBUG_DRIVER(dsi->dev, "clock = %d kHz\n", dsi->mode.clock);
284
285 color_format = nwl_dsi_get_dpi_pixel_format(dsi->format);
286 if (color_format < 0) {
287 DRM_DEV_ERROR(dsi->dev, "Invalid color format 0x%x\n",
288 dsi->format);
289 return color_format;
290 }
291 DRM_DEV_DEBUG_DRIVER(dsi->dev, "pixel fmt = %d\n", dsi->format);
292
293 nwl_dsi_write(dsi, NWL_DSI_INTERFACE_COLOR_CODING, NWL_DSI_DPI_24_BIT);
294 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FORMAT, color_format);
295 /*
296 * Adjusting input polarity based on the video mode results in
297 * a black screen so always pick active low:
298 */
299 nwl_dsi_write(dsi, NWL_DSI_VSYNC_POLARITY,
300 NWL_DSI_VSYNC_POLARITY_ACTIVE_LOW);
301 nwl_dsi_write(dsi, NWL_DSI_HSYNC_POLARITY,
302 NWL_DSI_HSYNC_POLARITY_ACTIVE_LOW);
303
304 burst_mode = (dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_BURST) &&
305 !(dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE);
306
307 if (burst_mode) {
308 nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, NWL_DSI_VM_BURST_MODE);
309 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL, 256);
310 } else {
311 mode = ((dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) ?
312 NWL_DSI_VM_BURST_MODE_WITH_SYNC_PULSES :
313 NWL_DSI_VM_NON_BURST_MODE_WITH_SYNC_EVENTS);
314 nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, mode);
315 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL,
316 dsi->mode.hdisplay);
317 }
318
319 nwl_dsi_write(dsi, NWL_DSI_HFP, hfront_porch);
320 nwl_dsi_write(dsi, NWL_DSI_HBP, hback_porch);
321 nwl_dsi_write(dsi, NWL_DSI_HSA, hsync_len);
322
323 nwl_dsi_write(dsi, NWL_DSI_ENABLE_MULT_PKTS, 0x0);
324 nwl_dsi_write(dsi, NWL_DSI_BLLP_MODE, 0x1);
325 nwl_dsi_write(dsi, NWL_DSI_USE_NULL_PKT_BLLP, 0x0);
326 nwl_dsi_write(dsi, NWL_DSI_VC, 0x0);
327
328 nwl_dsi_write(dsi, NWL_DSI_PIXEL_PAYLOAD_SIZE, dsi->mode.hdisplay);
329 nwl_dsi_write(dsi, NWL_DSI_VACTIVE, dsi->mode.vdisplay - 1);
330 nwl_dsi_write(dsi, NWL_DSI_VBP, vback_porch);
331 nwl_dsi_write(dsi, NWL_DSI_VFP, vfront_porch);
332
333 return nwl_dsi_clear_error(dsi);
334 }
335
nwl_dsi_init_interrupts(struct nwl_dsi * dsi)336 static int nwl_dsi_init_interrupts(struct nwl_dsi *dsi)
337 {
338 u32 irq_enable;
339
340 nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK, 0xffffffff);
341 nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK2, 0x7);
342
343 irq_enable = ~(u32)(NWL_DSI_TX_PKT_DONE_MASK |
344 NWL_DSI_RX_PKT_HDR_RCVD_MASK |
345 NWL_DSI_TX_FIFO_OVFLW_MASK |
346 NWL_DSI_HS_TX_TIMEOUT_MASK);
347
348 nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK, irq_enable);
349
350 return nwl_dsi_clear_error(dsi);
351 }
352
nwl_dsi_host_attach(struct mipi_dsi_host * dsi_host,struct mipi_dsi_device * device)353 static int nwl_dsi_host_attach(struct mipi_dsi_host *dsi_host,
354 struct mipi_dsi_device *device)
355 {
356 struct nwl_dsi *dsi = container_of(dsi_host, struct nwl_dsi, dsi_host);
357 struct device *dev = dsi->dev;
358
359 DRM_DEV_INFO(dev, "lanes=%u, format=0x%x flags=0x%lx\n", device->lanes,
360 device->format, device->mode_flags);
361
362 if (device->lanes < 1 || device->lanes > 4)
363 return -EINVAL;
364
365 dsi->lanes = device->lanes;
366 dsi->format = device->format;
367 dsi->dsi_mode_flags = device->mode_flags;
368
369 return 0;
370 }
371
nwl_dsi_read_packet(struct nwl_dsi * dsi,u32 status)372 static bool nwl_dsi_read_packet(struct nwl_dsi *dsi, u32 status)
373 {
374 struct device *dev = dsi->dev;
375 struct nwl_dsi_transfer *xfer = dsi->xfer;
376 int err;
377 u8 *payload = xfer->msg->rx_buf;
378 u32 val;
379 u16 word_count;
380 u8 channel;
381 u8 data_type;
382
383 xfer->status = 0;
384
385 if (xfer->rx_word_count == 0) {
386 if (!(status & NWL_DSI_RX_PKT_HDR_RCVD))
387 return false;
388 /* Get the RX header and parse it */
389 val = nwl_dsi_read(dsi, NWL_DSI_RX_PKT_HEADER);
390 err = nwl_dsi_clear_error(dsi);
391 if (err)
392 xfer->status = err;
393 word_count = NWL_DSI_WC(val);
394 channel = NWL_DSI_RX_VC(val);
395 data_type = NWL_DSI_RX_DT(val);
396
397 if (channel != xfer->msg->channel) {
398 DRM_DEV_ERROR(dev,
399 "[%02X] Channel mismatch (%u != %u)\n",
400 xfer->cmd, channel, xfer->msg->channel);
401 xfer->status = -EINVAL;
402 return true;
403 }
404
405 switch (data_type) {
406 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
407 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
408 if (xfer->msg->rx_len > 1) {
409 /* read second byte */
410 payload[1] = word_count >> 8;
411 ++xfer->rx_len;
412 }
413 fallthrough;
414 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
415 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
416 if (xfer->msg->rx_len > 0) {
417 /* read first byte */
418 payload[0] = word_count & 0xff;
419 ++xfer->rx_len;
420 }
421 xfer->status = xfer->rx_len;
422 return true;
423 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
424 word_count &= 0xff;
425 DRM_DEV_ERROR(dev, "[%02X] DSI error report: 0x%02x\n",
426 xfer->cmd, word_count);
427 xfer->status = -EPROTO;
428 return true;
429 }
430
431 if (word_count > xfer->msg->rx_len) {
432 DRM_DEV_ERROR(dev,
433 "[%02X] Receive buffer too small: %zu (< %u)\n",
434 xfer->cmd, xfer->msg->rx_len, word_count);
435 xfer->status = -EINVAL;
436 return true;
437 }
438
439 xfer->rx_word_count = word_count;
440 } else {
441 /* Set word_count from previous header read */
442 word_count = xfer->rx_word_count;
443 }
444
445 /* If RX payload is not yet received, wait for it */
446 if (!(status & NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD))
447 return false;
448
449 /* Read the RX payload */
450 while (word_count >= 4) {
451 val = nwl_dsi_read(dsi, NWL_DSI_RX_PAYLOAD);
452 payload[0] = (val >> 0) & 0xff;
453 payload[1] = (val >> 8) & 0xff;
454 payload[2] = (val >> 16) & 0xff;
455 payload[3] = (val >> 24) & 0xff;
456 payload += 4;
457 xfer->rx_len += 4;
458 word_count -= 4;
459 }
460
461 if (word_count > 0) {
462 val = nwl_dsi_read(dsi, NWL_DSI_RX_PAYLOAD);
463 switch (word_count) {
464 case 3:
465 payload[2] = (val >> 16) & 0xff;
466 ++xfer->rx_len;
467 fallthrough;
468 case 2:
469 payload[1] = (val >> 8) & 0xff;
470 ++xfer->rx_len;
471 fallthrough;
472 case 1:
473 payload[0] = (val >> 0) & 0xff;
474 ++xfer->rx_len;
475 break;
476 }
477 }
478
479 xfer->status = xfer->rx_len;
480 err = nwl_dsi_clear_error(dsi);
481 if (err)
482 xfer->status = err;
483
484 return true;
485 }
486
nwl_dsi_finish_transmission(struct nwl_dsi * dsi,u32 status)487 static void nwl_dsi_finish_transmission(struct nwl_dsi *dsi, u32 status)
488 {
489 struct nwl_dsi_transfer *xfer = dsi->xfer;
490 bool end_packet = false;
491
492 if (!xfer)
493 return;
494
495 if (xfer->direction == DSI_PACKET_SEND &&
496 status & NWL_DSI_TX_PKT_DONE) {
497 xfer->status = xfer->tx_len;
498 end_packet = true;
499 } else if (status & NWL_DSI_DPHY_DIRECTION &&
500 ((status & (NWL_DSI_RX_PKT_HDR_RCVD |
501 NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD)))) {
502 end_packet = nwl_dsi_read_packet(dsi, status);
503 }
504
505 if (end_packet)
506 complete(&xfer->completed);
507 }
508
nwl_dsi_begin_transmission(struct nwl_dsi * dsi)509 static void nwl_dsi_begin_transmission(struct nwl_dsi *dsi)
510 {
511 struct nwl_dsi_transfer *xfer = dsi->xfer;
512 struct mipi_dsi_packet *pkt = &xfer->packet;
513 const u8 *payload;
514 size_t length;
515 u16 word_count;
516 u8 hs_mode;
517 u32 val;
518 u32 hs_workaround = 0;
519
520 /* Send the payload, if any */
521 length = pkt->payload_length;
522 payload = pkt->payload;
523
524 while (length >= 4) {
525 val = *(u32 *)payload;
526 hs_workaround |= !(val & 0xFFFF00);
527 nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val);
528 payload += 4;
529 length -= 4;
530 }
531 /* Send the rest of the payload */
532 val = 0;
533 switch (length) {
534 case 3:
535 val |= payload[2] << 16;
536 fallthrough;
537 case 2:
538 val |= payload[1] << 8;
539 hs_workaround |= !(val & 0xFFFF00);
540 fallthrough;
541 case 1:
542 val |= payload[0];
543 nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val);
544 break;
545 }
546 xfer->tx_len = pkt->payload_length;
547
548 /*
549 * Send the header
550 * header[0] = Virtual Channel + Data Type
551 * header[1] = Word Count LSB (LP) or first param (SP)
552 * header[2] = Word Count MSB (LP) or second param (SP)
553 */
554 word_count = pkt->header[1] | (pkt->header[2] << 8);
555 if (hs_workaround && (dsi->quirks & E11418_HS_MODE_QUIRK)) {
556 DRM_DEV_DEBUG_DRIVER(dsi->dev,
557 "Using hs mode workaround for cmd 0x%x\n",
558 xfer->cmd);
559 hs_mode = 1;
560 } else {
561 hs_mode = (xfer->msg->flags & MIPI_DSI_MSG_USE_LPM) ? 0 : 1;
562 }
563 val = NWL_DSI_WC(word_count) | NWL_DSI_TX_VC(xfer->msg->channel) |
564 NWL_DSI_TX_DT(xfer->msg->type) | NWL_DSI_HS_SEL(hs_mode) |
565 NWL_DSI_BTA_TX(xfer->need_bta);
566 nwl_dsi_write(dsi, NWL_DSI_PKT_CONTROL, val);
567
568 /* Send packet command */
569 nwl_dsi_write(dsi, NWL_DSI_SEND_PACKET, 0x1);
570 }
571
nwl_dsi_host_transfer(struct mipi_dsi_host * dsi_host,const struct mipi_dsi_msg * msg)572 static ssize_t nwl_dsi_host_transfer(struct mipi_dsi_host *dsi_host,
573 const struct mipi_dsi_msg *msg)
574 {
575 struct nwl_dsi *dsi = container_of(dsi_host, struct nwl_dsi, dsi_host);
576 struct nwl_dsi_transfer xfer;
577 ssize_t ret = 0;
578
579 /* Create packet to be sent */
580 dsi->xfer = &xfer;
581 ret = mipi_dsi_create_packet(&xfer.packet, msg);
582 if (ret < 0) {
583 dsi->xfer = NULL;
584 return ret;
585 }
586
587 if ((msg->type & MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM ||
588 msg->type & MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM ||
589 msg->type & MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM ||
590 msg->type & MIPI_DSI_DCS_READ) &&
591 msg->rx_len > 0 && msg->rx_buf)
592 xfer.direction = DSI_PACKET_RECEIVE;
593 else
594 xfer.direction = DSI_PACKET_SEND;
595
596 xfer.need_bta = (xfer.direction == DSI_PACKET_RECEIVE);
597 xfer.need_bta |= (msg->flags & MIPI_DSI_MSG_REQ_ACK) ? 1 : 0;
598 xfer.msg = msg;
599 xfer.status = -ETIMEDOUT;
600 xfer.rx_word_count = 0;
601 xfer.rx_len = 0;
602 xfer.cmd = 0x00;
603 if (msg->tx_len > 0)
604 xfer.cmd = ((u8 *)(msg->tx_buf))[0];
605 init_completion(&xfer.completed);
606
607 ret = clk_prepare_enable(dsi->rx_esc_clk);
608 if (ret < 0) {
609 DRM_DEV_ERROR(dsi->dev, "Failed to enable rx_esc clk: %zd\n",
610 ret);
611 return ret;
612 }
613 DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled rx_esc clk @%lu Hz\n",
614 clk_get_rate(dsi->rx_esc_clk));
615
616 /* Initiate the DSI packet transmision */
617 nwl_dsi_begin_transmission(dsi);
618
619 if (!wait_for_completion_timeout(&xfer.completed,
620 NWL_DSI_MIPI_FIFO_TIMEOUT)) {
621 DRM_DEV_ERROR(dsi_host->dev, "[%02X] DSI transfer timed out\n",
622 xfer.cmd);
623 ret = -ETIMEDOUT;
624 } else {
625 ret = xfer.status;
626 }
627
628 clk_disable_unprepare(dsi->rx_esc_clk);
629
630 return ret;
631 }
632
633 static const struct mipi_dsi_host_ops nwl_dsi_host_ops = {
634 .attach = nwl_dsi_host_attach,
635 .transfer = nwl_dsi_host_transfer,
636 };
637
nwl_dsi_irq_handler(int irq,void * data)638 static irqreturn_t nwl_dsi_irq_handler(int irq, void *data)
639 {
640 u32 irq_status;
641 struct nwl_dsi *dsi = data;
642
643 irq_status = nwl_dsi_read(dsi, NWL_DSI_IRQ_STATUS);
644
645 if (irq_status & NWL_DSI_TX_FIFO_OVFLW)
646 DRM_DEV_ERROR_RATELIMITED(dsi->dev, "tx fifo overflow\n");
647
648 if (irq_status & NWL_DSI_HS_TX_TIMEOUT)
649 DRM_DEV_ERROR_RATELIMITED(dsi->dev, "HS tx timeout\n");
650
651 if (irq_status & NWL_DSI_TX_PKT_DONE ||
652 irq_status & NWL_DSI_RX_PKT_HDR_RCVD ||
653 irq_status & NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD)
654 nwl_dsi_finish_transmission(dsi, irq_status);
655
656 return IRQ_HANDLED;
657 }
658
nwl_dsi_mode_set(struct nwl_dsi * dsi)659 static int nwl_dsi_mode_set(struct nwl_dsi *dsi)
660 {
661 struct device *dev = dsi->dev;
662 union phy_configure_opts *phy_cfg = &dsi->phy_cfg;
663 int ret;
664
665 if (!dsi->lanes) {
666 DRM_DEV_ERROR(dev, "Need DSI lanes: %d\n", dsi->lanes);
667 return -EINVAL;
668 }
669
670 ret = phy_init(dsi->phy);
671 if (ret < 0) {
672 DRM_DEV_ERROR(dev, "Failed to init DSI phy: %d\n", ret);
673 return ret;
674 }
675
676 ret = phy_configure(dsi->phy, phy_cfg);
677 if (ret < 0) {
678 DRM_DEV_ERROR(dev, "Failed to configure DSI phy: %d\n", ret);
679 goto uninit_phy;
680 }
681
682 ret = clk_prepare_enable(dsi->tx_esc_clk);
683 if (ret < 0) {
684 DRM_DEV_ERROR(dsi->dev, "Failed to enable tx_esc clk: %d\n",
685 ret);
686 goto uninit_phy;
687 }
688 DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled tx_esc clk @%lu Hz\n",
689 clk_get_rate(dsi->tx_esc_clk));
690
691 ret = nwl_dsi_config_host(dsi);
692 if (ret < 0) {
693 DRM_DEV_ERROR(dev, "Failed to set up DSI: %d", ret);
694 goto disable_clock;
695 }
696
697 ret = nwl_dsi_config_dpi(dsi);
698 if (ret < 0) {
699 DRM_DEV_ERROR(dev, "Failed to set up DPI: %d", ret);
700 goto disable_clock;
701 }
702
703 ret = phy_power_on(dsi->phy);
704 if (ret < 0) {
705 DRM_DEV_ERROR(dev, "Failed to power on DPHY (%d)\n", ret);
706 goto disable_clock;
707 }
708
709 ret = nwl_dsi_init_interrupts(dsi);
710 if (ret < 0)
711 goto power_off_phy;
712
713 return ret;
714
715 power_off_phy:
716 phy_power_off(dsi->phy);
717 disable_clock:
718 clk_disable_unprepare(dsi->tx_esc_clk);
719 uninit_phy:
720 phy_exit(dsi->phy);
721
722 return ret;
723 }
724
nwl_dsi_disable(struct nwl_dsi * dsi)725 static int nwl_dsi_disable(struct nwl_dsi *dsi)
726 {
727 struct device *dev = dsi->dev;
728
729 DRM_DEV_DEBUG_DRIVER(dev, "Disabling clocks and phy\n");
730
731 phy_power_off(dsi->phy);
732 phy_exit(dsi->phy);
733
734 /* Disabling the clock before the phy breaks enabling dsi again */
735 clk_disable_unprepare(dsi->tx_esc_clk);
736
737 return 0;
738 }
739
740 static void
nwl_dsi_bridge_atomic_disable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)741 nwl_dsi_bridge_atomic_disable(struct drm_bridge *bridge,
742 struct drm_bridge_state *old_bridge_state)
743 {
744 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
745 int ret;
746
747 nwl_dsi_disable(dsi);
748
749 ret = reset_control_assert(dsi->rst_dpi);
750 if (ret < 0) {
751 DRM_DEV_ERROR(dsi->dev, "Failed to assert DPI: %d\n", ret);
752 return;
753 }
754 ret = reset_control_assert(dsi->rst_byte);
755 if (ret < 0) {
756 DRM_DEV_ERROR(dsi->dev, "Failed to assert ESC: %d\n", ret);
757 return;
758 }
759 ret = reset_control_assert(dsi->rst_esc);
760 if (ret < 0) {
761 DRM_DEV_ERROR(dsi->dev, "Failed to assert BYTE: %d\n", ret);
762 return;
763 }
764 ret = reset_control_assert(dsi->rst_pclk);
765 if (ret < 0) {
766 DRM_DEV_ERROR(dsi->dev, "Failed to assert PCLK: %d\n", ret);
767 return;
768 }
769
770 clk_disable_unprepare(dsi->core_clk);
771 clk_disable_unprepare(dsi->lcdif_clk);
772
773 pm_runtime_put(dsi->dev);
774 }
775
nwl_dsi_get_dphy_params(struct nwl_dsi * dsi,const struct drm_display_mode * mode,union phy_configure_opts * phy_opts)776 static int nwl_dsi_get_dphy_params(struct nwl_dsi *dsi,
777 const struct drm_display_mode *mode,
778 union phy_configure_opts *phy_opts)
779 {
780 unsigned long rate;
781 int ret;
782
783 if (dsi->lanes < 1 || dsi->lanes > 4)
784 return -EINVAL;
785
786 /*
787 * So far the DPHY spec minimal timings work for both mixel
788 * dphy and nwl dsi host
789 */
790 ret = phy_mipi_dphy_get_default_config(mode->clock * 1000,
791 mipi_dsi_pixel_format_to_bpp(dsi->format), dsi->lanes,
792 &phy_opts->mipi_dphy);
793 if (ret < 0)
794 return ret;
795
796 rate = clk_get_rate(dsi->tx_esc_clk);
797 DRM_DEV_DEBUG_DRIVER(dsi->dev, "LP clk is @%lu Hz\n", rate);
798 phy_opts->mipi_dphy.lp_clk_rate = rate;
799
800 return 0;
801 }
802
803 static enum drm_mode_status
nwl_dsi_bridge_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)804 nwl_dsi_bridge_mode_valid(struct drm_bridge *bridge,
805 const struct drm_display_info *info,
806 const struct drm_display_mode *mode)
807 {
808 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
809 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
810
811 if (mode->clock * bpp > 15000000 * dsi->lanes)
812 return MODE_CLOCK_HIGH;
813
814 if (mode->clock * bpp < 80000 * dsi->lanes)
815 return MODE_CLOCK_LOW;
816
817 return MODE_OK;
818 }
819
nwl_dsi_bridge_atomic_check(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)820 static int nwl_dsi_bridge_atomic_check(struct drm_bridge *bridge,
821 struct drm_bridge_state *bridge_state,
822 struct drm_crtc_state *crtc_state,
823 struct drm_connector_state *conn_state)
824 {
825 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
826
827 /* At least LCDIF + NWL needs active high sync */
828 adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
829 adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
830
831 /*
832 * Do a full modeset if crtc_state->active is changed to be true.
833 * This ensures our ->mode_set() is called to get the DSI controller
834 * and the PHY ready to send DCS commands, when only the connector's
835 * DPMS is brought out of "Off" status.
836 */
837 if (crtc_state->active_changed && crtc_state->active)
838 crtc_state->mode_changed = true;
839
840 return 0;
841 }
842
843 static void
nwl_dsi_bridge_mode_set(struct drm_bridge * bridge,const struct drm_display_mode * mode,const struct drm_display_mode * adjusted_mode)844 nwl_dsi_bridge_mode_set(struct drm_bridge *bridge,
845 const struct drm_display_mode *mode,
846 const struct drm_display_mode *adjusted_mode)
847 {
848 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
849 struct device *dev = dsi->dev;
850 union phy_configure_opts new_cfg;
851 unsigned long phy_ref_rate;
852 int ret;
853
854 ret = nwl_dsi_get_dphy_params(dsi, adjusted_mode, &new_cfg);
855 if (ret < 0)
856 return;
857
858 phy_ref_rate = clk_get_rate(dsi->phy_ref_clk);
859 DRM_DEV_DEBUG_DRIVER(dev, "PHY at ref rate: %lu\n", phy_ref_rate);
860 /* Save the new desired phy config */
861 memcpy(&dsi->phy_cfg, &new_cfg, sizeof(new_cfg));
862
863 memcpy(&dsi->mode, adjusted_mode, sizeof(dsi->mode));
864 drm_mode_debug_printmodeline(adjusted_mode);
865
866 pm_runtime_get_sync(dev);
867
868 if (clk_prepare_enable(dsi->lcdif_clk) < 0)
869 return;
870 if (clk_prepare_enable(dsi->core_clk) < 0)
871 return;
872
873 /* Step 1 from DSI reset-out instructions */
874 ret = reset_control_deassert(dsi->rst_pclk);
875 if (ret < 0) {
876 DRM_DEV_ERROR(dev, "Failed to deassert PCLK: %d\n", ret);
877 return;
878 }
879
880 /* Step 2 from DSI reset-out instructions */
881 nwl_dsi_mode_set(dsi);
882
883 /* Step 3 from DSI reset-out instructions */
884 ret = reset_control_deassert(dsi->rst_esc);
885 if (ret < 0) {
886 DRM_DEV_ERROR(dev, "Failed to deassert ESC: %d\n", ret);
887 return;
888 }
889 ret = reset_control_deassert(dsi->rst_byte);
890 if (ret < 0) {
891 DRM_DEV_ERROR(dev, "Failed to deassert BYTE: %d\n", ret);
892 return;
893 }
894 }
895
896 static void
nwl_dsi_bridge_atomic_enable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)897 nwl_dsi_bridge_atomic_enable(struct drm_bridge *bridge,
898 struct drm_bridge_state *old_bridge_state)
899 {
900 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
901 int ret;
902
903 /* Step 5 from DSI reset-out instructions */
904 ret = reset_control_deassert(dsi->rst_dpi);
905 if (ret < 0)
906 DRM_DEV_ERROR(dsi->dev, "Failed to deassert DPI: %d\n", ret);
907 }
908
nwl_dsi_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)909 static int nwl_dsi_bridge_attach(struct drm_bridge *bridge,
910 enum drm_bridge_attach_flags flags)
911 {
912 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
913 struct drm_bridge *panel_bridge;
914 struct drm_panel *panel;
915 int ret;
916
917 ret = drm_of_find_panel_or_bridge(dsi->dev->of_node, 1, 0, &panel,
918 &panel_bridge);
919 if (ret)
920 return ret;
921
922 if (panel) {
923 panel_bridge = drm_panel_bridge_add(panel);
924 if (IS_ERR(panel_bridge))
925 return PTR_ERR(panel_bridge);
926 }
927 dsi->panel_bridge = panel_bridge;
928
929 if (!dsi->panel_bridge)
930 return -EPROBE_DEFER;
931
932 return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge,
933 flags);
934 }
935
nwl_dsi_bridge_detach(struct drm_bridge * bridge)936 static void nwl_dsi_bridge_detach(struct drm_bridge *bridge)
937 { struct nwl_dsi *dsi = bridge_to_dsi(bridge);
938
939 drm_of_panel_bridge_remove(dsi->dev->of_node, 1, 0);
940 }
941
nwl_bridge_atomic_get_input_bus_fmts(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state,u32 output_fmt,unsigned int * num_input_fmts)942 static u32 *nwl_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
943 struct drm_bridge_state *bridge_state,
944 struct drm_crtc_state *crtc_state,
945 struct drm_connector_state *conn_state,
946 u32 output_fmt,
947 unsigned int *num_input_fmts)
948 {
949 u32 *input_fmts, input_fmt;
950
951 *num_input_fmts = 0;
952
953 switch (output_fmt) {
954 /* If MEDIA_BUS_FMT_FIXED is tested, return default bus format */
955 case MEDIA_BUS_FMT_FIXED:
956 input_fmt = MEDIA_BUS_FMT_RGB888_1X24;
957 break;
958 case MEDIA_BUS_FMT_RGB888_1X24:
959 case MEDIA_BUS_FMT_RGB666_1X18:
960 case MEDIA_BUS_FMT_RGB565_1X16:
961 input_fmt = output_fmt;
962 break;
963 default:
964 return NULL;
965 }
966
967 input_fmts = kcalloc(1, sizeof(*input_fmts), GFP_KERNEL);
968 if (!input_fmts)
969 return NULL;
970 input_fmts[0] = input_fmt;
971 *num_input_fmts = 1;
972
973 return input_fmts;
974 }
975
976 static const struct drm_bridge_funcs nwl_dsi_bridge_funcs = {
977 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
978 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
979 .atomic_reset = drm_atomic_helper_bridge_reset,
980 .atomic_check = nwl_dsi_bridge_atomic_check,
981 .atomic_enable = nwl_dsi_bridge_atomic_enable,
982 .atomic_disable = nwl_dsi_bridge_atomic_disable,
983 .atomic_get_input_bus_fmts = nwl_bridge_atomic_get_input_bus_fmts,
984 .mode_set = nwl_dsi_bridge_mode_set,
985 .mode_valid = nwl_dsi_bridge_mode_valid,
986 .attach = nwl_dsi_bridge_attach,
987 .detach = nwl_dsi_bridge_detach,
988 };
989
nwl_dsi_parse_dt(struct nwl_dsi * dsi)990 static int nwl_dsi_parse_dt(struct nwl_dsi *dsi)
991 {
992 struct platform_device *pdev = to_platform_device(dsi->dev);
993 struct clk *clk;
994 void __iomem *base;
995 int ret;
996
997 dsi->phy = devm_phy_get(dsi->dev, "dphy");
998 if (IS_ERR(dsi->phy)) {
999 ret = PTR_ERR(dsi->phy);
1000 if (ret != -EPROBE_DEFER)
1001 DRM_DEV_ERROR(dsi->dev, "Could not get PHY: %d\n", ret);
1002 return ret;
1003 }
1004
1005 clk = devm_clk_get(dsi->dev, "lcdif");
1006 if (IS_ERR(clk)) {
1007 ret = PTR_ERR(clk);
1008 DRM_DEV_ERROR(dsi->dev, "Failed to get lcdif clock: %d\n",
1009 ret);
1010 return ret;
1011 }
1012 dsi->lcdif_clk = clk;
1013
1014 clk = devm_clk_get(dsi->dev, "core");
1015 if (IS_ERR(clk)) {
1016 ret = PTR_ERR(clk);
1017 DRM_DEV_ERROR(dsi->dev, "Failed to get core clock: %d\n",
1018 ret);
1019 return ret;
1020 }
1021 dsi->core_clk = clk;
1022
1023 clk = devm_clk_get(dsi->dev, "phy_ref");
1024 if (IS_ERR(clk)) {
1025 ret = PTR_ERR(clk);
1026 DRM_DEV_ERROR(dsi->dev, "Failed to get phy_ref clock: %d\n",
1027 ret);
1028 return ret;
1029 }
1030 dsi->phy_ref_clk = clk;
1031
1032 clk = devm_clk_get(dsi->dev, "rx_esc");
1033 if (IS_ERR(clk)) {
1034 ret = PTR_ERR(clk);
1035 DRM_DEV_ERROR(dsi->dev, "Failed to get rx_esc clock: %d\n",
1036 ret);
1037 return ret;
1038 }
1039 dsi->rx_esc_clk = clk;
1040
1041 clk = devm_clk_get(dsi->dev, "tx_esc");
1042 if (IS_ERR(clk)) {
1043 ret = PTR_ERR(clk);
1044 DRM_DEV_ERROR(dsi->dev, "Failed to get tx_esc clock: %d\n",
1045 ret);
1046 return ret;
1047 }
1048 dsi->tx_esc_clk = clk;
1049
1050 dsi->mux = devm_mux_control_get(dsi->dev, NULL);
1051 if (IS_ERR(dsi->mux)) {
1052 ret = PTR_ERR(dsi->mux);
1053 if (ret != -EPROBE_DEFER)
1054 DRM_DEV_ERROR(dsi->dev, "Failed to get mux: %d\n", ret);
1055 return ret;
1056 }
1057
1058 base = devm_platform_ioremap_resource(pdev, 0);
1059 if (IS_ERR(base))
1060 return PTR_ERR(base);
1061
1062 dsi->regmap =
1063 devm_regmap_init_mmio(dsi->dev, base, &nwl_dsi_regmap_config);
1064 if (IS_ERR(dsi->regmap)) {
1065 ret = PTR_ERR(dsi->regmap);
1066 DRM_DEV_ERROR(dsi->dev, "Failed to create NWL DSI regmap: %d\n",
1067 ret);
1068 return ret;
1069 }
1070
1071 dsi->irq = platform_get_irq(pdev, 0);
1072 if (dsi->irq < 0) {
1073 DRM_DEV_ERROR(dsi->dev, "Failed to get device IRQ: %d\n",
1074 dsi->irq);
1075 return dsi->irq;
1076 }
1077
1078 dsi->rst_pclk = devm_reset_control_get_exclusive(dsi->dev, "pclk");
1079 if (IS_ERR(dsi->rst_pclk)) {
1080 DRM_DEV_ERROR(dsi->dev, "Failed to get pclk reset: %ld\n",
1081 PTR_ERR(dsi->rst_pclk));
1082 return PTR_ERR(dsi->rst_pclk);
1083 }
1084 dsi->rst_byte = devm_reset_control_get_exclusive(dsi->dev, "byte");
1085 if (IS_ERR(dsi->rst_byte)) {
1086 DRM_DEV_ERROR(dsi->dev, "Failed to get byte reset: %ld\n",
1087 PTR_ERR(dsi->rst_byte));
1088 return PTR_ERR(dsi->rst_byte);
1089 }
1090 dsi->rst_esc = devm_reset_control_get_exclusive(dsi->dev, "esc");
1091 if (IS_ERR(dsi->rst_esc)) {
1092 DRM_DEV_ERROR(dsi->dev, "Failed to get esc reset: %ld\n",
1093 PTR_ERR(dsi->rst_esc));
1094 return PTR_ERR(dsi->rst_esc);
1095 }
1096 dsi->rst_dpi = devm_reset_control_get_exclusive(dsi->dev, "dpi");
1097 if (IS_ERR(dsi->rst_dpi)) {
1098 DRM_DEV_ERROR(dsi->dev, "Failed to get dpi reset: %ld\n",
1099 PTR_ERR(dsi->rst_dpi));
1100 return PTR_ERR(dsi->rst_dpi);
1101 }
1102 return 0;
1103 }
1104
nwl_dsi_select_input(struct nwl_dsi * dsi)1105 static int nwl_dsi_select_input(struct nwl_dsi *dsi)
1106 {
1107 struct device_node *remote;
1108 u32 use_dcss = 1;
1109 int ret;
1110
1111 remote = of_graph_get_remote_node(dsi->dev->of_node, 0,
1112 NWL_DSI_ENDPOINT_LCDIF);
1113 if (remote) {
1114 use_dcss = 0;
1115 } else {
1116 remote = of_graph_get_remote_node(dsi->dev->of_node, 0,
1117 NWL_DSI_ENDPOINT_DCSS);
1118 if (!remote) {
1119 DRM_DEV_ERROR(dsi->dev,
1120 "No valid input endpoint found\n");
1121 return -EINVAL;
1122 }
1123 }
1124
1125 DRM_DEV_INFO(dsi->dev, "Using %s as input source\n",
1126 (use_dcss) ? "DCSS" : "LCDIF");
1127 ret = mux_control_try_select(dsi->mux, use_dcss);
1128 if (ret < 0)
1129 DRM_DEV_ERROR(dsi->dev, "Failed to select input: %d\n", ret);
1130
1131 of_node_put(remote);
1132 return ret;
1133 }
1134
nwl_dsi_deselect_input(struct nwl_dsi * dsi)1135 static int nwl_dsi_deselect_input(struct nwl_dsi *dsi)
1136 {
1137 int ret;
1138
1139 ret = mux_control_deselect(dsi->mux);
1140 if (ret < 0)
1141 DRM_DEV_ERROR(dsi->dev, "Failed to deselect input: %d\n", ret);
1142
1143 return ret;
1144 }
1145
1146 static const struct drm_bridge_timings nwl_dsi_timings = {
1147 .input_bus_flags = DRM_BUS_FLAG_DE_LOW,
1148 };
1149
1150 static const struct of_device_id nwl_dsi_dt_ids[] = {
1151 { .compatible = "fsl,imx8mq-nwl-dsi", },
1152 { /* sentinel */ }
1153 };
1154 MODULE_DEVICE_TABLE(of, nwl_dsi_dt_ids);
1155
1156 static const struct soc_device_attribute nwl_dsi_quirks_match[] = {
1157 { .soc_id = "i.MX8MQ", .revision = "2.0",
1158 .data = (void *)E11418_HS_MODE_QUIRK },
1159 { /* sentinel. */ },
1160 };
1161
nwl_dsi_probe(struct platform_device * pdev)1162 static int nwl_dsi_probe(struct platform_device *pdev)
1163 {
1164 struct device *dev = &pdev->dev;
1165 const struct soc_device_attribute *attr;
1166 struct nwl_dsi *dsi;
1167 int ret;
1168
1169 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1170 if (!dsi)
1171 return -ENOMEM;
1172
1173 dsi->dev = dev;
1174
1175 ret = nwl_dsi_parse_dt(dsi);
1176 if (ret)
1177 return ret;
1178
1179 ret = devm_request_irq(dev, dsi->irq, nwl_dsi_irq_handler, 0,
1180 dev_name(dev), dsi);
1181 if (ret < 0) {
1182 DRM_DEV_ERROR(dev, "Failed to request IRQ %d: %d\n", dsi->irq,
1183 ret);
1184 return ret;
1185 }
1186
1187 dsi->dsi_host.ops = &nwl_dsi_host_ops;
1188 dsi->dsi_host.dev = dev;
1189 ret = mipi_dsi_host_register(&dsi->dsi_host);
1190 if (ret) {
1191 DRM_DEV_ERROR(dev, "Failed to register MIPI host: %d\n", ret);
1192 return ret;
1193 }
1194
1195 attr = soc_device_match(nwl_dsi_quirks_match);
1196 if (attr)
1197 dsi->quirks = (uintptr_t)attr->data;
1198
1199 dsi->bridge.driver_private = dsi;
1200 dsi->bridge.funcs = &nwl_dsi_bridge_funcs;
1201 dsi->bridge.of_node = dev->of_node;
1202 dsi->bridge.timings = &nwl_dsi_timings;
1203
1204 dev_set_drvdata(dev, dsi);
1205 pm_runtime_enable(dev);
1206
1207 ret = nwl_dsi_select_input(dsi);
1208 if (ret < 0) {
1209 mipi_dsi_host_unregister(&dsi->dsi_host);
1210 return ret;
1211 }
1212
1213 drm_bridge_add(&dsi->bridge);
1214 return 0;
1215 }
1216
nwl_dsi_remove(struct platform_device * pdev)1217 static int nwl_dsi_remove(struct platform_device *pdev)
1218 {
1219 struct nwl_dsi *dsi = platform_get_drvdata(pdev);
1220
1221 nwl_dsi_deselect_input(dsi);
1222 mipi_dsi_host_unregister(&dsi->dsi_host);
1223 drm_bridge_remove(&dsi->bridge);
1224 pm_runtime_disable(&pdev->dev);
1225 return 0;
1226 }
1227
1228 static struct platform_driver nwl_dsi_driver = {
1229 .probe = nwl_dsi_probe,
1230 .remove = nwl_dsi_remove,
1231 .driver = {
1232 .of_match_table = nwl_dsi_dt_ids,
1233 .name = DRV_NAME,
1234 },
1235 };
1236
1237 module_platform_driver(nwl_dsi_driver);
1238
1239 MODULE_AUTHOR("NXP Semiconductor");
1240 MODULE_AUTHOR("Purism SPC");
1241 MODULE_DESCRIPTION("Northwest Logic MIPI-DSI driver");
1242 MODULE_LICENSE("GPL"); /* GPLv2 or later */
1243