1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 3 */ 4 5 #ifndef _DPU_HW_INTERRUPTS_H 6 #define _DPU_HW_INTERRUPTS_H 7 8 #include <linux/types.h> 9 10 #include "dpu_hwio.h" 11 #include "dpu_hw_catalog.h" 12 #include "dpu_hw_util.h" 13 #include "dpu_hw_mdss.h" 14 15 /* When making changes be sure to sync with dpu_intr_set */ 16 enum dpu_hw_intr_reg { 17 MDP_SSPP_TOP0_INTR, 18 MDP_SSPP_TOP0_INTR2, 19 MDP_SSPP_TOP0_HIST_INTR, 20 MDP_INTF0_INTR, 21 MDP_INTF1_INTR, 22 MDP_INTF2_INTR, 23 MDP_INTF3_INTR, 24 MDP_INTF4_INTR, 25 MDP_AD4_0_INTR, 26 MDP_AD4_1_INTR, 27 MDP_INTF0_7xxx_INTR, 28 MDP_INTF1_7xxx_INTR, 29 MDP_INTF5_7xxx_INTR, 30 MDP_INTR_MAX, 31 }; 32 33 #define DPU_IRQ_IDX(reg_idx, offset) (reg_idx * 32 + offset) 34 35 /** 36 * struct dpu_hw_intr: hw interrupts handling data structure 37 * @hw: virtual address mapping 38 * @ops: function pointer mapping for IRQ handling 39 * @cache_irq_mask: array of IRQ enable masks reg storage created during init 40 * @save_irq_status: array of IRQ status reg storage created during init 41 * @total_irqs: total number of irq_idx mapped in the hw_interrupts 42 * @irq_lock: spinlock for accessing IRQ resources 43 * @irq_cb_tbl: array of IRQ callbacks lists 44 * @irq_counts: array of IRQ counts 45 */ 46 struct dpu_hw_intr { 47 struct dpu_hw_blk_reg_map hw; 48 u32 *cache_irq_mask; 49 u32 *save_irq_status; 50 u32 total_irqs; 51 spinlock_t irq_lock; 52 unsigned long irq_mask; 53 54 struct list_head *irq_cb_tbl; 55 atomic_t *irq_counts; 56 }; 57 58 /** 59 * dpu_hw_intr_init(): Initializes the interrupts hw object 60 * @addr: mapped register io address of MDP 61 * @m : pointer to mdss catalog data 62 */ 63 struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr, 64 struct dpu_mdss_cfg *m); 65 66 /** 67 * dpu_hw_intr_destroy(): Cleanup interrutps hw object 68 * @intr: pointer to interrupts hw object 69 */ 70 void dpu_hw_intr_destroy(struct dpu_hw_intr *intr); 71 #endif 72