1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4  */
5 
6 #ifndef __DSI_PHY_H__
7 #define __DSI_PHY_H__
8 
9 #include <linux/clk-provider.h>
10 #include <linux/delay.h>
11 #include <linux/regulator/consumer.h>
12 
13 #include "dsi.h"
14 
15 #define dsi_phy_read(offset) msm_readl((offset))
16 #define dsi_phy_write(offset, data) msm_writel((data), (offset))
17 #define dsi_phy_write_udelay(offset, data, delay_us) { msm_writel((data), (offset)); udelay(delay_us); }
18 #define dsi_phy_write_ndelay(offset, data, delay_ns) { msm_writel((data), (offset)); ndelay(delay_ns); }
19 
20 struct msm_dsi_phy_ops {
21 	int (*pll_init)(struct msm_dsi_phy *phy);
22 	int (*enable)(struct msm_dsi_phy *phy,
23 			struct msm_dsi_phy_clk_request *clk_req);
24 	void (*disable)(struct msm_dsi_phy *phy);
25 	void (*save_pll_state)(struct msm_dsi_phy *phy);
26 	int (*restore_pll_state)(struct msm_dsi_phy *phy);
27 	bool (*set_continuous_clock)(struct msm_dsi_phy *phy, bool enable);
28 };
29 
30 struct msm_dsi_phy_cfg {
31 	struct dsi_reg_config reg_cfg;
32 	struct msm_dsi_phy_ops ops;
33 
34 	unsigned long	min_pll_rate;
35 	unsigned long	max_pll_rate;
36 
37 	const resource_size_t io_start[DSI_MAX];
38 	const int num_dsi_phy;
39 	const int quirks;
40 	bool has_phy_regulator;
41 	bool has_phy_lane;
42 };
43 
44 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs;
45 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs;
46 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs;
47 extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
48 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
49 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
50 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs;
51 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs;
52 extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs;
53 extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
54 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs;
55 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;
56 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
57 
58 struct msm_dsi_dphy_timing {
59 	u32 clk_zero;
60 	u32 clk_trail;
61 	u32 clk_prepare;
62 	u32 hs_exit;
63 	u32 hs_zero;
64 	u32 hs_prepare;
65 	u32 hs_trail;
66 	u32 hs_rqst;
67 	u32 ta_go;
68 	u32 ta_sure;
69 	u32 ta_get;
70 
71 	struct msm_dsi_phy_shared_timings shared_timings;
72 
73 	/* For PHY v2 only */
74 	u32 hs_rqst_ckln;
75 	u32 hs_prep_dly;
76 	u32 hs_prep_dly_ckln;
77 	u8 hs_halfbyte_en;
78 	u8 hs_halfbyte_en_ckln;
79 };
80 
81 #define DSI_BYTE_PLL_CLK		0
82 #define DSI_PIXEL_PLL_CLK		1
83 #define NUM_PROVIDED_CLKS		2
84 
85 struct msm_dsi_phy {
86 	struct platform_device *pdev;
87 	void __iomem *base;
88 	void __iomem *pll_base;
89 	void __iomem *reg_base;
90 	void __iomem *lane_base;
91 	phys_addr_t base_size;
92 	phys_addr_t pll_size;
93 	phys_addr_t reg_size;
94 	phys_addr_t lane_size;
95 	int id;
96 
97 	struct clk *ahb_clk;
98 	struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
99 
100 	struct msm_dsi_dphy_timing timing;
101 	const struct msm_dsi_phy_cfg *cfg;
102 
103 	enum msm_dsi_phy_usecase usecase;
104 	bool regulator_ldo_mode;
105 	bool cphy_mode;
106 
107 	struct clk_hw *vco_hw;
108 	bool pll_on;
109 
110 	struct clk_hw_onecell_data *provided_clocks;
111 
112 	bool state_saved;
113 };
114 
115 /*
116  * PHY internal functions
117  */
118 int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
119 			     struct msm_dsi_phy_clk_request *clk_req);
120 int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing,
121 				struct msm_dsi_phy_clk_request *clk_req);
122 int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
123 				struct msm_dsi_phy_clk_request *clk_req);
124 int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
125 				struct msm_dsi_phy_clk_request *clk_req);
126 int msm_dsi_cphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
127 				struct msm_dsi_phy_clk_request *clk_req);
128 
129 #endif /* __DSI_PHY_H__ */
130