1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Murata SCA3300 3-axis industrial accelerometer
4  *
5  * Copyright (c) 2021 Vaisala Oyj. All rights reserved.
6  */
7 
8 #include <linux/bitops.h>
9 #include <linux/crc8.h>
10 #include <linux/delay.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/spi/spi.h>
14 
15 #include <asm/unaligned.h>
16 
17 #include <linux/iio/buffer.h>
18 #include <linux/iio/iio.h>
19 #include <linux/iio/sysfs.h>
20 #include <linux/iio/trigger_consumer.h>
21 #include <linux/iio/triggered_buffer.h>
22 
23 #define SCA3300_ALIAS "sca3300"
24 
25 #define SCA3300_CRC8_POLYNOMIAL 0x1d
26 
27 /* Device mode register */
28 #define SCA3300_REG_MODE	0xd
29 #define SCA3300_MODE_SW_RESET	0x20
30 
31 /* Last register in map */
32 #define SCA3300_REG_SELBANK	0x1f
33 
34 /* Device status and mask */
35 #define SCA3300_REG_STATUS	0x6
36 #define SCA3300_STATUS_MASK	GENMASK(8, 0)
37 
38 /* Device ID */
39 #define SCA3300_REG_WHOAMI	0x10
40 #define SCA3300_WHOAMI_ID	0x51
41 
42 /* Device return status and mask */
43 #define SCA3300_VALUE_RS_ERROR	0x3
44 #define SCA3300_MASK_RS_STATUS	GENMASK(1, 0)
45 
46 enum sca3300_scan_indexes {
47 	SCA3300_ACC_X = 0,
48 	SCA3300_ACC_Y,
49 	SCA3300_ACC_Z,
50 	SCA3300_TEMP,
51 	SCA3300_TIMESTAMP,
52 };
53 
54 #define SCA3300_ACCEL_CHANNEL(index, reg, axis) {			\
55 	.type = IIO_ACCEL,						\
56 	.address = reg,							\
57 	.modified = 1,							\
58 	.channel2 = IIO_MOD_##axis,					\
59 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),			\
60 	.info_mask_shared_by_type =					\
61 	BIT(IIO_CHAN_INFO_SCALE) |					\
62 	BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),		\
63 	.info_mask_shared_by_type_available =				\
64 	BIT(IIO_CHAN_INFO_SCALE) |					\
65 	BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),		\
66 	.scan_index = index,						\
67 	.scan_type = {							\
68 		.sign = 's',						\
69 		.realbits = 16,						\
70 		.storagebits = 16,					\
71 		.endianness = IIO_CPU,					\
72 	},								\
73 }
74 
75 static const struct iio_chan_spec sca3300_channels[] = {
76 	SCA3300_ACCEL_CHANNEL(SCA3300_ACC_X, 0x1, X),
77 	SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Y, 0x2, Y),
78 	SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Z, 0x3, Z),
79 	{
80 		.type = IIO_TEMP,
81 		.address = 0x5,
82 		.scan_index = SCA3300_TEMP,
83 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
84 		.scan_type = {
85 			.sign = 's',
86 			.realbits = 16,
87 			.storagebits = 16,
88 			.endianness = IIO_CPU,
89 		},
90 	},
91 	IIO_CHAN_SOFT_TIMESTAMP(4),
92 };
93 
94 static const int sca3300_lp_freq[] = {70, 70, 70, 10};
95 static const int sca3300_accel_scale[][2] = {{0, 370}, {0, 741}, {0, 185}, {0, 185}};
96 
97 static const unsigned long sca3300_scan_masks[] = {
98 	BIT(SCA3300_ACC_X) | BIT(SCA3300_ACC_Y) | BIT(SCA3300_ACC_Z) |
99 	BIT(SCA3300_TEMP),
100 	0
101 };
102 
103 /**
104  * struct sca3300_data - device data
105  * @spi: SPI device structure
106  * @lock: Data buffer lock
107  * @scan: Triggered buffer. Four channel 16-bit data + 64-bit timestamp
108  * @txbuf: Transmit buffer
109  * @rxbuf: Receive buffer
110  */
111 struct sca3300_data {
112 	struct spi_device *spi;
113 	struct mutex lock;
114 	struct {
115 		s16 channels[4];
116 		s64 ts __aligned(sizeof(s64));
117 	} scan;
118 	u8 txbuf[4] ____cacheline_aligned;
119 	u8 rxbuf[4];
120 };
121 
122 DECLARE_CRC8_TABLE(sca3300_crc_table);
123 
sca3300_transfer(struct sca3300_data * sca_data,int * val)124 static int sca3300_transfer(struct sca3300_data *sca_data, int *val)
125 {
126 	/* Consecutive requests min. 10 us delay (Datasheet section 5.1.2) */
127 	struct spi_delay delay = { .value = 10, .unit = SPI_DELAY_UNIT_USECS };
128 	int32_t ret;
129 	int rs;
130 	u8 crc;
131 	struct spi_transfer xfers[2] = {
132 		{
133 			.tx_buf = sca_data->txbuf,
134 			.len = ARRAY_SIZE(sca_data->txbuf),
135 			.delay = delay,
136 			.cs_change = 1,
137 		},
138 		{
139 			.rx_buf = sca_data->rxbuf,
140 			.len = ARRAY_SIZE(sca_data->rxbuf),
141 			.delay = delay,
142 		}
143 	};
144 
145 	/* inverted crc value as described in device data sheet */
146 	crc = ~crc8(sca3300_crc_table, &sca_data->txbuf[0], 3, CRC8_INIT_VALUE);
147 	sca_data->txbuf[3] = crc;
148 
149 	ret = spi_sync_transfer(sca_data->spi, xfers, ARRAY_SIZE(xfers));
150 	if (ret) {
151 		dev_err(&sca_data->spi->dev,
152 			"transfer error, error: %d\n", ret);
153 		return -EIO;
154 	}
155 
156 	crc = ~crc8(sca3300_crc_table, &sca_data->rxbuf[0], 3, CRC8_INIT_VALUE);
157 	if (sca_data->rxbuf[3] != crc) {
158 		dev_err(&sca_data->spi->dev, "CRC checksum mismatch");
159 		return -EIO;
160 	}
161 
162 	/* get return status */
163 	rs = sca_data->rxbuf[0] & SCA3300_MASK_RS_STATUS;
164 	if (rs == SCA3300_VALUE_RS_ERROR)
165 		ret = -EINVAL;
166 
167 	*val = sign_extend32(get_unaligned_be16(&sca_data->rxbuf[1]), 15);
168 
169 	return ret;
170 }
171 
sca3300_error_handler(struct sca3300_data * sca_data)172 static int sca3300_error_handler(struct sca3300_data *sca_data)
173 {
174 	int ret;
175 	int val;
176 
177 	mutex_lock(&sca_data->lock);
178 	sca_data->txbuf[0] = SCA3300_REG_STATUS << 2;
179 	ret = sca3300_transfer(sca_data, &val);
180 	mutex_unlock(&sca_data->lock);
181 	/*
182 	 * Return status error is cleared after reading status register once,
183 	 * expect EINVAL here.
184 	 */
185 	if (ret != -EINVAL) {
186 		dev_err(&sca_data->spi->dev,
187 			"error reading device status: %d\n", ret);
188 		return ret;
189 	}
190 
191 	dev_err(&sca_data->spi->dev, "device status: 0x%lx\n",
192 		val & SCA3300_STATUS_MASK);
193 
194 	return 0;
195 }
196 
sca3300_read_reg(struct sca3300_data * sca_data,u8 reg,int * val)197 static int sca3300_read_reg(struct sca3300_data *sca_data, u8 reg, int *val)
198 {
199 	int ret;
200 
201 	mutex_lock(&sca_data->lock);
202 	sca_data->txbuf[0] = reg << 2;
203 	ret = sca3300_transfer(sca_data, val);
204 	mutex_unlock(&sca_data->lock);
205 	if (ret != -EINVAL)
206 		return ret;
207 
208 	return sca3300_error_handler(sca_data);
209 }
210 
sca3300_write_reg(struct sca3300_data * sca_data,u8 reg,int val)211 static int sca3300_write_reg(struct sca3300_data *sca_data, u8 reg, int val)
212 {
213 	int reg_val = 0;
214 	int ret;
215 
216 	mutex_lock(&sca_data->lock);
217 	/* BIT(7) for write operation */
218 	sca_data->txbuf[0] = BIT(7) | (reg << 2);
219 	put_unaligned_be16(val, &sca_data->txbuf[1]);
220 	ret = sca3300_transfer(sca_data, &reg_val);
221 	mutex_unlock(&sca_data->lock);
222 	if (ret != -EINVAL)
223 		return ret;
224 
225 	return sca3300_error_handler(sca_data);
226 }
227 
sca3300_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)228 static int sca3300_write_raw(struct iio_dev *indio_dev,
229 			     struct iio_chan_spec const *chan,
230 			     int val, int val2, long mask)
231 {
232 	struct sca3300_data *data = iio_priv(indio_dev);
233 	int reg_val;
234 	int ret;
235 	int i;
236 
237 	switch (mask) {
238 	case IIO_CHAN_INFO_SCALE:
239 		if (val)
240 			return -EINVAL;
241 
242 		for (i = 0; i < ARRAY_SIZE(sca3300_accel_scale); i++) {
243 			if (val2 == sca3300_accel_scale[i][1])
244 				return sca3300_write_reg(data, SCA3300_REG_MODE, i);
245 		}
246 		return -EINVAL;
247 
248 	case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
249 		ret = sca3300_read_reg(data, SCA3300_REG_MODE, &reg_val);
250 		if (ret)
251 			return ret;
252 		/* freq. change is possible only for mode 3 and 4 */
253 		if (reg_val == 2 && val == sca3300_lp_freq[3])
254 			return sca3300_write_reg(data, SCA3300_REG_MODE, 3);
255 		if (reg_val == 3 && val == sca3300_lp_freq[2])
256 			return sca3300_write_reg(data, SCA3300_REG_MODE, 2);
257 		return -EINVAL;
258 	default:
259 		return -EINVAL;
260 	}
261 }
262 
sca3300_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)263 static int sca3300_read_raw(struct iio_dev *indio_dev,
264 			    struct iio_chan_spec const *chan,
265 			    int *val, int *val2, long mask)
266 {
267 	struct sca3300_data *data = iio_priv(indio_dev);
268 	int ret;
269 	int reg_val;
270 
271 	switch (mask) {
272 	case IIO_CHAN_INFO_RAW:
273 		ret = sca3300_read_reg(data, chan->address, val);
274 		if (ret)
275 			return ret;
276 		return IIO_VAL_INT;
277 	case IIO_CHAN_INFO_SCALE:
278 		ret = sca3300_read_reg(data, SCA3300_REG_MODE, &reg_val);
279 		if (ret)
280 			return ret;
281 		*val = 0;
282 		*val2 = sca3300_accel_scale[reg_val][1];
283 		return IIO_VAL_INT_PLUS_MICRO;
284 	case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
285 		ret = sca3300_read_reg(data, SCA3300_REG_MODE, &reg_val);
286 		if (ret)
287 			return ret;
288 		*val = sca3300_lp_freq[reg_val];
289 		return IIO_VAL_INT;
290 	default:
291 		return -EINVAL;
292 	}
293 }
294 
sca3300_trigger_handler(int irq,void * p)295 static irqreturn_t sca3300_trigger_handler(int irq, void *p)
296 {
297 	struct iio_poll_func *pf = p;
298 	struct iio_dev *indio_dev = pf->indio_dev;
299 	struct sca3300_data *data = iio_priv(indio_dev);
300 	int bit, ret, val, i = 0;
301 
302 	for_each_set_bit(bit, indio_dev->active_scan_mask,
303 			 indio_dev->masklength) {
304 		ret = sca3300_read_reg(data, sca3300_channels[bit].address,
305 				       &val);
306 		if (ret) {
307 			dev_err_ratelimited(&data->spi->dev,
308 				"failed to read register, error: %d\n", ret);
309 			/* handled, but bailing out due to errors */
310 			goto out;
311 		}
312 		data->scan.channels[i++] = val;
313 	}
314 
315 	iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
316 					   iio_get_time_ns(indio_dev));
317 out:
318 	iio_trigger_notify_done(indio_dev->trig);
319 
320 	return IRQ_HANDLED;
321 }
322 
323 /*
324  * sca3300_init - Device init sequence. See datasheet rev 2 section
325  * 4.2 Start-Up Sequence for details.
326  */
sca3300_init(struct sca3300_data * sca_data,struct iio_dev * indio_dev)327 static int sca3300_init(struct sca3300_data *sca_data,
328 			struct iio_dev *indio_dev)
329 {
330 	int value = 0;
331 	int ret;
332 
333 	ret = sca3300_write_reg(sca_data, SCA3300_REG_MODE,
334 				SCA3300_MODE_SW_RESET);
335 	if (ret)
336 		return ret;
337 
338 	/*
339 	 * Wait 1ms after SW-reset command.
340 	 * Wait 15ms for settling of signal paths.
341 	 */
342 	usleep_range(16e3, 50e3);
343 
344 	ret = sca3300_read_reg(sca_data, SCA3300_REG_WHOAMI, &value);
345 	if (ret)
346 		return ret;
347 
348 	if (value != SCA3300_WHOAMI_ID) {
349 		dev_err(&sca_data->spi->dev,
350 			"device id not expected value, %d != %u\n",
351 			value, SCA3300_WHOAMI_ID);
352 		return -ENODEV;
353 	}
354 	return 0;
355 }
356 
sca3300_debugfs_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)357 static int sca3300_debugfs_reg_access(struct iio_dev *indio_dev,
358 				      unsigned int reg, unsigned int writeval,
359 				      unsigned int *readval)
360 {
361 	struct sca3300_data *data = iio_priv(indio_dev);
362 	int value;
363 	int ret;
364 
365 	if (reg > SCA3300_REG_SELBANK)
366 		return -EINVAL;
367 
368 	if (!readval)
369 		return sca3300_write_reg(data, reg, writeval);
370 
371 	ret = sca3300_read_reg(data, reg, &value);
372 	if (ret)
373 		return ret;
374 
375 	*readval = value;
376 
377 	return 0;
378 }
379 
sca3300_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)380 static int sca3300_read_avail(struct iio_dev *indio_dev,
381 			      struct iio_chan_spec const *chan,
382 			      const int **vals, int *type, int *length,
383 			      long mask)
384 {
385 	switch (mask) {
386 	case IIO_CHAN_INFO_SCALE:
387 		*vals = (const int *)sca3300_accel_scale;
388 		*length = ARRAY_SIZE(sca3300_accel_scale) * 2 - 2;
389 		*type = IIO_VAL_INT_PLUS_MICRO;
390 		return IIO_AVAIL_LIST;
391 	case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
392 		*vals = &sca3300_lp_freq[2];
393 		*length = 2;
394 		*type = IIO_VAL_INT;
395 		return IIO_AVAIL_LIST;
396 	default:
397 		return -EINVAL;
398 	}
399 }
400 
401 static const struct iio_info sca3300_info = {
402 	.read_raw = sca3300_read_raw,
403 	.write_raw = sca3300_write_raw,
404 	.debugfs_reg_access = &sca3300_debugfs_reg_access,
405 	.read_avail = sca3300_read_avail,
406 };
407 
sca3300_probe(struct spi_device * spi)408 static int sca3300_probe(struct spi_device *spi)
409 {
410 	struct sca3300_data *sca_data;
411 	struct iio_dev *indio_dev;
412 	int ret;
413 
414 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*sca_data));
415 	if (!indio_dev)
416 		return -ENOMEM;
417 
418 	sca_data = iio_priv(indio_dev);
419 	mutex_init(&sca_data->lock);
420 	sca_data->spi = spi;
421 
422 	crc8_populate_msb(sca3300_crc_table, SCA3300_CRC8_POLYNOMIAL);
423 
424 	indio_dev->info = &sca3300_info;
425 	indio_dev->name = SCA3300_ALIAS;
426 	indio_dev->modes = INDIO_DIRECT_MODE;
427 	indio_dev->channels = sca3300_channels;
428 	indio_dev->num_channels = ARRAY_SIZE(sca3300_channels);
429 	indio_dev->available_scan_masks = sca3300_scan_masks;
430 
431 	ret = sca3300_init(sca_data, indio_dev);
432 	if (ret) {
433 		dev_err(&spi->dev, "failed to init device, error: %d\n", ret);
434 		return ret;
435 	}
436 
437 	ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
438 					      iio_pollfunc_store_time,
439 					      sca3300_trigger_handler, NULL);
440 	if (ret) {
441 		dev_err(&spi->dev,
442 			"iio triggered buffer setup failed, error: %d\n", ret);
443 		return ret;
444 	}
445 
446 	ret = devm_iio_device_register(&spi->dev, indio_dev);
447 	if (ret) {
448 		dev_err(&spi->dev, "iio device register failed, error: %d\n",
449 			ret);
450 	}
451 
452 	return ret;
453 }
454 
455 static const struct of_device_id sca3300_dt_ids[] = {
456 	{ .compatible = "murata,sca3300"},
457 	{}
458 };
459 MODULE_DEVICE_TABLE(of, sca3300_dt_ids);
460 
461 static struct spi_driver sca3300_driver = {
462 	.driver = {
463 		.name		= SCA3300_ALIAS,
464 		.of_match_table = sca3300_dt_ids,
465 	},
466 	.probe	= sca3300_probe,
467 };
468 module_spi_driver(sca3300_driver);
469 
470 MODULE_AUTHOR("Tomas Melin <tomas.melin@vaisala.com>");
471 MODULE_DESCRIPTION("Murata SCA3300 SPI Accelerometer");
472 MODULE_LICENSE("GPL v2");
473