1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * AD7887 SPI ADC driver
4 *
5 * Copyright 2010-2011 Analog Devices Inc.
6 */
7
8 #include <linux/device.h>
9 #include <linux/kernel.h>
10 #include <linux/slab.h>
11 #include <linux/sysfs.h>
12 #include <linux/spi/spi.h>
13 #include <linux/regulator/consumer.h>
14 #include <linux/err.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/bitops.h>
18
19 #include <linux/iio/iio.h>
20 #include <linux/iio/sysfs.h>
21 #include <linux/iio/buffer.h>
22
23 #include <linux/iio/trigger_consumer.h>
24 #include <linux/iio/triggered_buffer.h>
25
26 #include <linux/platform_data/ad7887.h>
27
28 #define AD7887_REF_DIS BIT(5) /* on-chip reference disable */
29 #define AD7887_DUAL BIT(4) /* dual-channel mode */
30 #define AD7887_CH_AIN1 BIT(3) /* convert on channel 1, DUAL=1 */
31 #define AD7887_CH_AIN0 0 /* convert on channel 0, DUAL=0,1 */
32 #define AD7887_PM_MODE1 0 /* CS based shutdown */
33 #define AD7887_PM_MODE2 1 /* full on */
34 #define AD7887_PM_MODE3 2 /* auto shutdown after conversion */
35 #define AD7887_PM_MODE4 3 /* standby mode */
36
37 enum ad7887_channels {
38 AD7887_CH0,
39 AD7887_CH0_CH1,
40 AD7887_CH1,
41 };
42
43 /**
44 * struct ad7887_chip_info - chip specifc information
45 * @int_vref_mv: the internal reference voltage
46 * @channels: channels specification
47 * @num_channels: number of channels
48 * @dual_channels: channels specification in dual mode
49 * @num_dual_channels: number of channels in dual mode
50 */
51 struct ad7887_chip_info {
52 u16 int_vref_mv;
53 const struct iio_chan_spec *channels;
54 unsigned int num_channels;
55 const struct iio_chan_spec *dual_channels;
56 unsigned int num_dual_channels;
57 };
58
59 struct ad7887_state {
60 struct spi_device *spi;
61 const struct ad7887_chip_info *chip_info;
62 struct regulator *reg;
63 struct spi_transfer xfer[4];
64 struct spi_message msg[3];
65 struct spi_message *ring_msg;
66 unsigned char tx_cmd_buf[4];
67
68 /*
69 * DMA (thus cache coherency maintenance) requires the
70 * transfer buffers to live in their own cache lines.
71 * Buffer needs to be large enough to hold two 16 bit samples and a
72 * 64 bit aligned 64 bit timestamp.
73 */
74 unsigned char data[ALIGN(4, sizeof(s64)) + sizeof(s64)]
75 ____cacheline_aligned;
76 };
77
78 enum ad7887_supported_device_ids {
79 ID_AD7887
80 };
81
ad7887_ring_preenable(struct iio_dev * indio_dev)82 static int ad7887_ring_preenable(struct iio_dev *indio_dev)
83 {
84 struct ad7887_state *st = iio_priv(indio_dev);
85
86 /* We know this is a single long so can 'cheat' */
87 switch (*indio_dev->active_scan_mask) {
88 case (1 << 0):
89 st->ring_msg = &st->msg[AD7887_CH0];
90 break;
91 case (1 << 1):
92 st->ring_msg = &st->msg[AD7887_CH1];
93 /* Dummy read: push CH1 setting down to hardware */
94 spi_sync(st->spi, st->ring_msg);
95 break;
96 case ((1 << 1) | (1 << 0)):
97 st->ring_msg = &st->msg[AD7887_CH0_CH1];
98 break;
99 }
100
101 return 0;
102 }
103
ad7887_ring_postdisable(struct iio_dev * indio_dev)104 static int ad7887_ring_postdisable(struct iio_dev *indio_dev)
105 {
106 struct ad7887_state *st = iio_priv(indio_dev);
107
108 /* dummy read: restore default CH0 settin */
109 return spi_sync(st->spi, &st->msg[AD7887_CH0]);
110 }
111
ad7887_trigger_handler(int irq,void * p)112 static irqreturn_t ad7887_trigger_handler(int irq, void *p)
113 {
114 struct iio_poll_func *pf = p;
115 struct iio_dev *indio_dev = pf->indio_dev;
116 struct ad7887_state *st = iio_priv(indio_dev);
117 int b_sent;
118
119 b_sent = spi_sync(st->spi, st->ring_msg);
120 if (b_sent)
121 goto done;
122
123 iio_push_to_buffers_with_timestamp(indio_dev, st->data,
124 iio_get_time_ns(indio_dev));
125 done:
126 iio_trigger_notify_done(indio_dev->trig);
127
128 return IRQ_HANDLED;
129 }
130
131 static const struct iio_buffer_setup_ops ad7887_ring_setup_ops = {
132 .preenable = &ad7887_ring_preenable,
133 .postdisable = &ad7887_ring_postdisable,
134 };
135
ad7887_scan_direct(struct ad7887_state * st,unsigned ch)136 static int ad7887_scan_direct(struct ad7887_state *st, unsigned ch)
137 {
138 int ret = spi_sync(st->spi, &st->msg[ch]);
139 if (ret)
140 return ret;
141
142 return (st->data[(ch * 2)] << 8) | st->data[(ch * 2) + 1];
143 }
144
ad7887_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)145 static int ad7887_read_raw(struct iio_dev *indio_dev,
146 struct iio_chan_spec const *chan,
147 int *val,
148 int *val2,
149 long m)
150 {
151 int ret;
152 struct ad7887_state *st = iio_priv(indio_dev);
153
154 switch (m) {
155 case IIO_CHAN_INFO_RAW:
156 ret = iio_device_claim_direct_mode(indio_dev);
157 if (ret)
158 return ret;
159 ret = ad7887_scan_direct(st, chan->address);
160 iio_device_release_direct_mode(indio_dev);
161
162 if (ret < 0)
163 return ret;
164 *val = ret >> chan->scan_type.shift;
165 *val &= GENMASK(chan->scan_type.realbits - 1, 0);
166 return IIO_VAL_INT;
167 case IIO_CHAN_INFO_SCALE:
168 if (st->reg) {
169 *val = regulator_get_voltage(st->reg);
170 if (*val < 0)
171 return *val;
172 *val /= 1000;
173 } else {
174 *val = st->chip_info->int_vref_mv;
175 }
176
177 *val2 = chan->scan_type.realbits;
178
179 return IIO_VAL_FRACTIONAL_LOG2;
180 }
181 return -EINVAL;
182 }
183
184 #define AD7887_CHANNEL(x) { \
185 .type = IIO_VOLTAGE, \
186 .indexed = 1, \
187 .channel = (x), \
188 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
189 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
190 .address = (x), \
191 .scan_index = (x), \
192 .scan_type = { \
193 .sign = 'u', \
194 .realbits = 12, \
195 .storagebits = 16, \
196 .shift = 0, \
197 .endianness = IIO_BE, \
198 }, \
199 }
200
201 static const struct iio_chan_spec ad7887_channels[] = {
202 AD7887_CHANNEL(0),
203 IIO_CHAN_SOFT_TIMESTAMP(1),
204 };
205
206 static const struct iio_chan_spec ad7887_dual_channels[] = {
207 AD7887_CHANNEL(0),
208 AD7887_CHANNEL(1),
209 IIO_CHAN_SOFT_TIMESTAMP(2),
210 };
211
212 static const struct ad7887_chip_info ad7887_chip_info_tbl[] = {
213 /*
214 * More devices added in future
215 */
216 [ID_AD7887] = {
217 .channels = ad7887_channels,
218 .num_channels = ARRAY_SIZE(ad7887_channels),
219 .dual_channels = ad7887_dual_channels,
220 .num_dual_channels = ARRAY_SIZE(ad7887_dual_channels),
221 .int_vref_mv = 2500,
222 },
223 };
224
225 static const struct iio_info ad7887_info = {
226 .read_raw = &ad7887_read_raw,
227 };
228
ad7887_reg_disable(void * data)229 static void ad7887_reg_disable(void *data)
230 {
231 struct regulator *reg = data;
232
233 regulator_disable(reg);
234 }
235
ad7887_probe(struct spi_device * spi)236 static int ad7887_probe(struct spi_device *spi)
237 {
238 struct ad7887_platform_data *pdata = spi->dev.platform_data;
239 struct ad7887_state *st;
240 struct iio_dev *indio_dev;
241 uint8_t mode;
242 int ret;
243
244 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
245 if (indio_dev == NULL)
246 return -ENOMEM;
247
248 st = iio_priv(indio_dev);
249
250 st->reg = devm_regulator_get_optional(&spi->dev, "vref");
251 if (IS_ERR(st->reg)) {
252 if (PTR_ERR(st->reg) != -ENODEV)
253 return PTR_ERR(st->reg);
254
255 st->reg = NULL;
256 }
257
258 if (st->reg) {
259 ret = regulator_enable(st->reg);
260 if (ret)
261 return ret;
262
263 ret = devm_add_action_or_reset(&spi->dev, ad7887_reg_disable, st->reg);
264 if (ret)
265 return ret;
266 }
267
268 st->chip_info =
269 &ad7887_chip_info_tbl[spi_get_device_id(spi)->driver_data];
270
271 st->spi = spi;
272
273 indio_dev->name = spi_get_device_id(spi)->name;
274 indio_dev->info = &ad7887_info;
275 indio_dev->modes = INDIO_DIRECT_MODE;
276
277 /* Setup default message */
278
279 mode = AD7887_PM_MODE4;
280 if (!st->reg)
281 mode |= AD7887_REF_DIS;
282 if (pdata && pdata->en_dual)
283 mode |= AD7887_DUAL;
284
285 st->tx_cmd_buf[0] = AD7887_CH_AIN0 | mode;
286
287 st->xfer[0].rx_buf = &st->data[0];
288 st->xfer[0].tx_buf = &st->tx_cmd_buf[0];
289 st->xfer[0].len = 2;
290
291 spi_message_init(&st->msg[AD7887_CH0]);
292 spi_message_add_tail(&st->xfer[0], &st->msg[AD7887_CH0]);
293
294 if (pdata && pdata->en_dual) {
295 st->tx_cmd_buf[2] = AD7887_CH_AIN1 | mode;
296
297 st->xfer[1].rx_buf = &st->data[0];
298 st->xfer[1].tx_buf = &st->tx_cmd_buf[2];
299 st->xfer[1].len = 2;
300
301 st->xfer[2].rx_buf = &st->data[2];
302 st->xfer[2].tx_buf = &st->tx_cmd_buf[0];
303 st->xfer[2].len = 2;
304
305 spi_message_init(&st->msg[AD7887_CH0_CH1]);
306 spi_message_add_tail(&st->xfer[1], &st->msg[AD7887_CH0_CH1]);
307 spi_message_add_tail(&st->xfer[2], &st->msg[AD7887_CH0_CH1]);
308
309 st->xfer[3].rx_buf = &st->data[2];
310 st->xfer[3].tx_buf = &st->tx_cmd_buf[2];
311 st->xfer[3].len = 2;
312
313 spi_message_init(&st->msg[AD7887_CH1]);
314 spi_message_add_tail(&st->xfer[3], &st->msg[AD7887_CH1]);
315
316 indio_dev->channels = st->chip_info->dual_channels;
317 indio_dev->num_channels = st->chip_info->num_dual_channels;
318 } else {
319 indio_dev->channels = st->chip_info->channels;
320 indio_dev->num_channels = st->chip_info->num_channels;
321 }
322
323 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
324 &iio_pollfunc_store_time,
325 &ad7887_trigger_handler, &ad7887_ring_setup_ops);
326 if (ret)
327 return ret;
328
329 return devm_iio_device_register(&spi->dev, indio_dev);
330 }
331
332 static const struct spi_device_id ad7887_id[] = {
333 {"ad7887", ID_AD7887},
334 {}
335 };
336 MODULE_DEVICE_TABLE(spi, ad7887_id);
337
338 static struct spi_driver ad7887_driver = {
339 .driver = {
340 .name = "ad7887",
341 },
342 .probe = ad7887_probe,
343 .id_table = ad7887_id,
344 };
345 module_spi_driver(ad7887_driver);
346
347 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
348 MODULE_DESCRIPTION("Analog Devices AD7887 ADC");
349 MODULE_LICENSE("GPL v2");
350