1 /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
2 /*
3  * Copyright(c) 2020 - Cornelis Networks, Inc.
4  * Copyright(c) 2015 - 2018 Intel Corporation.
5  */
6 #ifndef _HFI1_USER_SDMA_H
7 #define _HFI1_USER_SDMA_H
8 
9 #include <linux/device.h>
10 #include <linux/wait.h>
11 
12 #include "common.h"
13 #include "iowait.h"
14 #include "user_exp_rcv.h"
15 #include "mmu_rb.h"
16 
17 /* The maximum number of Data io vectors per message/request */
18 #define MAX_VECTORS_PER_REQ 8
19 /*
20  * Maximum number of packet to send from each message/request
21  * before moving to the next one.
22  */
23 #define MAX_PKTS_PER_QUEUE 16
24 
25 #define num_pages(x) (1 + ((((x) - 1) & PAGE_MASK) >> PAGE_SHIFT))
26 
27 #define req_opcode(x) \
28 	(((x) >> HFI1_SDMA_REQ_OPCODE_SHIFT) & HFI1_SDMA_REQ_OPCODE_MASK)
29 #define req_version(x) \
30 	(((x) >> HFI1_SDMA_REQ_VERSION_SHIFT) & HFI1_SDMA_REQ_OPCODE_MASK)
31 #define req_iovcnt(x) \
32 	(((x) >> HFI1_SDMA_REQ_IOVCNT_SHIFT) & HFI1_SDMA_REQ_IOVCNT_MASK)
33 
34 /* Number of BTH.PSN bits used for sequence number in expected rcvs */
35 #define BTH_SEQ_MASK 0x7ffull
36 
37 #define AHG_KDETH_INTR_SHIFT 12
38 #define AHG_KDETH_SH_SHIFT   13
39 #define AHG_KDETH_ARRAY_SIZE  9
40 
41 #define PBC2LRH(x) ((((x) & 0xfff) << 2) - 4)
42 #define LRH2PBC(x) ((((x) >> 2) + 1) & 0xfff)
43 
44 /**
45  * Build an SDMA AHG header update descriptor and save it to an array.
46  * @arr        - Array to save the descriptor to.
47  * @idx        - Index of the array at which the descriptor will be saved.
48  * @array_size - Size of the array arr.
49  * @dw         - Update index into the header in DWs.
50  * @bit        - Start bit.
51  * @width      - Field width.
52  * @value      - 16 bits of immediate data to write into the field.
53  * Returns -ERANGE if idx is invalid. If successful, returns the next index
54  * (idx + 1) of the array to be used for the next descriptor.
55  */
ahg_header_set(u32 * arr,int idx,size_t array_size,u8 dw,u8 bit,u8 width,u16 value)56 static inline int ahg_header_set(u32 *arr, int idx, size_t array_size,
57 				 u8 dw, u8 bit, u8 width, u16 value)
58 {
59 	if ((size_t)idx >= array_size)
60 		return -ERANGE;
61 	arr[idx++] = sdma_build_ahg_descriptor(value, dw, bit, width);
62 	return idx;
63 }
64 
65 /* Tx request flag bits */
66 #define TXREQ_FLAGS_REQ_ACK   BIT(0)      /* Set the ACK bit in the header */
67 #define TXREQ_FLAGS_REQ_DISABLE_SH BIT(1) /* Disable header suppression */
68 
69 enum pkt_q_sdma_state {
70 	SDMA_PKT_Q_ACTIVE,
71 	SDMA_PKT_Q_DEFERRED,
72 };
73 
74 #define SDMA_IOWAIT_TIMEOUT 1000 /* in milliseconds */
75 
76 #define SDMA_DBG(req, fmt, ...)				     \
77 	hfi1_cdbg(SDMA, "[%u:%u:%u:%u] " fmt, (req)->pq->dd->unit, \
78 		 (req)->pq->ctxt, (req)->pq->subctxt, (req)->info.comp_idx, \
79 		 ##__VA_ARGS__)
80 
81 struct hfi1_user_sdma_pkt_q {
82 	u16 ctxt;
83 	u16 subctxt;
84 	u16 n_max_reqs;
85 	atomic_t n_reqs;
86 	u16 reqidx;
87 	struct hfi1_devdata *dd;
88 	struct kmem_cache *txreq_cache;
89 	struct user_sdma_request *reqs;
90 	unsigned long *req_in_use;
91 	struct iowait busy;
92 	enum pkt_q_sdma_state state;
93 	wait_queue_head_t wait;
94 	unsigned long unpinned;
95 	struct mmu_rb_handler *handler;
96 	atomic_t n_locked;
97 };
98 
99 struct hfi1_user_sdma_comp_q {
100 	u16 nentries;
101 	struct hfi1_sdma_comp_entry *comps;
102 };
103 
104 struct sdma_mmu_node {
105 	struct mmu_rb_node rb;
106 	struct hfi1_user_sdma_pkt_q *pq;
107 	atomic_t refcount;
108 	struct page **pages;
109 	unsigned int npages;
110 };
111 
112 struct user_sdma_iovec {
113 	struct list_head list;
114 	struct iovec iov;
115 	/* number of pages in this vector */
116 	unsigned int npages;
117 	/* array of pinned pages for this vector */
118 	struct page **pages;
119 	/*
120 	 * offset into the virtual address space of the vector at
121 	 * which we last left off.
122 	 */
123 	u64 offset;
124 	struct sdma_mmu_node *node;
125 };
126 
127 /* evict operation argument */
128 struct evict_data {
129 	u32 cleared;	/* count evicted so far */
130 	u32 target;	/* target count to evict */
131 };
132 
133 struct user_sdma_request {
134 	/* This is the original header from user space */
135 	struct hfi1_pkt_header hdr;
136 
137 	/* Read mostly fields */
138 	struct hfi1_user_sdma_pkt_q *pq ____cacheline_aligned_in_smp;
139 	struct hfi1_user_sdma_comp_q *cq;
140 	/*
141 	 * Pointer to the SDMA engine for this request.
142 	 * Since different request could be on different VLs,
143 	 * each request will need it's own engine pointer.
144 	 */
145 	struct sdma_engine *sde;
146 	struct sdma_req_info info;
147 	/* TID array values copied from the tid_iov vector */
148 	u32 *tids;
149 	/* total length of the data in the request */
150 	u32 data_len;
151 	/* number of elements copied to the tids array */
152 	u16 n_tids;
153 	/*
154 	 * We copy the iovs for this request (based on
155 	 * info.iovcnt). These are only the data vectors
156 	 */
157 	u8 data_iovs;
158 	s8 ahg_idx;
159 
160 	/* Writeable fields shared with interrupt */
161 	u16 seqcomp ____cacheline_aligned_in_smp;
162 	u16 seqsubmitted;
163 
164 	/* Send side fields */
165 	struct list_head txps ____cacheline_aligned_in_smp;
166 	u16 seqnum;
167 	/*
168 	 * KDETH.OFFSET (TID) field
169 	 * The offset can cover multiple packets, depending on the
170 	 * size of the TID entry.
171 	 */
172 	u32 tidoffset;
173 	/*
174 	 * KDETH.Offset (Eager) field
175 	 * We need to remember the initial value so the headers
176 	 * can be updated properly.
177 	 */
178 	u32 koffset;
179 	u32 sent;
180 	/* TID index copied from the tid_iov vector */
181 	u16 tididx;
182 	/* progress index moving along the iovs array */
183 	u8 iov_idx;
184 	u8 has_error;
185 
186 	struct user_sdma_iovec iovs[MAX_VECTORS_PER_REQ];
187 } ____cacheline_aligned_in_smp;
188 
189 /*
190  * A single txreq could span up to 3 physical pages when the MTU
191  * is sufficiently large (> 4K). Each of the IOV pointers also
192  * needs it's own set of flags so the vector has been handled
193  * independently of each other.
194  */
195 struct user_sdma_txreq {
196 	/* Packet header for the txreq */
197 	struct hfi1_pkt_header hdr;
198 	struct sdma_txreq txreq;
199 	struct list_head list;
200 	struct user_sdma_request *req;
201 	u16 flags;
202 	u16 seqnum;
203 };
204 
205 int hfi1_user_sdma_alloc_queues(struct hfi1_ctxtdata *uctxt,
206 				struct hfi1_filedata *fd);
207 int hfi1_user_sdma_free_queues(struct hfi1_filedata *fd,
208 			       struct hfi1_ctxtdata *uctxt);
209 int hfi1_user_sdma_process_request(struct hfi1_filedata *fd,
210 				   struct iovec *iovec, unsigned long dim,
211 				   unsigned long *count);
212 
mm_from_sdma_node(struct sdma_mmu_node * node)213 static inline struct mm_struct *mm_from_sdma_node(struct sdma_mmu_node *node)
214 {
215 	return node->rb.handler->mn.mm;
216 }
217 
218 #endif /* _HFI1_USER_SDMA_H */
219