1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2018-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 #ifndef HL_BOOT_IF_H 9 #define HL_BOOT_IF_H 10 11 #define LKD_HARD_RESET_MAGIC 0xED7BD694 /* deprecated - do not use */ 12 #define HL_POWER9_HOST_MAGIC 0x1DA30009 13 14 #define BOOT_FIT_SRAM_OFFSET 0x200000 15 16 #define VERSION_MAX_LEN 128 17 18 enum cpu_boot_err { 19 CPU_BOOT_ERR_DRAM_INIT_FAIL = 0, 20 CPU_BOOT_ERR_FIT_CORRUPTED = 1, 21 CPU_BOOT_ERR_TS_INIT_FAIL = 2, 22 CPU_BOOT_ERR_DRAM_SKIPPED = 3, 23 CPU_BOOT_ERR_BMC_WAIT_SKIPPED = 4, 24 CPU_BOOT_ERR_NIC_DATA_NOT_RDY = 5, 25 CPU_BOOT_ERR_NIC_FW_FAIL = 6, 26 CPU_BOOT_ERR_SECURITY_NOT_RDY = 7, 27 CPU_BOOT_ERR_SECURITY_FAIL = 8, 28 CPU_BOOT_ERR_EFUSE_FAIL = 9, 29 CPU_BOOT_ERR_PRI_IMG_VER_FAIL = 10, 30 CPU_BOOT_ERR_SEC_IMG_VER_FAIL = 11, 31 CPU_BOOT_ERR_PLL_FAIL = 12, 32 CPU_BOOT_ERR_DEVICE_UNUSABLE_FAIL = 13, 33 CPU_BOOT_ERR_BOOT_FW_CRIT_ERR = 18, 34 CPU_BOOT_ERR_BINNING_FAIL = 19, 35 CPU_BOOT_ERR_ENABLED = 31, 36 CPU_BOOT_ERR_SCND_EN = 63, 37 CPU_BOOT_ERR_LAST = 64 /* we have 2 registers of 32 bits */ 38 }; 39 40 /* 41 * CPU error bits in BOOT_ERROR registers 42 * 43 * CPU_BOOT_ERR0_DRAM_INIT_FAIL DRAM initialization failed. 44 * DRAM is not reliable to use. 45 * 46 * CPU_BOOT_ERR0_FIT_CORRUPTED FIT data integrity verification of the 47 * image provided by the host has failed. 48 * 49 * CPU_BOOT_ERR0_TS_INIT_FAIL Thermal Sensor initialization failed. 50 * Boot continues as usual, but keep in 51 * mind this is a warning. 52 * 53 * CPU_BOOT_ERR0_DRAM_SKIPPED DRAM initialization has been skipped. 54 * Skipping DRAM initialization has been 55 * requested (e.g. strap, command, etc.) 56 * and FW skipped the DRAM initialization. 57 * Host can initialize the DRAM. 58 * 59 * CPU_BOOT_ERR0_BMC_WAIT_SKIPPED Waiting for BMC data will be skipped. 60 * Meaning the BMC data might not be 61 * available until reset. 62 * 63 * CPU_BOOT_ERR0_NIC_DATA_NOT_RDY NIC data from BMC is not ready. 64 * BMC has not provided the NIC data yet. 65 * Once provided this bit will be cleared. 66 * 67 * CPU_BOOT_ERR0_NIC_FW_FAIL NIC FW loading failed. 68 * The NIC FW loading and initialization 69 * failed. This means NICs are not usable. 70 * 71 * CPU_BOOT_ERR0_SECURITY_NOT_RDY Chip security initialization has been 72 * started, but is not ready yet - chip 73 * cannot be accessed. 74 * 75 * CPU_BOOT_ERR0_SECURITY_FAIL Security related tasks have failed. 76 * The tasks are security init (root of 77 * trust), boot authentication (chain of 78 * trust), data packets authentication. 79 * 80 * CPU_BOOT_ERR0_EFUSE_FAIL Reading from eFuse failed. 81 * The PCI device ID might be wrong. 82 * 83 * CPU_BOOT_ERR0_PRI_IMG_VER_FAIL Verification of primary image failed. 84 * It mean that ppboot checksum 85 * verification for the preboot primary 86 * image has failed to match expected 87 * checksum. Trying to program image again 88 * might solve this. 89 * 90 * CPU_BOOT_ERR0_SEC_IMG_VER_FAIL Verification of secondary image failed. 91 * It mean that ppboot checksum 92 * verification for the preboot secondary 93 * image has failed to match expected 94 * checksum. Trying to program image again 95 * might solve this. 96 * 97 * CPU_BOOT_ERR0_PLL_FAIL PLL settings failed, meaning that one 98 * of the PLLs remains in REF_CLK 99 * 100 * CPU_BOOT_ERR0_DEVICE_UNUSABLE_FAIL Device is unusable and customer support 101 * should be contacted. 102 * 103 * CPU_BOOT_ERR0_BOOT_FW_CRIT_ERR Critical error was detected during 104 * the execution of ppboot or preboot. 105 * for example: stack overflow. 106 * 107 * CPU_BOOT_ERR0_BINNING_FAIL Binning settings failed, meaning 108 * malfunctioning components might still be 109 * in use. 110 * 111 * CPU_BOOT_ERR0_ENABLED Error registers enabled. 112 * This is a main indication that the 113 * running FW populates the error 114 * registers. Meaning the error bits are 115 * not garbage, but actual error statuses. 116 */ 117 #define CPU_BOOT_ERR0_DRAM_INIT_FAIL (1 << CPU_BOOT_ERR_DRAM_INIT_FAIL) 118 #define CPU_BOOT_ERR0_FIT_CORRUPTED (1 << CPU_BOOT_ERR_FIT_CORRUPTED) 119 #define CPU_BOOT_ERR0_TS_INIT_FAIL (1 << CPU_BOOT_ERR_TS_INIT_FAIL) 120 #define CPU_BOOT_ERR0_DRAM_SKIPPED (1 << CPU_BOOT_ERR_DRAM_SKIPPED) 121 #define CPU_BOOT_ERR0_BMC_WAIT_SKIPPED (1 << CPU_BOOT_ERR_BMC_WAIT_SKIPPED) 122 #define CPU_BOOT_ERR0_NIC_DATA_NOT_RDY (1 << CPU_BOOT_ERR_NIC_DATA_NOT_RDY) 123 #define CPU_BOOT_ERR0_NIC_FW_FAIL (1 << CPU_BOOT_ERR_NIC_FW_FAIL) 124 #define CPU_BOOT_ERR0_SECURITY_NOT_RDY (1 << CPU_BOOT_ERR_SECURITY_NOT_RDY) 125 #define CPU_BOOT_ERR0_SECURITY_FAIL (1 << CPU_BOOT_ERR_SECURITY_FAIL) 126 #define CPU_BOOT_ERR0_EFUSE_FAIL (1 << CPU_BOOT_ERR_EFUSE_FAIL) 127 #define CPU_BOOT_ERR0_PRI_IMG_VER_FAIL (1 << CPU_BOOT_ERR_PRI_IMG_VER_FAIL) 128 #define CPU_BOOT_ERR0_SEC_IMG_VER_FAIL (1 << CPU_BOOT_ERR_SEC_IMG_VER_FAIL) 129 #define CPU_BOOT_ERR0_PLL_FAIL (1 << CPU_BOOT_ERR_PLL_FAIL) 130 #define CPU_BOOT_ERR0_DEVICE_UNUSABLE_FAIL (1 << CPU_BOOT_ERR_DEVICE_UNUSABLE_FAIL) 131 #define CPU_BOOT_ERR0_BOOT_FW_CRIT_ERR (1 << CPU_BOOT_ERR_BOOT_FW_CRIT_ERR) 132 #define CPU_BOOT_ERR0_BINNING_FAIL (1 << CPU_BOOT_ERR_BINNING_FAIL) 133 #define CPU_BOOT_ERR0_ENABLED (1 << CPU_BOOT_ERR_ENABLED) 134 #define CPU_BOOT_ERR1_ENABLED (1 << CPU_BOOT_ERR_ENABLED) 135 136 enum cpu_boot_dev_sts { 137 CPU_BOOT_DEV_STS_SECURITY_EN = 0, 138 CPU_BOOT_DEV_STS_DEBUG_EN = 1, 139 CPU_BOOT_DEV_STS_WATCHDOG_EN = 2, 140 CPU_BOOT_DEV_STS_DRAM_INIT_EN = 3, 141 CPU_BOOT_DEV_STS_BMC_WAIT_EN = 4, 142 CPU_BOOT_DEV_STS_E2E_CRED_EN = 5, 143 CPU_BOOT_DEV_STS_HBM_CRED_EN = 6, 144 CPU_BOOT_DEV_STS_RL_EN = 7, 145 CPU_BOOT_DEV_STS_SRAM_SCR_EN = 8, 146 CPU_BOOT_DEV_STS_DRAM_SCR_EN = 9, 147 CPU_BOOT_DEV_STS_FW_HARD_RST_EN = 10, 148 CPU_BOOT_DEV_STS_PLL_INFO_EN = 11, 149 CPU_BOOT_DEV_STS_SP_SRAM_EN = 12, 150 CPU_BOOT_DEV_STS_CLK_GATE_EN = 13, 151 CPU_BOOT_DEV_STS_HBM_ECC_EN = 14, 152 CPU_BOOT_DEV_STS_PKT_PI_ACK_EN = 15, 153 CPU_BOOT_DEV_STS_FW_LD_COM_EN = 16, 154 CPU_BOOT_DEV_STS_FW_IATU_CONF_EN = 17, 155 CPU_BOOT_DEV_STS_FW_NIC_MAC_EN = 18, 156 CPU_BOOT_DEV_STS_DYN_PLL_EN = 19, 157 CPU_BOOT_DEV_STS_GIC_PRIVILEGED_EN = 20, 158 CPU_BOOT_DEV_STS_EQ_INDEX_EN = 21, 159 CPU_BOOT_DEV_STS_MULTI_IRQ_POLL_EN = 22, 160 CPU_BOOT_DEV_STS_FW_NIC_STAT_XPCS91_EN = 23, 161 CPU_BOOT_DEV_STS_FW_NIC_STAT_EXT_EN = 24, 162 CPU_BOOT_DEV_STS_IS_IDLE_CHECK_EN = 25, 163 CPU_BOOT_DEV_STS_MAP_HWMON_EN = 26, 164 CPU_BOOT_DEV_STS_ENABLED = 31, 165 CPU_BOOT_DEV_STS_SCND_EN = 63, 166 CPU_BOOT_DEV_STS_LAST = 64 /* we have 2 registers of 32 bits */ 167 }; 168 169 /* 170 * BOOT DEVICE STATUS bits in BOOT_DEVICE_STS registers 171 * 172 * CPU_BOOT_DEV_STS0_SECURITY_EN Security is Enabled. 173 * This is an indication for security 174 * enabled in FW, which means that 175 * all conditions for security are met: 176 * device is indicated as security enabled, 177 * registers are protected, and device 178 * uses keys for image verification. 179 * Initialized in: preboot 180 * 181 * CPU_BOOT_DEV_STS0_DEBUG_EN Debug is enabled. 182 * Enabled when JTAG or DEBUG is enabled 183 * in FW. 184 * Initialized in: preboot 185 * 186 * CPU_BOOT_DEV_STS0_WATCHDOG_EN Watchdog is enabled. 187 * Watchdog is enabled in FW. 188 * Initialized in: preboot 189 * 190 * CPU_BOOT_DEV_STS0_DRAM_INIT_EN DRAM initialization is enabled. 191 * DRAM initialization has been done in FW. 192 * Initialized in: u-boot 193 * 194 * CPU_BOOT_DEV_STS0_BMC_WAIT_EN Waiting for BMC data enabled. 195 * If set, it means that during boot, 196 * FW waited for BMC data. 197 * Initialized in: u-boot 198 * 199 * CPU_BOOT_DEV_STS0_E2E_CRED_EN E2E credits initialized. 200 * FW initialized E2E credits. 201 * Initialized in: u-boot 202 * 203 * CPU_BOOT_DEV_STS0_HBM_CRED_EN HBM credits initialized. 204 * FW initialized HBM credits. 205 * Initialized in: u-boot 206 * 207 * CPU_BOOT_DEV_STS0_RL_EN Rate limiter initialized. 208 * FW initialized rate limiter. 209 * Initialized in: u-boot 210 * 211 * CPU_BOOT_DEV_STS0_SRAM_SCR_EN SRAM scrambler enabled. 212 * FW initialized SRAM scrambler. 213 * Initialized in: linux 214 * 215 * CPU_BOOT_DEV_STS0_DRAM_SCR_EN DRAM scrambler enabled. 216 * FW initialized DRAM scrambler. 217 * Initialized in: u-boot 218 * 219 * CPU_BOOT_DEV_STS0_FW_HARD_RST_EN FW hard reset procedure is enabled. 220 * FW has the hard reset procedure 221 * implemented. This means that FW will 222 * perform hard reset procedure on 223 * receiving the halt-machine event. 224 * Initialized in: preboot, u-boot, linux 225 * 226 * CPU_BOOT_DEV_STS0_PLL_INFO_EN FW retrieval of PLL info is enabled. 227 * Initialized in: linux 228 * 229 * CPU_BOOT_DEV_STS0_SP_SRAM_EN SP SRAM is initialized and available 230 * for use. 231 * Initialized in: preboot 232 * 233 * CPU_BOOT_DEV_STS0_CLK_GATE_EN Clock Gating enabled. 234 * FW initialized Clock Gating. 235 * Initialized in: preboot 236 * 237 * CPU_BOOT_DEV_STS0_HBM_ECC_EN HBM ECC handling Enabled. 238 * FW handles HBM ECC indications. 239 * Initialized in: linux 240 * 241 * CPU_BOOT_DEV_STS0_PKT_PI_ACK_EN Packets ack value used in the armcpd 242 * is set to the PI counter. 243 * Initialized in: linux 244 * 245 * CPU_BOOT_DEV_STS0_FW_LD_COM_EN Flexible FW loading communication 246 * protocol is enabled. 247 * Initialized in: preboot 248 * 249 * CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN FW iATU configuration is enabled. 250 * This bit if set, means the iATU has been 251 * configured and is ready for use. 252 * Initialized in: ppboot 253 * 254 * CPU_BOOT_DEV_STS0_FW_NIC_MAC_EN NIC MAC channels init is done by FW and 255 * any access to them is done via the FW. 256 * Initialized in: linux 257 * 258 * CPU_BOOT_DEV_STS0_DYN_PLL_EN Dynamic PLL configuration is enabled. 259 * FW sends to host a bitmap of supported 260 * PLLs. 261 * Initialized in: linux 262 * 263 * CPU_BOOT_DEV_STS0_GIC_PRIVILEGED_EN GIC access permission only from 264 * previleged entity. FW sets this status 265 * bit for host. If this bit is set then 266 * GIC can not be accessed from host. 267 * Initialized in: linux 268 * 269 * CPU_BOOT_DEV_STS0_EQ_INDEX_EN Event Queue (EQ) index is a running 270 * index for each new event sent to host. 271 * This is used as a method in host to 272 * identify that the waiting event in 273 * queue is actually a new event which 274 * was not served before. 275 * Initialized in: linux 276 * 277 * CPU_BOOT_DEV_STS0_MULTI_IRQ_POLL_EN Use multiple scratchpad interfaces to 278 * prevent IRQs overriding each other. 279 * Initialized in: linux 280 * 281 * CPU_BOOT_DEV_STS0_FW_NIC_STAT_XPCS91_EN 282 * NIC STAT and XPCS91 access is restricted 283 * and is done via FW only. 284 * Initialized in: linux 285 * 286 * CPU_BOOT_DEV_STS0_FW_NIC_STAT_EXT_EN 287 * NIC STAT get all is supported. 288 * Initialized in: linux 289 * 290 * CPU_BOOT_DEV_STS0_IS_IDLE_CHECK_EN 291 * F/W checks if the device is idle by reading defined set 292 * of registers. It returns a bitmask of all the engines, 293 * where a bit is set if the engine is not idle. 294 * Initialized in: linux 295 * 296 * CPU_BOOT_DEV_STS0_MAP_HWMON_EN 297 * If set, means f/w supports proprietary 298 * HWMON enum mapping to cpucp enums. 299 * Initialized in: linux 300 * 301 * CPU_BOOT_DEV_STS0_ENABLED Device status register enabled. 302 * This is a main indication that the 303 * running FW populates the device status 304 * register. Meaning the device status 305 * bits are not garbage, but actual 306 * statuses. 307 * Initialized in: preboot 308 * 309 */ 310 #define CPU_BOOT_DEV_STS0_SECURITY_EN (1 << CPU_BOOT_DEV_STS_SECURITY_EN) 311 #define CPU_BOOT_DEV_STS0_DEBUG_EN (1 << CPU_BOOT_DEV_STS_DEBUG_EN) 312 #define CPU_BOOT_DEV_STS0_WATCHDOG_EN (1 << CPU_BOOT_DEV_STS_WATCHDOG_EN) 313 #define CPU_BOOT_DEV_STS0_DRAM_INIT_EN (1 << CPU_BOOT_DEV_STS_DRAM_INIT_EN) 314 #define CPU_BOOT_DEV_STS0_BMC_WAIT_EN (1 << CPU_BOOT_DEV_STS_BMC_WAIT_EN) 315 #define CPU_BOOT_DEV_STS0_E2E_CRED_EN (1 << CPU_BOOT_DEV_STS_E2E_CRED_EN) 316 #define CPU_BOOT_DEV_STS0_HBM_CRED_EN (1 << CPU_BOOT_DEV_STS_HBM_CRED_EN) 317 #define CPU_BOOT_DEV_STS0_RL_EN (1 << CPU_BOOT_DEV_STS_RL_EN) 318 #define CPU_BOOT_DEV_STS0_SRAM_SCR_EN (1 << CPU_BOOT_DEV_STS_SRAM_SCR_EN) 319 #define CPU_BOOT_DEV_STS0_DRAM_SCR_EN (1 << CPU_BOOT_DEV_STS_DRAM_SCR_EN) 320 #define CPU_BOOT_DEV_STS0_FW_HARD_RST_EN (1 << CPU_BOOT_DEV_STS_FW_HARD_RST_EN) 321 #define CPU_BOOT_DEV_STS0_PLL_INFO_EN (1 << CPU_BOOT_DEV_STS_PLL_INFO_EN) 322 #define CPU_BOOT_DEV_STS0_SP_SRAM_EN (1 << CPU_BOOT_DEV_STS_SP_SRAM_EN) 323 #define CPU_BOOT_DEV_STS0_CLK_GATE_EN (1 << CPU_BOOT_DEV_STS_CLK_GATE_EN) 324 #define CPU_BOOT_DEV_STS0_HBM_ECC_EN (1 << CPU_BOOT_DEV_STS_HBM_ECC_EN) 325 #define CPU_BOOT_DEV_STS0_PKT_PI_ACK_EN (1 << CPU_BOOT_DEV_STS_PKT_PI_ACK_EN) 326 #define CPU_BOOT_DEV_STS0_FW_LD_COM_EN (1 << CPU_BOOT_DEV_STS_FW_LD_COM_EN) 327 #define CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN (1 << CPU_BOOT_DEV_STS_FW_IATU_CONF_EN) 328 #define CPU_BOOT_DEV_STS0_FW_NIC_MAC_EN (1 << CPU_BOOT_DEV_STS_FW_NIC_MAC_EN) 329 #define CPU_BOOT_DEV_STS0_DYN_PLL_EN (1 << CPU_BOOT_DEV_STS_DYN_PLL_EN) 330 #define CPU_BOOT_DEV_STS0_GIC_PRIVILEGED_EN (1 << CPU_BOOT_DEV_STS_GIC_PRIVILEGED_EN) 331 #define CPU_BOOT_DEV_STS0_EQ_INDEX_EN (1 << CPU_BOOT_DEV_STS_EQ_INDEX_EN) 332 #define CPU_BOOT_DEV_STS0_MULTI_IRQ_POLL_EN (1 << CPU_BOOT_DEV_STS_MULTI_IRQ_POLL_EN) 333 #define CPU_BOOT_DEV_STS0_FW_NIC_STAT_XPCS91_EN (1 << CPU_BOOT_DEV_STS_FW_NIC_STAT_XPCS91_EN) 334 #define CPU_BOOT_DEV_STS0_FW_NIC_STAT_EXT_EN (1 << CPU_BOOT_DEV_STS_FW_NIC_STAT_EXT_EN) 335 #define CPU_BOOT_DEV_STS0_IS_IDLE_CHECK_EN (1 << CPU_BOOT_DEV_STS_IS_IDLE_CHECK_EN) 336 #define CPU_BOOT_DEV_STS0_MAP_HWMON_EN (1 << CPU_BOOT_DEV_STS_MAP_HWMON_EN) 337 #define CPU_BOOT_DEV_STS0_ENABLED (1 << CPU_BOOT_DEV_STS_ENABLED) 338 #define CPU_BOOT_DEV_STS1_ENABLED (1 << CPU_BOOT_DEV_STS_ENABLED) 339 340 enum cpu_boot_status { 341 CPU_BOOT_STATUS_NA = 0, /* Default value after reset of chip */ 342 CPU_BOOT_STATUS_IN_WFE = 1, 343 CPU_BOOT_STATUS_DRAM_RDY = 2, 344 CPU_BOOT_STATUS_SRAM_AVAIL = 3, 345 CPU_BOOT_STATUS_IN_BTL = 4, /* BTL is H/W FSM */ 346 CPU_BOOT_STATUS_IN_PREBOOT = 5, 347 CPU_BOOT_STATUS_IN_SPL, /* deprecated - not reported */ 348 CPU_BOOT_STATUS_IN_UBOOT = 7, 349 CPU_BOOT_STATUS_DRAM_INIT_FAIL, /* deprecated - will be removed */ 350 CPU_BOOT_STATUS_FIT_CORRUPTED, /* deprecated - will be removed */ 351 /* U-Boot console prompt activated, commands are not processed */ 352 CPU_BOOT_STATUS_UBOOT_NOT_READY = 10, 353 /* Finished NICs init, reported after DRAM and NICs */ 354 CPU_BOOT_STATUS_NIC_FW_RDY = 11, 355 CPU_BOOT_STATUS_TS_INIT_FAIL, /* deprecated - will be removed */ 356 CPU_BOOT_STATUS_DRAM_SKIPPED, /* deprecated - will be removed */ 357 CPU_BOOT_STATUS_BMC_WAITING_SKIPPED, /* deprecated - will be removed */ 358 /* Last boot loader progress status, ready to receive commands */ 359 CPU_BOOT_STATUS_READY_TO_BOOT = 15, 360 /* Internal Boot finished, ready for boot-fit */ 361 CPU_BOOT_STATUS_WAITING_FOR_BOOT_FIT = 16, 362 /* Internal Security has been initialized, device can be accessed */ 363 CPU_BOOT_STATUS_SECURITY_READY = 17, 364 }; 365 366 enum kmd_msg { 367 KMD_MSG_NA = 0, 368 KMD_MSG_GOTO_WFE, 369 KMD_MSG_FIT_RDY, 370 KMD_MSG_SKIP_BMC, 371 RESERVED, 372 KMD_MSG_RST_DEV, 373 KMD_MSG_LAST 374 }; 375 376 enum cpu_msg_status { 377 CPU_MSG_CLR = 0, 378 CPU_MSG_OK, 379 CPU_MSG_ERR, 380 }; 381 382 /* communication registers mapping - consider ABI when changing */ 383 struct cpu_dyn_regs { 384 __le32 cpu_pq_base_addr_low; 385 __le32 cpu_pq_base_addr_high; 386 __le32 cpu_pq_length; 387 __le32 cpu_pq_init_status; 388 __le32 cpu_eq_base_addr_low; 389 __le32 cpu_eq_base_addr_high; 390 __le32 cpu_eq_length; 391 __le32 cpu_eq_ci; 392 __le32 cpu_cq_base_addr_low; 393 __le32 cpu_cq_base_addr_high; 394 __le32 cpu_cq_length; 395 __le32 cpu_pf_pq_pi; 396 __le32 cpu_boot_dev_sts0; 397 __le32 cpu_boot_dev_sts1; 398 __le32 cpu_boot_err0; 399 __le32 cpu_boot_err1; 400 __le32 cpu_boot_status; 401 __le32 fw_upd_sts; 402 __le32 fw_upd_cmd; 403 __le32 fw_upd_pending_sts; 404 __le32 fuse_ver_offset; 405 __le32 preboot_ver_offset; 406 __le32 uboot_ver_offset; 407 __le32 hw_state; 408 __le32 kmd_msg_to_cpu; 409 __le32 cpu_cmd_status_to_host; 410 __le32 gic_host_pi_upd_irq; 411 __le32 gic_tpc_qm_irq_ctrl; 412 __le32 gic_mme_qm_irq_ctrl; 413 __le32 gic_dma_qm_irq_ctrl; 414 __le32 gic_nic_qm_irq_ctrl; 415 __le32 gic_dma_core_irq_ctrl; 416 __le32 gic_host_halt_irq; 417 __le32 gic_host_ints_irq; 418 __le32 gic_host_soft_rst_irq; 419 __le32 gic_rot_qm_irq_ctrl; 420 __le32 reserved1[22]; /* reserve for future use */ 421 }; 422 423 /* TODO: remove the desc magic after the code is updated to use message */ 424 /* HCDM - Habana Communications Descriptor Magic */ 425 #define HL_COMMS_DESC_MAGIC 0x4843444D 426 #define HL_COMMS_DESC_VER 1 427 428 /* HCMv - Habana Communications Message + header version */ 429 #define HL_COMMS_MSG_MAGIC_VALUE 0x48434D00 430 #define HL_COMMS_MSG_MAGIC_MASK 0xFFFFFF00 431 #define HL_COMMS_MSG_MAGIC_VER_MASK 0xFF 432 433 #define HL_COMMS_MSG_MAGIC_VER(ver) (HL_COMMS_MSG_MAGIC_VALUE | \ 434 ((ver) & HL_COMMS_MSG_MAGIC_VER_MASK)) 435 #define HL_COMMS_MSG_MAGIC_V0 HL_COMMS_DESC_MAGIC 436 #define HL_COMMS_MSG_MAGIC_V1 HL_COMMS_MSG_MAGIC_VER(1) 437 438 #define HL_COMMS_MSG_MAGIC HL_COMMS_MSG_MAGIC_V1 439 440 #define HL_COMMS_MSG_MAGIC_VALIDATE_MAGIC(magic) \ 441 (((magic) & HL_COMMS_MSG_MAGIC_MASK) == \ 442 HL_COMMS_MSG_MAGIC_VALUE) 443 444 #define HL_COMMS_MSG_MAGIC_VALIDATE_VERSION(magic, ver) \ 445 (((magic) & HL_COMMS_MSG_MAGIC_VER_MASK) >= \ 446 ((ver) & HL_COMMS_MSG_MAGIC_VER_MASK)) 447 448 #define HL_COMMS_MSG_MAGIC_VALIDATE(magic, ver) \ 449 (HL_COMMS_MSG_MAGIC_VALIDATE_MAGIC((magic)) && \ 450 HL_COMMS_MSG_MAGIC_VALIDATE_VERSION((magic), (ver))) 451 452 enum comms_msg_type { 453 HL_COMMS_DESC_TYPE = 0, 454 HL_COMMS_RESET_CAUSE_TYPE = 1, 455 HL_COMMS_FW_CFG_SKIP_TYPE = 2, 456 HL_COMMS_BINNING_CONF_TYPE = 3, 457 }; 458 459 /* TODO: remove this struct after the code is updated to use message */ 460 /* this is the comms descriptor header - meta data */ 461 struct comms_desc_header { 462 __le32 magic; /* magic for validation */ 463 __le32 crc32; /* CRC32 of the descriptor w/o header */ 464 __le16 size; /* size of the descriptor w/o header */ 465 __u8 version; /* descriptor version */ 466 __u8 reserved[5]; /* pad to 64 bit */ 467 }; 468 469 /* this is the comms message header - meta data */ 470 struct comms_msg_header { 471 __le32 magic; /* magic for validation */ 472 __le32 crc32; /* CRC32 of the message w/o header */ 473 __le16 size; /* size of the message w/o header */ 474 __u8 version; /* message payload version */ 475 __u8 type; /* message type */ 476 __u8 reserved[4]; /* pad to 64 bit */ 477 }; 478 479 /* this is the main FW descriptor - consider ABI when changing */ 480 struct lkd_fw_comms_desc { 481 struct comms_desc_header header; 482 struct cpu_dyn_regs cpu_dyn_regs; 483 char fuse_ver[VERSION_MAX_LEN]; 484 char cur_fw_ver[VERSION_MAX_LEN]; 485 /* can be used for 1 more version w/o ABI change */ 486 char reserved0[VERSION_MAX_LEN]; 487 __le64 img_addr; /* address for next FW component load */ 488 }; 489 490 enum comms_reset_cause { 491 HL_RESET_CAUSE_UNKNOWN = 0, 492 HL_RESET_CAUSE_HEARTBEAT = 1, 493 HL_RESET_CAUSE_TDR = 2, 494 }; 495 496 /* TODO: remove define after struct name is aligned on all projects */ 497 #define lkd_msg_comms lkd_fw_comms_msg 498 499 /* this is the comms message descriptor */ 500 struct lkd_fw_comms_msg { 501 struct comms_msg_header header; 502 /* union for future expantions of new messages */ 503 union { 504 struct { 505 struct cpu_dyn_regs cpu_dyn_regs; 506 char fuse_ver[VERSION_MAX_LEN]; 507 char cur_fw_ver[VERSION_MAX_LEN]; 508 /* can be used for 1 more version w/o ABI change */ 509 char reserved0[VERSION_MAX_LEN]; 510 /* address for next FW component load */ 511 __le64 img_addr; 512 }; 513 struct { 514 __u8 reset_cause; 515 }; 516 struct { 517 __u8 fw_cfg_skip; /* 1 - skip, 0 - don't skip */ 518 }; 519 }; 520 }; 521 522 /* 523 * LKD commands: 524 * 525 * COMMS_NOOP Used to clear the command register and no actual 526 * command is send. 527 * 528 * COMMS_CLR_STS Clear status command - FW should clear the 529 * status register. Used for synchronization 530 * between the commands as part of the race free 531 * protocol. 532 * 533 * COMMS_RST_STATE Reset the current communication state which is 534 * kept by FW for proper responses. 535 * Should be used in the beginning of the 536 * communication cycle to clean any leftovers from 537 * previous communication attempts. 538 * 539 * COMMS_PREP_DESC Prepare descriptor for setting up the 540 * communication and other dynamic data: 541 * struct lkd_fw_comms_desc. 542 * This command has a parameter stating the next FW 543 * component size, so the FW can actually prepare a 544 * space for it and in the status response provide 545 * the descriptor offset. The Offset of the next FW 546 * data component is a part of the descriptor 547 * structure. 548 * 549 * COMMS_DATA_RDY The FW data has been uploaded and is ready for 550 * validation. 551 * 552 * COMMS_EXEC Execute the next FW component. 553 * 554 * COMMS_RST_DEV Reset the device. 555 * 556 * COMMS_GOTO_WFE Execute WFE command. Allowed only on non-secure 557 * devices. 558 * 559 * COMMS_SKIP_BMC Perform actions required for BMC-less servers. 560 * Do not wait for BMC response. 561 * 562 * COMMS_PREP_DESC_ELBI Same as COMMS_PREP_DESC only that the memory 563 * space is allocated in a ELBI access only 564 * address range. 565 * 566 */ 567 enum comms_cmd { 568 COMMS_NOOP = 0, 569 COMMS_CLR_STS = 1, 570 COMMS_RST_STATE = 2, 571 COMMS_PREP_DESC = 3, 572 COMMS_DATA_RDY = 4, 573 COMMS_EXEC = 5, 574 COMMS_RST_DEV = 6, 575 COMMS_GOTO_WFE = 7, 576 COMMS_SKIP_BMC = 8, 577 COMMS_PREP_DESC_ELBI = 10, 578 COMMS_INVLD_LAST 579 }; 580 581 #define COMMS_COMMAND_SIZE_SHIFT 0 582 #define COMMS_COMMAND_SIZE_MASK 0x1FFFFFF 583 #define COMMS_COMMAND_CMD_SHIFT 27 584 #define COMMS_COMMAND_CMD_MASK 0xF8000000 585 586 /* 587 * LKD command to FW register structure 588 * @size - FW component size 589 * @cmd - command from enum comms_cmd 590 */ 591 struct comms_command { 592 union { /* bit fields are only for FW use */ 593 struct { 594 u32 size :25; /* 32MB max. */ 595 u32 reserved :2; 596 enum comms_cmd cmd :5; /* 32 commands */ 597 }; 598 __le32 val; 599 }; 600 }; 601 602 /* 603 * FW status 604 * 605 * COMMS_STS_NOOP Used to clear the status register and no actual 606 * status is provided. 607 * 608 * COMMS_STS_ACK Command has been received and recognized. 609 * 610 * COMMS_STS_OK Command execution has finished successfully. 611 * 612 * COMMS_STS_ERR Command execution was unsuccessful and resulted 613 * in error. 614 * 615 * COMMS_STS_VALID_ERR FW validation has failed. 616 * 617 * COMMS_STS_TIMEOUT_ERR Command execution has timed out. 618 */ 619 enum comms_sts { 620 COMMS_STS_NOOP = 0, 621 COMMS_STS_ACK = 1, 622 COMMS_STS_OK = 2, 623 COMMS_STS_ERR = 3, 624 COMMS_STS_VALID_ERR = 4, 625 COMMS_STS_TIMEOUT_ERR = 5, 626 COMMS_STS_INVLD_LAST 627 }; 628 629 /* RAM types for FW components loading - defines the base address */ 630 enum comms_ram_types { 631 COMMS_SRAM = 0, 632 COMMS_DRAM = 1, 633 }; 634 635 #define COMMS_STATUS_OFFSET_SHIFT 0 636 #define COMMS_STATUS_OFFSET_MASK 0x03FFFFFF 637 #define COMMS_STATUS_OFFSET_ALIGN_SHIFT 2 638 #define COMMS_STATUS_RAM_TYPE_SHIFT 26 639 #define COMMS_STATUS_RAM_TYPE_MASK 0x0C000000 640 #define COMMS_STATUS_STATUS_SHIFT 28 641 #define COMMS_STATUS_STATUS_MASK 0xF0000000 642 643 /* 644 * FW status to LKD register structure 645 * @offset - an offset from the base of the ram_type shifted right by 646 * 2 bits (always aligned to 32 bits). 647 * Allows a maximum addressable offset of 256MB from RAM base. 648 * Example: for real offset in RAM of 0x800000 (8MB), the value 649 * in offset field is (0x800000 >> 2) = 0x200000. 650 * @ram_type - the RAM type that should be used for offset from 651 * enum comms_ram_types 652 * @status - status from enum comms_sts 653 */ 654 struct comms_status { 655 union { /* bit fields are only for FW use */ 656 struct { 657 u32 offset :26; 658 enum comms_ram_types ram_type :2; 659 enum comms_sts status :4; /* 16 statuses */ 660 }; 661 __le32 val; 662 }; 663 }; 664 665 #endif /* HL_BOOT_IF_H */ 666