1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (C) 2013 - 2015 Fujitsu Semiconductor, Ltd
4  *              Vincent Yang <vincent.yang@tw.fujitsu.com>
5  * Copyright (C) 2015 Linaro Ltd  Andy Green <andy.green@linaro.org>
6  * Copyright (C) 2019 Socionext Inc.
7  *
8  */
9 
10 /* F_SDH30 extended Controller registers */
11 #define F_SDH30_AHB_CONFIG      0x100
12 #define  F_SDH30_AHB_BIGED      BIT(6)
13 #define  F_SDH30_BUSLOCK_DMA    BIT(5)
14 #define  F_SDH30_BUSLOCK_EN     BIT(4)
15 #define  F_SDH30_SIN            BIT(3)
16 #define  F_SDH30_AHB_INCR_16    BIT(2)
17 #define  F_SDH30_AHB_INCR_8     BIT(1)
18 #define  F_SDH30_AHB_INCR_4     BIT(0)
19 
20 #define F_SDH30_TUNING_SETTING  0x108
21 #define  F_SDH30_CMD_CHK_DIS    BIT(16)
22 
23 #define F_SDH30_IO_CONTROL2     0x114
24 #define  F_SDH30_CRES_O_DN      BIT(19)
25 #define  F_SDH30_MSEL_O_1_8     BIT(18)
26 
27 #define F_SDH30_ESD_CONTROL     0x124
28 #define	 F_SDH30_EMMC_RST		BIT(1)
29 #define  F_SDH30_CMD_DAT_DELAY	BIT(9)
30 #define	 F_SDH30_EMMC_HS200		BIT(24)
31 
32 #define F_SDH30_MIN_CLOCK		400000
33