1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2005, Intec Automation Inc.
4  * Copyright (C) 2014, Freescale Semiconductor, Inc.
5  */
6 
7 #include <linux/mtd/spi-nor.h>
8 
9 #include "core.h"
10 
11 static int
mx25l25635_post_bfpt_fixups(struct spi_nor * nor,const struct sfdp_parameter_header * bfpt_header,const struct sfdp_bfpt * bfpt)12 mx25l25635_post_bfpt_fixups(struct spi_nor *nor,
13 			    const struct sfdp_parameter_header *bfpt_header,
14 			    const struct sfdp_bfpt *bfpt)
15 {
16 	/*
17 	 * MX25L25635F supports 4B opcodes but MX25L25635E does not.
18 	 * Unfortunately, Macronix has re-used the same JEDEC ID for both
19 	 * variants which prevents us from defining a new entry in the parts
20 	 * table.
21 	 * We need a way to differentiate MX25L25635E and MX25L25635F, and it
22 	 * seems that the F version advertises support for Fast Read 4-4-4 in
23 	 * its BFPT table.
24 	 */
25 	if (bfpt->dwords[BFPT_DWORD(5)] & BFPT_DWORD5_FAST_READ_4_4_4)
26 		nor->flags |= SNOR_F_4B_OPCODES;
27 
28 	return 0;
29 }
30 
31 static struct spi_nor_fixups mx25l25635_fixups = {
32 	.post_bfpt = mx25l25635_post_bfpt_fixups,
33 };
34 
35 static const struct flash_info macronix_parts[] = {
36 	/* Macronix */
37 	{ "mx25l512e",   INFO(0xc22010, 0, 64 * 1024,   1, SECT_4K) },
38 	{ "mx25l2005a",  INFO(0xc22012, 0, 64 * 1024,   4, SECT_4K) },
39 	{ "mx25l4005a",  INFO(0xc22013, 0, 64 * 1024,   8, SECT_4K) },
40 	{ "mx25l8005",   INFO(0xc22014, 0, 64 * 1024,  16, 0) },
41 	{ "mx25l1606e",  INFO(0xc22015, 0, 64 * 1024,  32, SECT_4K) },
42 	{ "mx25l3205d",  INFO(0xc22016, 0, 64 * 1024,  64, SECT_4K) },
43 	{ "mx25l3255e",  INFO(0xc29e16, 0, 64 * 1024,  64, SECT_4K) },
44 	{ "mx25l6405d",  INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
45 	{ "mx25u2033e",  INFO(0xc22532, 0, 64 * 1024,   4, SECT_4K) },
46 	{ "mx25u3235f",	 INFO(0xc22536, 0, 64 * 1024,  64,
47 			      SECT_4K | SPI_NOR_DUAL_READ |
48 			      SPI_NOR_QUAD_READ) },
49 	{ "mx25u4035",   INFO(0xc22533, 0, 64 * 1024,   8, SECT_4K) },
50 	{ "mx25u8035",   INFO(0xc22534, 0, 64 * 1024,  16, SECT_4K) },
51 	{ "mx25u6435f",  INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
52 	{ "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, SECT_4K |
53 			      SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },
54 	{ "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
55 	{ "mx25r1635f",  INFO(0xc22815, 0, 64 * 1024,  32,
56 			      SECT_4K | SPI_NOR_DUAL_READ |
57 			      SPI_NOR_QUAD_READ) },
58 	{ "mx25r3235f",  INFO(0xc22816, 0, 64 * 1024,  64,
59 			      SECT_4K | SPI_NOR_DUAL_READ |
60 			      SPI_NOR_QUAD_READ) },
61 	{ "mx25u12835f", INFO(0xc22538, 0, 64 * 1024, 256,
62 			      SECT_4K | SPI_NOR_DUAL_READ |
63 			      SPI_NOR_QUAD_READ) },
64 	{ "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512,
65 			      SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
66 		.fixups = &mx25l25635_fixups },
67 	{ "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512,
68 			      SECT_4K | SPI_NOR_4B_OPCODES) },
69 	{ "mx25u51245g", INFO(0xc2253a, 0, 64 * 1024, 1024,
70 			      SECT_4K | SPI_NOR_DUAL_READ |
71 			      SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
72 	{ "mx25v8035f",  INFO(0xc22314, 0, 64 * 1024,  16,
73 			      SECT_4K | SPI_NOR_DUAL_READ |
74 			      SPI_NOR_QUAD_READ) },
75 	{ "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
76 	{ "mx66l51235f", INFO(0xc2201a, 0, 64 * 1024, 1024,
77 			      SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
78 			      SPI_NOR_4B_OPCODES) },
79 	{ "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024,
80 			      SECT_4K | SPI_NOR_DUAL_READ |
81 			      SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
82 	{ "mx66l1g45g",  INFO(0xc2201b, 0, 64 * 1024, 2048,
83 			      SECT_4K | SPI_NOR_DUAL_READ |
84 			      SPI_NOR_QUAD_READ) },
85 	{ "mx66l1g55g",  INFO(0xc2261b, 0, 64 * 1024, 2048,
86 			      SPI_NOR_QUAD_READ) },
87 	{ "mx66u2g45g",	 INFO(0xc2253c, 0, 64 * 1024, 4096,
88 			      SECT_4K | SPI_NOR_DUAL_READ |
89 			      SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
90 };
91 
macronix_default_init(struct spi_nor * nor)92 static void macronix_default_init(struct spi_nor *nor)
93 {
94 	nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
95 	nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode;
96 }
97 
98 static const struct spi_nor_fixups macronix_fixups = {
99 	.default_init = macronix_default_init,
100 };
101 
102 const struct spi_nor_manufacturer spi_nor_macronix = {
103 	.name = "macronix",
104 	.parts = macronix_parts,
105 	.nparts = ARRAY_SIZE(macronix_parts),
106 	.fixups = &macronix_fixups,
107 };
108