1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * mace.h - definitions for the registers in the Am79C940 MACE
4  * (Medium Access Control for Ethernet) controller.
5  *
6  * Copyright (C) 1996 Paul Mackerras.
7  */
8 
9 #define REG(x)	volatile unsigned char x; char x ## _pad[15]
10 
11 struct mace {
12 	REG(rcvfifo);		/* receive FIFO */
13 	REG(xmtfifo);		/* transmit FIFO */
14 	REG(xmtfc);		/* transmit frame control */
15 	REG(xmtfs);		/* transmit frame status */
16 	REG(xmtrc);		/* transmit retry count */
17 	REG(rcvfc);		/* receive frame control */
18 	REG(rcvfs);		/* receive frame status (4 bytes) */
19 	REG(fifofc);		/* FIFO frame count */
20 	REG(ir);		/* interrupt register */
21 	REG(imr);		/* interrupt mask register */
22 	REG(pr);		/* poll register */
23 	REG(biucc);		/* bus interface unit config control */
24 	REG(fifocc);		/* FIFO configuration control */
25 	REG(maccc);		/* medium access control config control */
26 	REG(plscc);		/* phys layer signalling config control */
27 	REG(phycc);		/* physical configuration control */
28 	REG(chipid_lo);		/* chip ID, lsb */
29 	REG(chipid_hi);		/* chip ID, msb */
30 	REG(iac);		/* internal address config */
31 	REG(reg19);
32 	REG(ladrf);		/* logical address filter (8 bytes) */
33 	REG(padr);		/* physical address (6 bytes) */
34 	REG(reg22);
35 	REG(reg23);
36 	REG(mpc);		/* missed packet count (clears when read) */
37 	REG(reg25);
38 	REG(rntpc);		/* runt packet count (clears when read) */
39 	REG(rcvcc);		/* recv collision count (clears when read) */
40 	REG(reg28);
41 	REG(utr);		/* user test reg */
42 	REG(reg30);
43 	REG(reg31);
44 };
45 
46 /* Bits in XMTFC */
47 #define DRTRY		0x80	/* don't retry transmission after collision */
48 #define DXMTFCS		0x08	/* don't append FCS to transmitted frame */
49 #define AUTO_PAD_XMIT	0x01	/* auto-pad short packets on transmission */
50 
51 /* Bits in XMTFS: only valid when XMTSV is set in PR and XMTFS */
52 #define XMTSV		0x80	/* transmit status (i.e. XMTFS) valid */
53 #define UFLO		0x40	/* underflow - xmit fifo ran dry */
54 #define LCOL		0x20	/* late collision (transmission aborted) */
55 #define MORE		0x10	/* 2 or more retries needed to xmit frame */
56 #define ONE		0x08	/* 1 retry needed to xmit frame */
57 #define DEFER		0x04	/* MACE had to defer xmission (enet busy) */
58 #define LCAR		0x02	/* loss of carrier (transmission aborted) */
59 #define RTRY		0x01	/* too many retries (transmission aborted) */
60 
61 /* Bits in XMTRC: only valid when XMTSV is set in PR (and XMTFS) */
62 #define EXDEF		0x80	/* had to defer for excessive time */
63 #define RETRY_MASK	0x0f	/* number of retries (0 - 15) */
64 
65 /* Bits in RCVFC */
66 #define LLRCV		0x08	/* low latency receive: early DMA request */
67 #define M_RBAR		0x04	/* sets function of EAM/R pin */
68 #define AUTO_STRIP_RCV	0x01	/* auto-strip short LLC frames on recv */
69 
70 /*
71  * Bits in RCVFS.  After a frame is received, four bytes of status
72  * are automatically read from this register and appended to the frame
73  * data in memory.  These are:
74  * Byte 0 and 1: message byte count and frame status
75  * Byte 2: runt packet count
76  * Byte 3: receive collision count
77  */
78 #define RS_OFLO		0x8000	/* receive FIFO overflowed */
79 #define RS_CLSN		0x4000	/* received frame suffered (late) collision */
80 #define RS_FRAMERR	0x2000	/* framing error flag */
81 #define RS_FCSERR	0x1000	/* frame had FCS error */
82 #define RS_COUNT	0x0fff	/* mask for byte count field */
83 
84 /* Bits (fields) in FIFOFC */
85 #define RCVFC_SH	4	/* receive frame count in FIFO */
86 #define RCVFC_MASK	0x0f
87 #define XMTFC_SH	0	/* transmit frame count in FIFO */
88 #define XMTFC_MASK	0x0f
89 
90 /*
91  * Bits in IR and IMR.  The IR clears itself when read.
92  * Setting a bit in the IMR will disable the corresponding interrupt.
93  */
94 #define JABBER		0x80	/* jabber error - 10baseT xmission too long */
95 #define BABBLE		0x40	/* babble - xmitter xmitting for too long */
96 #define CERR		0x20	/* collision err - no SQE test (heartbeat) */
97 #define RCVCCO		0x10	/* RCVCC overflow */
98 #define RNTPCO		0x08	/* RNTPC overflow */
99 #define MPCO		0x04	/* MPC overflow */
100 #define RCVINT		0x02	/* receive interrupt */
101 #define XMTINT		0x01	/* transmitter interrupt */
102 
103 /* Bits in PR */
104 #define XMTSV		0x80	/* XMTFS valid (same as in XMTFS) */
105 #define TDTREQ		0x40	/* set when xmit fifo is requesting data */
106 #define RDTREQ		0x20	/* set when recv fifo requests data xfer */
107 
108 /* Bits in BIUCC */
109 #define BSWP		0x40	/* byte swap, i.e. big-endian bus */
110 #define XMTSP_4		0x00	/* start xmitting when 4 bytes in FIFO */
111 #define XMTSP_16	0x10	/* start xmitting when 16 bytes in FIFO */
112 #define XMTSP_64	0x20	/* start xmitting when 64 bytes in FIFO */
113 #define XMTSP_112	0x30	/* start xmitting when 112 bytes in FIFO */
114 #define SWRST		0x01	/* software reset */
115 
116 /* Bits in FIFOCC */
117 #define XMTFW_8		0x00	/* xmit fifo watermark = 8 words free */
118 #define XMTFW_16	0x40	/*  16 words free */
119 #define XMTFW_32	0x80	/*  32 words free */
120 #define RCVFW_16	0x00	/* recv fifo watermark = 16 bytes avail */
121 #define RCVFW_32	0x10	/*  32 bytes avail */
122 #define RCVFW_64	0x20	/*  64 bytes avail */
123 #define XMTFWU		0x08	/* xmit fifo watermark update enable */
124 #define RCVFWU		0x04	/* recv fifo watermark update enable */
125 #define XMTBRST		0x02	/* enable transmit burst mode */
126 #define RCVBRST		0x01	/* enable receive burst mode */
127 
128 /* Bits in MACCC */
129 #define PROM		0x80	/* promiscuous mode */
130 #define DXMT2PD		0x40	/* disable xmit two-part deferral algorithm */
131 #define EMBA		0x20	/* enable modified backoff algorithm */
132 #define DRCVPA		0x08	/* disable receiving physical address */
133 #define DRCVBC		0x04	/* disable receiving broadcasts */
134 #define ENXMT		0x02	/* enable transmitter */
135 #define ENRCV		0x01	/* enable receiver */
136 
137 /* Bits in PLSCC */
138 #define XMTSEL		0x08	/* select DO+/DO- state when idle */
139 #define PORTSEL_AUI	0x00	/* select AUI port */
140 #define PORTSEL_10T	0x02	/* select 10Base-T port */
141 #define PORTSEL_DAI	0x04	/* select DAI port */
142 #define PORTSEL_GPSI	0x06	/* select GPSI port */
143 #define ENPLSIO		0x01	/* enable optional PLS I/O pins */
144 
145 /* Bits in PHYCC */
146 #define LNKFL		0x80	/* reports 10Base-T link failure */
147 #define DLNKTST		0x40	/* disable 10Base-T link test */
148 #define REVPOL		0x20	/* 10Base-T receiver polarity reversed */
149 #define DAPC		0x10	/* disable auto receiver polarity correction */
150 #define LRT		0x08	/* low receive threshold for long links */
151 #define ASEL		0x04	/* auto-select AUI or 10Base-T port */
152 #define RWAKE		0x02	/* remote wake function */
153 #define AWAKE		0x01	/* auto wake function */
154 
155 /* Bits in IAC */
156 #define ADDRCHG		0x80	/* request address change */
157 #define PHYADDR		0x04	/* access physical address */
158 #define LOGADDR		0x02	/* access multicast filter */
159 
160 /* Bits in UTR */
161 #define RTRE		0x80	/* reserved test register enable. DON'T SET. */
162 #define RTRD		0x40	/* reserved test register disable.  Sticky */
163 #define RPAC		0x20	/* accept runt packets */
164 #define FCOLL		0x10	/* force collision */
165 #define RCVFCSE		0x08	/* receive FCS enable */
166 #define LOOP_NONE	0x00	/* no loopback */
167 #define LOOP_EXT	0x02	/* external loopback */
168 #define LOOP_INT	0x04	/* internal loopback, excludes MENDEC */
169 #define LOOP_MENDEC	0x06	/* internal loopback, includes MENDEC */
170