1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 * Google virtual Ethernet (gve) driver
3 *
4 * Copyright (C) 2015-2021 Google, Inc.
5 */
6
7 #ifndef _GVE_DQO_H_
8 #define _GVE_DQO_H_
9
10 #include "gve_adminq.h"
11
12 #define GVE_ITR_ENABLE_BIT_DQO BIT(0)
13 #define GVE_ITR_CLEAR_PBA_BIT_DQO BIT(1)
14 #define GVE_ITR_NO_UPDATE_DQO (3 << 3)
15
16 #define GVE_ITR_INTERVAL_DQO_SHIFT 5
17 #define GVE_ITR_INTERVAL_DQO_MASK ((1 << 12) - 1)
18
19 #define GVE_TX_IRQ_RATELIMIT_US_DQO 50
20 #define GVE_RX_IRQ_RATELIMIT_US_DQO 20
21
22 /* Timeout in seconds to wait for a reinjection completion after receiving
23 * its corresponding miss completion.
24 */
25 #define GVE_REINJECT_COMPL_TIMEOUT 1
26
27 /* Timeout in seconds to deallocate the completion tag for a packet that was
28 * prematurely freed for not receiving a valid completion. This should be large
29 * enough to rule out the possibility of receiving the corresponding valid
30 * completion after this interval.
31 */
32 #define GVE_DEALLOCATE_COMPL_TIMEOUT 60
33
34 netdev_tx_t gve_tx_dqo(struct sk_buff *skb, struct net_device *dev);
35 bool gve_tx_poll_dqo(struct gve_notify_block *block, bool do_clean);
36 int gve_rx_poll_dqo(struct gve_notify_block *block, int budget);
37 int gve_tx_alloc_rings_dqo(struct gve_priv *priv);
38 void gve_tx_free_rings_dqo(struct gve_priv *priv);
39 int gve_rx_alloc_rings_dqo(struct gve_priv *priv);
40 void gve_rx_free_rings_dqo(struct gve_priv *priv);
41 int gve_clean_tx_done_dqo(struct gve_priv *priv, struct gve_tx_ring *tx,
42 struct napi_struct *napi);
43 void gve_rx_post_buffers_dqo(struct gve_rx_ring *rx);
44 void gve_rx_write_doorbell_dqo(const struct gve_priv *priv, int queue_idx);
45
46 static inline void
gve_tx_put_doorbell_dqo(const struct gve_priv * priv,const struct gve_queue_resources * q_resources,u32 val)47 gve_tx_put_doorbell_dqo(const struct gve_priv *priv,
48 const struct gve_queue_resources *q_resources, u32 val)
49 {
50 u64 index;
51
52 index = be32_to_cpu(q_resources->db_index);
53 iowrite32(val, &priv->db_bar2[index]);
54 }
55
56 /* Builds register value to write to DQO IRQ doorbell to enable with specified
57 * ratelimit.
58 */
gve_set_itr_ratelimit_dqo(u32 ratelimit_us)59 static inline u32 gve_set_itr_ratelimit_dqo(u32 ratelimit_us)
60 {
61 u32 result = GVE_ITR_ENABLE_BIT_DQO;
62
63 /* Interval has 2us granularity. */
64 ratelimit_us >>= 1;
65
66 ratelimit_us &= GVE_ITR_INTERVAL_DQO_MASK;
67 result |= (ratelimit_us << GVE_ITR_INTERVAL_DQO_SHIFT);
68
69 return result;
70 }
71
72 static inline void
gve_write_irq_doorbell_dqo(const struct gve_priv * priv,const struct gve_notify_block * block,u32 val)73 gve_write_irq_doorbell_dqo(const struct gve_priv *priv,
74 const struct gve_notify_block *block, u32 val)
75 {
76 u32 index = be32_to_cpu(block->irq_db_index);
77
78 iowrite32(val, &priv->db_bar2[index]);
79 }
80
81 #endif /* _GVE_DQO_H_ */
82