1 /*
2 * Copyright (c) 2017 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34 #ifndef __MLX5_FPGA_IPSEC_H__
35 #define __MLX5_FPGA_IPSEC_H__
36
37 #include "accel/ipsec.h"
38 #include "fs_cmd.h"
39
40 #ifdef CONFIG_MLX5_FPGA_IPSEC
41 const struct mlx5_accel_ipsec_ops *mlx5_fpga_ipsec_ops(struct mlx5_core_dev *mdev);
42 u32 mlx5_fpga_ipsec_device_caps(struct mlx5_core_dev *mdev);
43 const struct mlx5_flow_cmds *
44 mlx5_fs_cmd_get_default_ipsec_fpga_cmds(enum fs_flow_table_type type);
45 void mlx5_fpga_ipsec_build_fs_cmds(void);
46 bool mlx5_fpga_is_ipsec_device(struct mlx5_core_dev *mdev);
47 #else
48 static inline
mlx5_fpga_ipsec_ops(struct mlx5_core_dev * mdev)49 const struct mlx5_accel_ipsec_ops *mlx5_fpga_ipsec_ops(struct mlx5_core_dev *mdev)
50 { return NULL; }
mlx5_fpga_ipsec_device_caps(struct mlx5_core_dev * mdev)51 static inline u32 mlx5_fpga_ipsec_device_caps(struct mlx5_core_dev *mdev) { return 0; }
52 static inline const struct mlx5_flow_cmds *
mlx5_fs_cmd_get_default_ipsec_fpga_cmds(enum fs_flow_table_type type)53 mlx5_fs_cmd_get_default_ipsec_fpga_cmds(enum fs_flow_table_type type)
54 {
55 return mlx5_fs_cmd_get_default(type);
56 }
57
mlx5_fpga_ipsec_build_fs_cmds(void)58 static inline void mlx5_fpga_ipsec_build_fs_cmds(void) {};
mlx5_fpga_is_ipsec_device(struct mlx5_core_dev * mdev)59 static inline bool mlx5_fpga_is_ipsec_device(struct mlx5_core_dev *mdev) { return false; }
60
61 #endif /* CONFIG_MLX5_FPGA_IPSEC */
62 #endif /* __MLX5_FPGA_IPSEC_H__ */
63