1 // SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
2
3 /* MDIO support for Mellanox Gigabit Ethernet driver
4 *
5 * Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES
6 */
7
8 #include <linux/acpi.h>
9 #include <linux/bitfield.h>
10 #include <linux/delay.h>
11 #include <linux/device.h>
12 #include <linux/err.h>
13 #include <linux/io.h>
14 #include <linux/iopoll.h>
15 #include <linux/ioport.h>
16 #include <linux/irqreturn.h>
17 #include <linux/jiffies.h>
18 #include <linux/module.h>
19 #include <linux/mod_devicetable.h>
20 #include <linux/phy.h>
21 #include <linux/platform_device.h>
22 #include <linux/property.h>
23
24 #include "mlxbf_gige.h"
25
26 #define MLXBF_GIGE_MDIO_GW_OFFSET 0x0
27 #define MLXBF_GIGE_MDIO_CFG_OFFSET 0x4
28
29 /* Support clause 22 */
30 #define MLXBF_GIGE_MDIO_CL22_ST1 0x1
31 #define MLXBF_GIGE_MDIO_CL22_WRITE 0x1
32 #define MLXBF_GIGE_MDIO_CL22_READ 0x2
33
34 /* Busy bit is set by software and cleared by hardware */
35 #define MLXBF_GIGE_MDIO_SET_BUSY 0x1
36
37 /* MDIO GW register bits */
38 #define MLXBF_GIGE_MDIO_GW_AD_MASK GENMASK(15, 0)
39 #define MLXBF_GIGE_MDIO_GW_DEVAD_MASK GENMASK(20, 16)
40 #define MLXBF_GIGE_MDIO_GW_PARTAD_MASK GENMASK(25, 21)
41 #define MLXBF_GIGE_MDIO_GW_OPCODE_MASK GENMASK(27, 26)
42 #define MLXBF_GIGE_MDIO_GW_ST1_MASK GENMASK(28, 28)
43 #define MLXBF_GIGE_MDIO_GW_BUSY_MASK GENMASK(30, 30)
44
45 /* MDIO config register bits */
46 #define MLXBF_GIGE_MDIO_CFG_MDIO_MODE_MASK GENMASK(1, 0)
47 #define MLXBF_GIGE_MDIO_CFG_MDIO3_3_MASK GENMASK(2, 2)
48 #define MLXBF_GIGE_MDIO_CFG_MDIO_FULL_DRIVE_MASK GENMASK(4, 4)
49 #define MLXBF_GIGE_MDIO_CFG_MDC_PERIOD_MASK GENMASK(15, 8)
50 #define MLXBF_GIGE_MDIO_CFG_MDIO_IN_SAMP_MASK GENMASK(23, 16)
51 #define MLXBF_GIGE_MDIO_CFG_MDIO_OUT_SAMP_MASK GENMASK(31, 24)
52
53 /* Formula for encoding the MDIO period. The encoded value is
54 * passed to the MDIO config register.
55 *
56 * mdc_clk = 2*(val + 1)*i1clk
57 *
58 * 400 ns = 2*(val + 1)*(((1/430)*1000) ns)
59 *
60 * val = (((400 * 430 / 1000) / 2) - 1)
61 */
62 #define MLXBF_GIGE_I1CLK_MHZ 430
63 #define MLXBF_GIGE_MDC_CLK_NS 400
64
65 #define MLXBF_GIGE_MDIO_PERIOD (((MLXBF_GIGE_MDC_CLK_NS * MLXBF_GIGE_I1CLK_MHZ / 1000) / 2) - 1)
66
67 #define MLXBF_GIGE_MDIO_CFG_VAL (FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO_MODE_MASK, 1) | \
68 FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO3_3_MASK, 1) | \
69 FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO_FULL_DRIVE_MASK, 1) | \
70 FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDC_PERIOD_MASK, \
71 MLXBF_GIGE_MDIO_PERIOD) | \
72 FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO_IN_SAMP_MASK, 6) | \
73 FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO_OUT_SAMP_MASK, 13))
74
mlxbf_gige_mdio_create_cmd(u16 data,int phy_add,int phy_reg,u32 opcode)75 static u32 mlxbf_gige_mdio_create_cmd(u16 data, int phy_add,
76 int phy_reg, u32 opcode)
77 {
78 u32 gw_reg = 0;
79
80 gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_AD_MASK, data);
81 gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_DEVAD_MASK, phy_reg);
82 gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_PARTAD_MASK, phy_add);
83 gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_OPCODE_MASK, opcode);
84 gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_ST1_MASK,
85 MLXBF_GIGE_MDIO_CL22_ST1);
86 gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_BUSY_MASK,
87 MLXBF_GIGE_MDIO_SET_BUSY);
88
89 return gw_reg;
90 }
91
mlxbf_gige_mdio_read(struct mii_bus * bus,int phy_add,int phy_reg)92 static int mlxbf_gige_mdio_read(struct mii_bus *bus, int phy_add, int phy_reg)
93 {
94 struct mlxbf_gige *priv = bus->priv;
95 u32 cmd;
96 int ret;
97 u32 val;
98
99 if (phy_reg & MII_ADDR_C45)
100 return -EOPNOTSUPP;
101
102 /* Send mdio read request */
103 cmd = mlxbf_gige_mdio_create_cmd(0, phy_add, phy_reg, MLXBF_GIGE_MDIO_CL22_READ);
104
105 writel(cmd, priv->mdio_io + MLXBF_GIGE_MDIO_GW_OFFSET);
106
107 ret = readl_poll_timeout_atomic(priv->mdio_io + MLXBF_GIGE_MDIO_GW_OFFSET,
108 val, !(val & MLXBF_GIGE_MDIO_GW_BUSY_MASK), 100, 1000000);
109
110 if (ret) {
111 writel(0, priv->mdio_io + MLXBF_GIGE_MDIO_GW_OFFSET);
112 return ret;
113 }
114
115 ret = readl(priv->mdio_io + MLXBF_GIGE_MDIO_GW_OFFSET);
116 /* Only return ad bits of the gw register */
117 ret &= MLXBF_GIGE_MDIO_GW_AD_MASK;
118
119 return ret;
120 }
121
mlxbf_gige_mdio_write(struct mii_bus * bus,int phy_add,int phy_reg,u16 val)122 static int mlxbf_gige_mdio_write(struct mii_bus *bus, int phy_add,
123 int phy_reg, u16 val)
124 {
125 struct mlxbf_gige *priv = bus->priv;
126 u32 cmd;
127 int ret;
128 u32 temp;
129
130 if (phy_reg & MII_ADDR_C45)
131 return -EOPNOTSUPP;
132
133 /* Send mdio write request */
134 cmd = mlxbf_gige_mdio_create_cmd(val, phy_add, phy_reg,
135 MLXBF_GIGE_MDIO_CL22_WRITE);
136 writel(cmd, priv->mdio_io + MLXBF_GIGE_MDIO_GW_OFFSET);
137
138 /* If the poll timed out, drop the request */
139 ret = readl_poll_timeout_atomic(priv->mdio_io + MLXBF_GIGE_MDIO_GW_OFFSET,
140 temp, !(temp & MLXBF_GIGE_MDIO_GW_BUSY_MASK), 100, 1000000);
141
142 return ret;
143 }
144
mlxbf_gige_mdio_probe(struct platform_device * pdev,struct mlxbf_gige * priv)145 int mlxbf_gige_mdio_probe(struct platform_device *pdev, struct mlxbf_gige *priv)
146 {
147 struct device *dev = &pdev->dev;
148 int ret;
149
150 priv->mdio_io = devm_platform_ioremap_resource(pdev, MLXBF_GIGE_RES_MDIO9);
151 if (IS_ERR(priv->mdio_io))
152 return PTR_ERR(priv->mdio_io);
153
154 /* Configure mdio parameters */
155 writel(MLXBF_GIGE_MDIO_CFG_VAL,
156 priv->mdio_io + MLXBF_GIGE_MDIO_CFG_OFFSET);
157
158 priv->mdiobus = devm_mdiobus_alloc(dev);
159 if (!priv->mdiobus) {
160 dev_err(dev, "Failed to alloc MDIO bus\n");
161 return -ENOMEM;
162 }
163
164 priv->mdiobus->name = "mlxbf-mdio";
165 priv->mdiobus->read = mlxbf_gige_mdio_read;
166 priv->mdiobus->write = mlxbf_gige_mdio_write;
167 priv->mdiobus->parent = dev;
168 priv->mdiobus->priv = priv;
169 snprintf(priv->mdiobus->id, MII_BUS_ID_SIZE, "%s",
170 dev_name(dev));
171
172 ret = mdiobus_register(priv->mdiobus);
173 if (ret)
174 dev_err(dev, "Failed to register MDIO bus\n");
175
176 return ret;
177 }
178
mlxbf_gige_mdio_remove(struct mlxbf_gige * priv)179 void mlxbf_gige_mdio_remove(struct mlxbf_gige *priv)
180 {
181 mdiobus_unregister(priv->mdiobus);
182 }
183