1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 #ifndef _LMC_IOCTL_H_ 3 #define _LMC_IOCTL_H_ 4 /* $Id: lmc_ioctl.h,v 1.15 2000/04/06 12:16:43 asj Exp $ */ 5 6 /* 7 * Copyright (c) 1997-2000 LAN Media Corporation (LMC) 8 * All rights reserved. www.lanmedia.com 9 * 10 * This code is written by: 11 * Andrew Stanley-Jones (asj@cban.com) 12 * Rob Braun (bbraun@vix.com), 13 * Michael Graff (explorer@vix.com) and 14 * Matt Thomas (matt@3am-software.com). 15 */ 16 17 #define LMCIOCGINFO SIOCDEVPRIVATE+3 /* get current state */ 18 #define LMCIOCSINFO SIOCDEVPRIVATE+4 /* set state to user values */ 19 #define LMCIOCGETLMCSTATS SIOCDEVPRIVATE+5 20 #define LMCIOCCLEARLMCSTATS SIOCDEVPRIVATE+6 21 #define LMCIOCDUMPEVENTLOG SIOCDEVPRIVATE+7 22 #define LMCIOCGETXINFO SIOCDEVPRIVATE+8 23 #define LMCIOCSETCIRCUIT SIOCDEVPRIVATE+9 24 #define LMCIOCUNUSEDATM SIOCDEVPRIVATE+10 25 #define LMCIOCRESET SIOCDEVPRIVATE+11 26 #define LMCIOCT1CONTROL SIOCDEVPRIVATE+12 27 #define LMCIOCIFTYPE SIOCDEVPRIVATE+13 28 #define LMCIOCXILINX SIOCDEVPRIVATE+14 29 30 #define LMC_CARDTYPE_UNKNOWN -1 31 #define LMC_CARDTYPE_HSSI 1 /* probed card is a HSSI card */ 32 #define LMC_CARDTYPE_DS3 2 /* probed card is a DS3 card */ 33 #define LMC_CARDTYPE_SSI 3 /* probed card is a SSI card */ 34 #define LMC_CARDTYPE_T1 4 /* probed card is a T1 card */ 35 36 #define LMC_CTL_CARDTYPE_LMC5200 0 /* HSSI */ 37 #define LMC_CTL_CARDTYPE_LMC5245 1 /* DS3 */ 38 #define LMC_CTL_CARDTYPE_LMC1000 2 /* SSI, V.35 */ 39 #define LMC_CTL_CARDTYPE_LMC1200 3 /* DS1 */ 40 41 #define LMC_CTL_OFF 0 /* generic OFF value */ 42 #define LMC_CTL_ON 1 /* generic ON value */ 43 44 #define LMC_CTL_CLOCK_SOURCE_EXT 0 /* clock off line */ 45 #define LMC_CTL_CLOCK_SOURCE_INT 1 /* internal clock */ 46 47 #define LMC_CTL_CRC_LENGTH_16 16 48 #define LMC_CTL_CRC_LENGTH_32 32 49 #define LMC_CTL_CRC_BYTESIZE_2 2 50 #define LMC_CTL_CRC_BYTESIZE_4 4 51 52 53 #define LMC_CTL_CABLE_LENGTH_LT_100FT 0 /* DS3 cable < 100 feet */ 54 #define LMC_CTL_CABLE_LENGTH_GT_100FT 1 /* DS3 cable >= 100 feet */ 55 56 #define LMC_CTL_CIRCUIT_TYPE_E1 0 57 #define LMC_CTL_CIRCUIT_TYPE_T1 1 58 59 /* 60 * IFTYPE defines 61 */ 62 #define LMC_PPP 1 /* use generic HDLC interface */ 63 #define LMC_NET 2 /* use direct net interface */ 64 #define LMC_RAW 3 /* use direct net interface */ 65 66 /* 67 * These are not in the least IOCTL related, but I want them common. 68 */ 69 /* 70 * assignments for the GPIO register on the DEC chip (common) 71 */ 72 #define LMC_GEP_INIT 0x01 /* 0: */ 73 #define LMC_GEP_RESET 0x02 /* 1: */ 74 #define LMC_GEP_MODE 0x10 /* 4: */ 75 #define LMC_GEP_DP 0x20 /* 5: */ 76 #define LMC_GEP_DATA 0x40 /* 6: serial out */ 77 #define LMC_GEP_CLK 0x80 /* 7: serial clock */ 78 79 /* 80 * HSSI GPIO assignments 81 */ 82 #define LMC_GEP_HSSI_ST 0x04 /* 2: receive timing sense (deprecated) */ 83 #define LMC_GEP_HSSI_CLOCK 0x08 /* 3: clock source */ 84 85 /* 86 * T1 GPIO assignments 87 */ 88 #define LMC_GEP_SSI_GENERATOR 0x04 /* 2: enable prog freq gen serial i/f */ 89 #define LMC_GEP_SSI_TXCLOCK 0x08 /* 3: provide clock on TXCLOCK output */ 90 91 /* 92 * Common MII16 bits 93 */ 94 #define LMC_MII16_LED0 0x0080 95 #define LMC_MII16_LED1 0x0100 96 #define LMC_MII16_LED2 0x0200 97 #define LMC_MII16_LED3 0x0400 /* Error, and the red one */ 98 #define LMC_MII16_LED_ALL 0x0780 /* LED bit mask */ 99 #define LMC_MII16_FIFO_RESET 0x0800 100 101 /* 102 * definitions for HSSI 103 */ 104 #define LMC_MII16_HSSI_TA 0x0001 105 #define LMC_MII16_HSSI_CA 0x0002 106 #define LMC_MII16_HSSI_LA 0x0004 107 #define LMC_MII16_HSSI_LB 0x0008 108 #define LMC_MII16_HSSI_LC 0x0010 109 #define LMC_MII16_HSSI_TM 0x0020 110 #define LMC_MII16_HSSI_CRC 0x0040 111 112 /* 113 * assignments for the MII register 16 (DS3) 114 */ 115 #define LMC_MII16_DS3_ZERO 0x0001 116 #define LMC_MII16_DS3_TRLBK 0x0002 117 #define LMC_MII16_DS3_LNLBK 0x0004 118 #define LMC_MII16_DS3_RAIS 0x0008 119 #define LMC_MII16_DS3_TAIS 0x0010 120 #define LMC_MII16_DS3_BIST 0x0020 121 #define LMC_MII16_DS3_DLOS 0x0040 122 #define LMC_MII16_DS3_CRC 0x1000 123 #define LMC_MII16_DS3_SCRAM 0x2000 124 #define LMC_MII16_DS3_SCRAM_LARS 0x4000 125 126 /* Note: 2 pairs of LEDs where swapped by mistake 127 * in Xilinx code for DS3 & DS1 adapters */ 128 #define LMC_DS3_LED0 0x0100 /* bit 08 yellow */ 129 #define LMC_DS3_LED1 0x0080 /* bit 07 blue */ 130 #define LMC_DS3_LED2 0x0400 /* bit 10 green */ 131 #define LMC_DS3_LED3 0x0200 /* bit 09 red */ 132 133 /* 134 * framer register 0 and 7 (7 is latched and reset on read) 135 */ 136 #define LMC_FRAMER_REG0_DLOS 0x80 /* digital loss of service */ 137 #define LMC_FRAMER_REG0_OOFS 0x40 /* out of frame sync */ 138 #define LMC_FRAMER_REG0_AIS 0x20 /* alarm indication signal */ 139 #define LMC_FRAMER_REG0_CIS 0x10 /* channel idle */ 140 #define LMC_FRAMER_REG0_LOC 0x08 /* loss of clock */ 141 142 /* 143 * Framer register 9 contains the blue alarm signal 144 */ 145 #define LMC_FRAMER_REG9_RBLUE 0x02 /* Blue alarm failure */ 146 147 /* 148 * Framer register 0x10 contains xbit error 149 */ 150 #define LMC_FRAMER_REG10_XBIT 0x01 /* X bit error alarm failure */ 151 152 /* 153 * And SSI, LMC1000 154 */ 155 #define LMC_MII16_SSI_DTR 0x0001 /* DTR output RW */ 156 #define LMC_MII16_SSI_DSR 0x0002 /* DSR input RO */ 157 #define LMC_MII16_SSI_RTS 0x0004 /* RTS output RW */ 158 #define LMC_MII16_SSI_CTS 0x0008 /* CTS input RO */ 159 #define LMC_MII16_SSI_DCD 0x0010 /* DCD input RO */ 160 #define LMC_MII16_SSI_RI 0x0020 /* RI input RO */ 161 #define LMC_MII16_SSI_CRC 0x1000 /* CRC select - RW */ 162 163 /* 164 * bits 0x0080 through 0x0800 are generic, and described 165 * above with LMC_MII16_LED[0123] _LED_ALL, and _FIFO_RESET 166 */ 167 #define LMC_MII16_SSI_LL 0x1000 /* LL output RW */ 168 #define LMC_MII16_SSI_RL 0x2000 /* RL output RW */ 169 #define LMC_MII16_SSI_TM 0x4000 /* TM input RO */ 170 #define LMC_MII16_SSI_LOOP 0x8000 /* loopback enable RW */ 171 172 /* 173 * Some of the MII16 bits are mirrored in the MII17 register as well, 174 * but let's keep thing separate for now, and get only the cable from 175 * the MII17. 176 */ 177 #define LMC_MII17_SSI_CABLE_MASK 0x0038 /* mask to extract the cable type */ 178 #define LMC_MII17_SSI_CABLE_SHIFT 3 /* shift to extract the cable type */ 179 180 /* 181 * And T1, LMC1200 182 */ 183 #define LMC_MII16_T1_UNUSED1 0x0003 184 #define LMC_MII16_T1_XOE 0x0004 185 #define LMC_MII16_T1_RST 0x0008 /* T1 chip reset - RW */ 186 #define LMC_MII16_T1_Z 0x0010 /* output impedance T1=1, E1=0 output - RW */ 187 #define LMC_MII16_T1_INTR 0x0020 /* interrupt from 8370 - RO */ 188 #define LMC_MII16_T1_ONESEC 0x0040 /* one second square wave - ro */ 189 190 #define LMC_MII16_T1_LED0 0x0100 191 #define LMC_MII16_T1_LED1 0x0080 192 #define LMC_MII16_T1_LED2 0x0400 193 #define LMC_MII16_T1_LED3 0x0200 194 #define LMC_MII16_T1_FIFO_RESET 0x0800 195 196 #define LMC_MII16_T1_CRC 0x1000 /* CRC select - RW */ 197 #define LMC_MII16_T1_UNUSED2 0xe000 198 199 200 /* 8370 framer registers */ 201 202 #define T1FRAMER_ALARM1_STATUS 0x47 203 #define T1FRAMER_ALARM2_STATUS 0x48 204 #define T1FRAMER_FERR_LSB 0x50 205 #define T1FRAMER_FERR_MSB 0x51 /* framing bit error counter */ 206 #define T1FRAMER_LCV_LSB 0x54 207 #define T1FRAMER_LCV_MSB 0x55 /* line code violation counter */ 208 #define T1FRAMER_AERR 0x5A 209 210 /* mask for the above AERR register */ 211 #define T1FRAMER_LOF_MASK (0x0f0) /* receive loss of frame */ 212 #define T1FRAMER_COFA_MASK (0x0c0) /* change of frame alignment */ 213 #define T1FRAMER_SEF_MASK (0x03) /* severely errored frame */ 214 215 /* 8370 framer register ALM1 (0x47) values 216 * used to determine link status 217 */ 218 219 #define T1F_SIGFRZ 0x01 /* signaling freeze */ 220 #define T1F_RLOF 0x02 /* receive loss of frame alignment */ 221 #define T1F_RLOS 0x04 /* receive loss of signal */ 222 #define T1F_RALOS 0x08 /* receive analog loss of signal or RCKI loss of clock */ 223 #define T1F_RAIS 0x10 /* receive alarm indication signal */ 224 #define T1F_UNUSED 0x20 225 #define T1F_RYEL 0x40 /* receive yellow alarm */ 226 #define T1F_RMYEL 0x80 /* receive multiframe yellow alarm */ 227 228 #define LMC_T1F_WRITE 0 229 #define LMC_T1F_READ 1 230 231 typedef struct lmc_st1f_control { 232 int command; 233 int address; 234 int value; 235 char __user *data; 236 } lmc_t1f_control; 237 238 enum lmc_xilinx_c { 239 lmc_xilinx_reset = 1, 240 lmc_xilinx_load_prom = 2, 241 lmc_xilinx_load = 3 242 }; 243 244 struct lmc_xilinx_control { 245 enum lmc_xilinx_c command; 246 int len; 247 char __user *data; 248 }; 249 250 /* ------------------ end T1 defs ------------------- */ 251 252 #define LMC_MII_LedMask 0x0780 253 #define LMC_MII_LedBitPos 7 254 255 #endif 256