1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3 * Copyright (C) 2017 Intel Deutschland GmbH
4 * Copyright (C) 2018-2021 Intel Corporation
5 */
6 #include "iwl-trans.h"
7 #include "iwl-prph.h"
8 #include "iwl-context-info.h"
9 #include "iwl-context-info-gen3.h"
10 #include "internal.h"
11 #include "fw/dbg.h"
12
13 #define FW_RESET_TIMEOUT (HZ / 5)
14
15 /*
16 * Start up NIC's basic functionality after it has been reset
17 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
18 * NOTE: This does not load uCode nor start the embedded processor
19 */
iwl_pcie_gen2_apm_init(struct iwl_trans * trans)20 int iwl_pcie_gen2_apm_init(struct iwl_trans *trans)
21 {
22 int ret = 0;
23
24 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
25
26 /*
27 * Use "set_bit" below rather than "write", to preserve any hardware
28 * bits already set by default after reset.
29 */
30
31 /*
32 * Disable L0s without affecting L1;
33 * don't wait for ICH L0s (ICH bug W/A)
34 */
35 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
36 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
37
38 /* Set FH wait threshold to maximum (HW error during stress W/A) */
39 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
40
41 /*
42 * Enable HAP INTA (interrupt from management bus) to
43 * wake device's PCI Express link L1a -> L0s
44 */
45 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
46 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
47
48 iwl_pcie_apm_config(trans);
49
50 ret = iwl_finish_nic_init(trans);
51 if (ret)
52 return ret;
53
54 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
55
56 return 0;
57 }
58
iwl_pcie_gen2_apm_stop(struct iwl_trans * trans,bool op_mode_leave)59 static void iwl_pcie_gen2_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
60 {
61 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
62
63 if (op_mode_leave) {
64 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
65 iwl_pcie_gen2_apm_init(trans);
66
67 /* inform ME that we are leaving */
68 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
69 CSR_RESET_LINK_PWR_MGMT_DISABLED);
70 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
71 CSR_HW_IF_CONFIG_REG_PREPARE |
72 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
73 mdelay(1);
74 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
75 CSR_RESET_LINK_PWR_MGMT_DISABLED);
76 mdelay(5);
77 }
78
79 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
80
81 /* Stop device's DMA activity */
82 iwl_pcie_apm_stop_master(trans);
83
84 iwl_trans_sw_reset(trans);
85
86 /*
87 * Clear "initialization complete" bit to move adapter from
88 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
89 */
90 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
91 iwl_clear_bit(trans, CSR_GP_CNTRL,
92 CSR_GP_CNTRL_REG_FLAG_MAC_INIT);
93 else
94 iwl_clear_bit(trans, CSR_GP_CNTRL,
95 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
96 }
97
iwl_trans_pcie_fw_reset_handshake(struct iwl_trans * trans)98 static void iwl_trans_pcie_fw_reset_handshake(struct iwl_trans *trans)
99 {
100 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
101 int ret;
102
103 trans_pcie->fw_reset_state = FW_RESET_REQUESTED;
104
105 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
106 iwl_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER,
107 UREG_NIC_SET_NMI_DRIVER_RESET_HANDSHAKE);
108 else
109 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
110 UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);
111
112 /* wait 200ms */
113 ret = wait_event_timeout(trans_pcie->fw_reset_waitq,
114 trans_pcie->fw_reset_state != FW_RESET_REQUESTED,
115 FW_RESET_TIMEOUT);
116 if (!ret || trans_pcie->fw_reset_state == FW_RESET_ERROR) {
117 IWL_INFO(trans,
118 "firmware didn't ACK the reset - continue anyway\n");
119 iwl_trans_fw_error(trans, true);
120 }
121
122 trans_pcie->fw_reset_state = FW_RESET_IDLE;
123 }
124
_iwl_trans_pcie_gen2_stop_device(struct iwl_trans * trans)125 void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans)
126 {
127 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
128
129 lockdep_assert_held(&trans_pcie->mutex);
130
131 if (trans_pcie->is_down)
132 return;
133
134 if (trans->state >= IWL_TRANS_FW_STARTED)
135 if (trans_pcie->fw_reset_handshake)
136 iwl_trans_pcie_fw_reset_handshake(trans);
137
138 trans_pcie->is_down = true;
139
140 /* tell the device to stop sending interrupts */
141 iwl_disable_interrupts(trans);
142
143 /* device going down, Stop using ICT table */
144 iwl_pcie_disable_ict(trans);
145
146 /*
147 * If a HW restart happens during firmware loading,
148 * then the firmware loading might call this function
149 * and later it might be called again due to the
150 * restart. So don't process again if the device is
151 * already dead.
152 */
153 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
154 IWL_DEBUG_INFO(trans,
155 "DEVICE_ENABLED bit was set and is now cleared\n");
156 iwl_txq_gen2_tx_free(trans);
157 iwl_pcie_rx_stop(trans);
158 }
159
160 iwl_pcie_ctxt_info_free_paging(trans);
161 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
162 iwl_pcie_ctxt_info_gen3_free(trans, false);
163 else
164 iwl_pcie_ctxt_info_free(trans);
165
166 /* Stop the device, and put it in low power state */
167 iwl_pcie_gen2_apm_stop(trans, false);
168
169 iwl_trans_sw_reset(trans);
170
171 /*
172 * Upon stop, the IVAR table gets erased, so msi-x won't
173 * work. This causes a bug in RF-KILL flows, since the interrupt
174 * that enables radio won't fire on the correct irq, and the
175 * driver won't be able to handle the interrupt.
176 * Configure the IVAR table again after reset.
177 */
178 iwl_pcie_conf_msix_hw(trans_pcie);
179
180 /*
181 * Upon stop, the APM issues an interrupt if HW RF kill is set.
182 * This is a bug in certain verions of the hardware.
183 * Certain devices also keep sending HW RF kill interrupt all
184 * the time, unless the interrupt is ACKed even if the interrupt
185 * should be masked. Re-ACK all the interrupts here.
186 */
187 iwl_disable_interrupts(trans);
188
189 /* clear all status bits */
190 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
191 clear_bit(STATUS_INT_ENABLED, &trans->status);
192 clear_bit(STATUS_TPOWER_PMI, &trans->status);
193
194 /*
195 * Even if we stop the HW, we still want the RF kill
196 * interrupt
197 */
198 iwl_enable_rfkill_int(trans);
199
200 /* re-take ownership to prevent other users from stealing the device */
201 iwl_pcie_prepare_card_hw(trans);
202 }
203
iwl_trans_pcie_gen2_stop_device(struct iwl_trans * trans)204 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans)
205 {
206 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
207 bool was_in_rfkill;
208
209 iwl_op_mode_time_point(trans->op_mode,
210 IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE,
211 NULL);
212
213 mutex_lock(&trans_pcie->mutex);
214 trans_pcie->opmode_down = true;
215 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
216 _iwl_trans_pcie_gen2_stop_device(trans);
217 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
218 mutex_unlock(&trans_pcie->mutex);
219 }
220
iwl_pcie_gen2_nic_init(struct iwl_trans * trans)221 static int iwl_pcie_gen2_nic_init(struct iwl_trans *trans)
222 {
223 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
224 int queue_size = max_t(u32, IWL_CMD_QUEUE_SIZE,
225 trans->cfg->min_txq_size);
226
227 /* TODO: most of the logic can be removed in A0 - but not in Z0 */
228 spin_lock_bh(&trans_pcie->irq_lock);
229 iwl_pcie_gen2_apm_init(trans);
230 spin_unlock_bh(&trans_pcie->irq_lock);
231
232 iwl_op_mode_nic_config(trans->op_mode);
233
234 /* Allocate the RX queue, or reset if it is already allocated */
235 if (iwl_pcie_gen2_rx_init(trans))
236 return -ENOMEM;
237
238 /* Allocate or reset and init all Tx and Command queues */
239 if (iwl_txq_gen2_init(trans, trans->txqs.cmd.q_id, queue_size))
240 return -ENOMEM;
241
242 /* enable shadow regs in HW */
243 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
244 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
245
246 return 0;
247 }
248
iwl_pcie_get_rf_name(struct iwl_trans * trans)249 static void iwl_pcie_get_rf_name(struct iwl_trans *trans)
250 {
251 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
252 char *buf = trans_pcie->rf_name;
253 size_t buflen = sizeof(trans_pcie->rf_name);
254 size_t pos;
255 u32 version;
256
257 if (buf[0])
258 return;
259
260 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) {
261 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_JF):
262 pos = scnprintf(buf, buflen, "JF");
263 break;
264 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_GF):
265 pos = scnprintf(buf, buflen, "GF");
266 break;
267 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_GF4):
268 pos = scnprintf(buf, buflen, "GF4");
269 break;
270 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR):
271 pos = scnprintf(buf, buflen, "HR");
272 break;
273 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1):
274 pos = scnprintf(buf, buflen, "HR1");
275 break;
276 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB):
277 pos = scnprintf(buf, buflen, "HRCDB");
278 break;
279 default:
280 return;
281 }
282
283 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) {
284 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR):
285 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1):
286 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB):
287 version = iwl_read_prph(trans, CNVI_MBOX_C);
288 switch (version) {
289 case 0x20000:
290 pos += scnprintf(buf + pos, buflen - pos, " B3");
291 break;
292 case 0x120000:
293 pos += scnprintf(buf + pos, buflen - pos, " B5");
294 break;
295 default:
296 pos += scnprintf(buf + pos, buflen - pos,
297 " (0x%x)", version);
298 break;
299 }
300 break;
301 default:
302 break;
303 }
304
305 pos += scnprintf(buf + pos, buflen - pos, ", rfid=0x%x",
306 trans->hw_rf_id);
307
308 IWL_INFO(trans, "Detected RF %s\n", buf);
309
310 /*
311 * also add a \n for debugfs - need to do it after printing
312 * since our IWL_INFO machinery wants to see a static \n at
313 * the end of the string
314 */
315 pos += scnprintf(buf + pos, buflen - pos, "\n");
316 }
317
iwl_trans_pcie_gen2_fw_alive(struct iwl_trans * trans,u32 scd_addr)318 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr)
319 {
320 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
321
322 iwl_pcie_reset_ict(trans);
323
324 /* make sure all queue are not stopped/used */
325 memset(trans->txqs.queue_stopped, 0,
326 sizeof(trans->txqs.queue_stopped));
327 memset(trans->txqs.queue_used, 0, sizeof(trans->txqs.queue_used));
328
329 /* now that we got alive we can free the fw image & the context info.
330 * paging memory cannot be freed included since FW will still use it
331 */
332 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
333 iwl_pcie_ctxt_info_gen3_free(trans, true);
334 else
335 iwl_pcie_ctxt_info_free(trans);
336
337 /*
338 * Re-enable all the interrupts, including the RF-Kill one, now that
339 * the firmware is alive.
340 */
341 iwl_enable_interrupts(trans);
342 mutex_lock(&trans_pcie->mutex);
343 iwl_pcie_check_hw_rf_kill(trans);
344
345 iwl_pcie_get_rf_name(trans);
346 mutex_unlock(&trans_pcie->mutex);
347 }
348
iwl_pcie_set_ltr(struct iwl_trans * trans)349 static void iwl_pcie_set_ltr(struct iwl_trans *trans)
350 {
351 u32 ltr_val = CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ |
352 u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
353 CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE) |
354 u32_encode_bits(250,
355 CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL) |
356 CSR_LTR_LONG_VAL_AD_SNOOP_REQ |
357 u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
358 CSR_LTR_LONG_VAL_AD_SNOOP_SCALE) |
359 u32_encode_bits(250, CSR_LTR_LONG_VAL_AD_SNOOP_VAL);
360
361 /*
362 * To workaround hardware latency issues during the boot process,
363 * initialize the LTR to ~250 usec (see ltr_val above).
364 * The firmware initializes this again later (to a smaller value).
365 */
366 if ((trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210 ||
367 trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) &&
368 !trans->trans_cfg->integrated) {
369 iwl_write32(trans, CSR_LTR_LONG_VAL_AD, ltr_val);
370 } else if (trans->trans_cfg->integrated &&
371 trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) {
372 iwl_write_prph(trans, HPM_MAC_LTR_CSR, HPM_MAC_LRT_ENABLE_ALL);
373 iwl_write_prph(trans, HPM_UMAC_LTR, ltr_val);
374 }
375 }
376
iwl_trans_pcie_gen2_start_fw(struct iwl_trans * trans,const struct fw_img * fw,bool run_in_rfkill)377 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
378 const struct fw_img *fw, bool run_in_rfkill)
379 {
380 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
381 bool hw_rfkill;
382 int ret;
383
384 /* This may fail if AMT took ownership of the device */
385 if (iwl_pcie_prepare_card_hw(trans)) {
386 IWL_WARN(trans, "Exit HW not ready\n");
387 ret = -EIO;
388 goto out;
389 }
390
391 iwl_enable_rfkill_int(trans);
392
393 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
394
395 /*
396 * We enabled the RF-Kill interrupt and the handler may very
397 * well be running. Disable the interrupts to make sure no other
398 * interrupt can be fired.
399 */
400 iwl_disable_interrupts(trans);
401
402 /* Make sure it finished running */
403 iwl_pcie_synchronize_irqs(trans);
404
405 mutex_lock(&trans_pcie->mutex);
406
407 /* If platform's RF_KILL switch is NOT set to KILL */
408 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
409 if (hw_rfkill && !run_in_rfkill) {
410 ret = -ERFKILL;
411 goto out;
412 }
413
414 /* Someone called stop_device, don't try to start_fw */
415 if (trans_pcie->is_down) {
416 IWL_WARN(trans,
417 "Can't start_fw since the HW hasn't been started\n");
418 ret = -EIO;
419 goto out;
420 }
421
422 /* make sure rfkill handshake bits are cleared */
423 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
424 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
425 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
426
427 /* clear (again), then enable host interrupts */
428 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
429
430 ret = iwl_pcie_gen2_nic_init(trans);
431 if (ret) {
432 IWL_ERR(trans, "Unable to init nic\n");
433 goto out;
434 }
435
436 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
437 ret = iwl_pcie_ctxt_info_gen3_init(trans, fw);
438 else
439 ret = iwl_pcie_ctxt_info_init(trans, fw);
440 if (ret)
441 goto out;
442
443 iwl_pcie_set_ltr(trans);
444
445 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
446 iwl_write32(trans, CSR_FUNC_SCRATCH, CSR_FUNC_SCRATCH_INIT_VALUE);
447 iwl_set_bit(trans, CSR_GP_CNTRL,
448 CSR_GP_CNTRL_REG_FLAG_ROM_START);
449 } else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
450 iwl_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1);
451 } else {
452 iwl_write_prph(trans, UREG_CPU_INIT_RUN, 1);
453 }
454
455 /* re-check RF-Kill state since we may have missed the interrupt */
456 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
457 if (hw_rfkill && !run_in_rfkill)
458 ret = -ERFKILL;
459
460 out:
461 mutex_unlock(&trans_pcie->mutex);
462 return ret;
463 }
464