1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2019 MediaTek Inc.
3 *
4 * Author: Ryder Lee <ryder.lee@mediatek.com>
5 * Roy Luo <royluo@google.com>
6 * Lorenzo Bianconi <lorenzo@kernel.org>
7 * Felix Fietkau <nbd@nbd.name>
8 */
9
10 #include "mt7615.h"
11 #include "../dma.h"
12 #include "mac.h"
13
14 static int
mt7622_init_tx_queues_multi(struct mt7615_dev * dev)15 mt7622_init_tx_queues_multi(struct mt7615_dev *dev)
16 {
17 static const u8 wmm_queue_map[] = {
18 [IEEE80211_AC_BK] = MT7622_TXQ_AC0,
19 [IEEE80211_AC_BE] = MT7622_TXQ_AC1,
20 [IEEE80211_AC_VI] = MT7622_TXQ_AC2,
21 [IEEE80211_AC_VO] = MT7622_TXQ_AC3,
22 };
23 int ret;
24 int i;
25
26 for (i = 0; i < ARRAY_SIZE(wmm_queue_map); i++) {
27 ret = mt76_init_tx_queue(&dev->mphy, i, wmm_queue_map[i],
28 MT7615_TX_RING_SIZE / 2,
29 MT_TX_RING_BASE);
30 if (ret)
31 return ret;
32 }
33
34 ret = mt76_init_tx_queue(&dev->mphy, MT_TXQ_PSD, MT7622_TXQ_MGMT,
35 MT7615_TX_MGMT_RING_SIZE,
36 MT_TX_RING_BASE);
37 if (ret)
38 return ret;
39
40 return mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7622_TXQ_MCU,
41 MT7615_TX_MCU_RING_SIZE, MT_TX_RING_BASE);
42 }
43
44 static int
mt7615_init_tx_queues(struct mt7615_dev * dev)45 mt7615_init_tx_queues(struct mt7615_dev *dev)
46 {
47 int ret, i;
48
49 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, MT7615_TXQ_FWDL,
50 MT7615_TX_FWDL_RING_SIZE, MT_TX_RING_BASE);
51 if (ret)
52 return ret;
53
54 if (!is_mt7615(&dev->mt76))
55 return mt7622_init_tx_queues_multi(dev);
56
57 ret = mt76_init_tx_queue(&dev->mphy, 0, 0, MT7615_TX_RING_SIZE,
58 MT_TX_RING_BASE);
59 if (ret)
60 return ret;
61
62 for (i = 1; i <= MT_TXQ_PSD ; i++)
63 dev->mphy.q_tx[i] = dev->mphy.q_tx[0];
64
65 return mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7615_TXQ_MCU,
66 MT7615_TX_MCU_RING_SIZE, MT_TX_RING_BASE);
67 }
68
mt7615_poll_tx(struct napi_struct * napi,int budget)69 static int mt7615_poll_tx(struct napi_struct *napi, int budget)
70 {
71 struct mt7615_dev *dev;
72
73 dev = container_of(napi, struct mt7615_dev, mt76.tx_napi);
74 if (!mt76_connac_pm_ref(&dev->mphy, &dev->pm)) {
75 napi_complete(napi);
76 queue_work(dev->mt76.wq, &dev->pm.wake_work);
77 return 0;
78 }
79
80 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], false);
81 if (napi_complete(napi))
82 mt7615_irq_enable(dev, mt7615_tx_mcu_int_mask(dev));
83
84 mt76_connac_pm_unref(&dev->mphy, &dev->pm);
85
86 return 0;
87 }
88
mt7615_poll_rx(struct napi_struct * napi,int budget)89 static int mt7615_poll_rx(struct napi_struct *napi, int budget)
90 {
91 struct mt7615_dev *dev;
92 int done;
93
94 dev = container_of(napi->dev, struct mt7615_dev, mt76.napi_dev);
95
96 if (!mt76_connac_pm_ref(&dev->mphy, &dev->pm)) {
97 napi_complete(napi);
98 queue_work(dev->mt76.wq, &dev->pm.wake_work);
99 return 0;
100 }
101 done = mt76_dma_rx_poll(napi, budget);
102 mt76_connac_pm_unref(&dev->mphy, &dev->pm);
103
104 return done;
105 }
106
mt7615_wait_pdma_busy(struct mt7615_dev * dev)107 int mt7615_wait_pdma_busy(struct mt7615_dev *dev)
108 {
109 struct mt76_dev *mdev = &dev->mt76;
110
111 if (!is_mt7663(mdev)) {
112 u32 mask = MT_PDMA_TX_BUSY | MT_PDMA_RX_BUSY;
113 u32 reg = mt7615_reg_map(dev, MT_PDMA_BUSY);
114
115 if (!mt76_poll_msec(dev, reg, mask, 0, 1000)) {
116 dev_err(mdev->dev, "PDMA engine busy\n");
117 return -EIO;
118 }
119
120 return 0;
121 }
122
123 if (!mt76_poll_msec(dev, MT_PDMA_BUSY_STATUS,
124 MT_PDMA_TX_IDX_BUSY, 0, 1000)) {
125 dev_err(mdev->dev, "PDMA engine tx busy\n");
126 return -EIO;
127 }
128
129 if (!mt76_poll_msec(dev, MT_PSE_PG_INFO,
130 MT_PSE_SRC_CNT, 0, 1000)) {
131 dev_err(mdev->dev, "PSE engine busy\n");
132 return -EIO;
133 }
134
135 if (!mt76_poll_msec(dev, MT_PDMA_BUSY_STATUS,
136 MT_PDMA_BUSY_IDX, 0, 1000)) {
137 dev_err(mdev->dev, "PDMA engine busy\n");
138 return -EIO;
139 }
140
141 return 0;
142 }
143
mt7622_dma_sched_init(struct mt7615_dev * dev)144 static void mt7622_dma_sched_init(struct mt7615_dev *dev)
145 {
146 u32 reg = mt7615_reg_map(dev, MT_DMASHDL_BASE);
147 int i;
148
149 mt76_rmw(dev, reg + MT_DMASHDL_PKT_MAX_SIZE,
150 MT_DMASHDL_PKT_MAX_SIZE_PLE | MT_DMASHDL_PKT_MAX_SIZE_PSE,
151 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PLE, 1) |
152 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PSE, 8));
153
154 for (i = 0; i <= 5; i++)
155 mt76_wr(dev, reg + MT_DMASHDL_GROUP_QUOTA(i),
156 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x10) |
157 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x800));
158
159 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(0), 0x42104210);
160 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(1), 0x42104210);
161 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(2), 0x5);
162 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(3), 0);
163
164 mt76_wr(dev, reg + MT_DMASHDL_SCHED_SET0, 0x6012345f);
165 mt76_wr(dev, reg + MT_DMASHDL_SCHED_SET1, 0xedcba987);
166 }
167
mt7663_dma_sched_init(struct mt7615_dev * dev)168 static void mt7663_dma_sched_init(struct mt7615_dev *dev)
169 {
170 int i;
171
172 mt76_rmw(dev, MT_DMA_SHDL(MT_DMASHDL_PKT_MAX_SIZE),
173 MT_DMASHDL_PKT_MAX_SIZE_PLE | MT_DMASHDL_PKT_MAX_SIZE_PSE,
174 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PLE, 1) |
175 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PSE, 8));
176
177 /* enable refill control group 0, 1, 2, 4, 5 */
178 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_REFILL), 0xffc80000);
179 /* enable group 0, 1, 2, 4, 5, 15 */
180 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_OPTIONAL), 0x70068037);
181
182 /* each group min quota must larger then PLE_PKT_MAX_SIZE_NUM */
183 for (i = 0; i < 5; i++)
184 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(i)),
185 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x40) |
186 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x800));
187 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(5)),
188 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x40) |
189 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x40));
190 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(15)),
191 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x20) |
192 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x20));
193
194 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(0)), 0x42104210);
195 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(1)), 0x42104210);
196 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(2)), 0x00050005);
197 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(3)), 0);
198 /* ALTX0 and ALTX1 QID mapping to group 5 */
199 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_SCHED_SET0), 0x6012345f);
200 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_SCHED_SET1), 0xedcba987);
201 }
202
mt7615_dma_start(struct mt7615_dev * dev)203 void mt7615_dma_start(struct mt7615_dev *dev)
204 {
205 /* start dma engine */
206 mt76_set(dev, MT_WPDMA_GLO_CFG,
207 MT_WPDMA_GLO_CFG_TX_DMA_EN |
208 MT_WPDMA_GLO_CFG_RX_DMA_EN |
209 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
210
211 if (is_mt7622(&dev->mt76))
212 mt7622_dma_sched_init(dev);
213
214 if (is_mt7663(&dev->mt76)) {
215 mt7663_dma_sched_init(dev);
216
217 mt76_wr(dev, MT_MCU2HOST_INT_ENABLE, MT7663_MCU_CMD_ERROR_MASK);
218 }
219
220 }
221
mt7615_dma_init(struct mt7615_dev * dev)222 int mt7615_dma_init(struct mt7615_dev *dev)
223 {
224 int rx_ring_size = MT7615_RX_RING_SIZE;
225 u32 mask;
226 int ret;
227
228 mt76_dma_attach(&dev->mt76);
229
230 mt76_wr(dev, MT_WPDMA_GLO_CFG,
231 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE |
232 MT_WPDMA_GLO_CFG_FIFO_LITTLE_ENDIAN |
233 MT_WPDMA_GLO_CFG_OMIT_TX_INFO);
234
235 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
236 MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT0, 0x1);
237
238 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
239 MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT21, 0x1);
240
241 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
242 MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 0x3);
243
244 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
245 MT_WPDMA_GLO_CFG_MULTI_DMA_EN, 0x3);
246
247 if (is_mt7615(&dev->mt76)) {
248 mt76_set(dev, MT_WPDMA_GLO_CFG,
249 MT_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY);
250
251 mt76_wr(dev, MT_WPDMA_GLO_CFG1, 0x1);
252 mt76_wr(dev, MT_WPDMA_TX_PRE_CFG, 0xf0000);
253 mt76_wr(dev, MT_WPDMA_RX_PRE_CFG, 0xf7f0000);
254 mt76_wr(dev, MT_WPDMA_ABT_CFG, 0x4000026);
255 mt76_wr(dev, MT_WPDMA_ABT_CFG1, 0x18811881);
256 mt76_set(dev, 0x7158, BIT(16));
257 mt76_clear(dev, 0x7000, BIT(23));
258 }
259
260 mt76_wr(dev, MT_WPDMA_RST_IDX, ~0);
261
262 ret = mt7615_init_tx_queues(dev);
263 if (ret)
264 return ret;
265
266 /* init rx queues */
267 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 1,
268 MT7615_RX_MCU_RING_SIZE, MT_RX_BUF_SIZE,
269 MT_RX_RING_BASE);
270 if (ret)
271 return ret;
272
273 if (!is_mt7615(&dev->mt76))
274 rx_ring_size /= 2;
275
276 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], 0,
277 rx_ring_size, MT_RX_BUF_SIZE, MT_RX_RING_BASE);
278 if (ret)
279 return ret;
280
281 mt76_wr(dev, MT_DELAY_INT_CFG, 0);
282
283 ret = mt76_init_queues(dev, mt7615_poll_rx);
284 if (ret < 0)
285 return ret;
286
287 netif_tx_napi_add(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi,
288 mt7615_poll_tx, NAPI_POLL_WEIGHT);
289 napi_enable(&dev->mt76.tx_napi);
290
291 mt76_poll(dev, MT_WPDMA_GLO_CFG,
292 MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
293 MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 1000);
294
295 /* enable interrupts for TX/RX rings */
296
297 mask = MT_INT_RX_DONE_ALL | mt7615_tx_mcu_int_mask(dev);
298 if (is_mt7663(&dev->mt76))
299 mask |= MT7663_INT_MCU_CMD;
300 else
301 mask |= MT_INT_MCU_CMD;
302
303 mt7615_irq_enable(dev, mask);
304
305 mt7615_dma_start(dev);
306
307 return 0;
308 }
309
mt7615_dma_cleanup(struct mt7615_dev * dev)310 void mt7615_dma_cleanup(struct mt7615_dev *dev)
311 {
312 mt76_clear(dev, MT_WPDMA_GLO_CFG,
313 MT_WPDMA_GLO_CFG_TX_DMA_EN |
314 MT_WPDMA_GLO_CFG_RX_DMA_EN);
315 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_SW_RESET);
316
317 mt76_dma_cleanup(&dev->mt76);
318 }
319