1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * This file is part of wl1251
4  *
5  * Copyright (c) 1998-2007 Texas Instruments Incorporated
6  * Copyright (C) 2008 Nokia Corporation
7  */
8 
9 #ifndef __WL1251_TX_H__
10 #define __WL1251_TX_H__
11 
12 #include <linux/bitops.h>
13 #include "acx.h"
14 
15 /*
16  *
17  * TX PATH
18  *
19  * The Tx path uses a double buffer and a tx_control structure, each located
20  * at a fixed address in the device's memory. On startup, the host retrieves
21  * the pointers to these addresses. A double buffer allows for continuous data
22  * flow towards the device. The host keeps track of which buffer is available
23  * and alternates between these two buffers on a per packet basis.
24  *
25  * The size of each of the two buffers is large enough to hold the longest
26  * 802.3 packet - maximum size Ethernet packet + header + descriptor.
27  * TX complete indication will be received a-synchronously in a TX done cyclic
28  * buffer which is composed of 16 tx_result descriptors structures and is used
29  * in a cyclic manner.
30  *
31  * The TX (HOST) procedure is as follows:
32  * 1. Read the Tx path status, that will give the data_out_count.
33  * 2. goto 1, if not possible.
34  *    i.e. if data_in_count - data_out_count >= HwBuffer size (2 for double
35  *    buffer).
36  * 3. Copy the packet (preceded by double_buffer_desc), if possible.
37  *    i.e. if data_in_count - data_out_count < HwBuffer size (2 for double
38  *    buffer).
39  * 4. increment data_in_count.
40  * 5. Inform the firmware by generating a firmware internal interrupt.
41  * 6. FW will increment data_out_count after it reads the buffer.
42  *
43  * The TX Complete procedure:
44  * 1. To get a TX complete indication the host enables the tx_complete flag in
45  *    the TX descriptor Structure.
46  * 2. For each packet with a Tx Complete field set, the firmware adds the
47  *    transmit results to the cyclic buffer (txDoneRing) and sets both done_1
48  *    and done_2 to 1 to indicate driver ownership.
49  * 3. The firmware sends a Tx Complete interrupt to the host to trigger the
50  *    host to process the new data. Note: interrupt will be send per packet if
51  *    TX complete indication was requested in tx_control or per crossing
52  *    aggregation threshold.
53  * 4. After receiving the Tx Complete interrupt, the host reads the
54  *    TxDescriptorDone information in a cyclic manner and clears both done_1
55  *    and done_2 fields.
56  *
57  */
58 
59 #define TX_COMPLETE_REQUIRED_BIT	0x80
60 #define TX_STATUS_DATA_OUT_COUNT_MASK   0xf
61 
62 #define WL1251_TX_ALIGN_TO 4
63 #define WL1251_TX_ALIGN(len) (((len) + WL1251_TX_ALIGN_TO - 1) & \
64 			     ~(WL1251_TX_ALIGN_TO - 1))
65 #define WL1251_TKIP_IV_SPACE 4
66 
67 struct tx_control {
68 	/* Rate Policy (class) index */
69 	unsigned rate_policy:3;
70 
71 	/* When set, no ack policy is expected */
72 	unsigned ack_policy:1;
73 
74 	/*
75 	 * Packet type:
76 	 * 0 -> 802.11
77 	 * 1 -> 802.3
78 	 * 2 -> IP
79 	 * 3 -> raw codec
80 	 */
81 	unsigned packet_type:2;
82 
83 	/* If set, this is a QoS-Null or QoS-Data frame */
84 	unsigned qos:1;
85 
86 	/*
87 	 * If set, the target triggers the tx complete INT
88 	 * upon frame sending completion.
89 	 */
90 	unsigned tx_complete:1;
91 
92 	/* 2 bytes padding before packet header */
93 	unsigned xfer_pad:1;
94 
95 	unsigned reserved:7;
96 } __packed;
97 
98 
99 struct tx_double_buffer_desc {
100 	/* Length of payload, including headers. */
101 	__le16 length;
102 
103 	/*
104 	 * A bit mask that specifies the initial rate to be used
105 	 * Possible values are:
106 	 * 0x0001 - 1Mbits
107 	 * 0x0002 - 2Mbits
108 	 * 0x0004 - 5.5Mbits
109 	 * 0x0008 - 6Mbits
110 	 * 0x0010 - 9Mbits
111 	 * 0x0020 - 11Mbits
112 	 * 0x0040 - 12Mbits
113 	 * 0x0080 - 18Mbits
114 	 * 0x0100 - 22Mbits
115 	 * 0x0200 - 24Mbits
116 	 * 0x0400 - 36Mbits
117 	 * 0x0800 - 48Mbits
118 	 * 0x1000 - 54Mbits
119 	 */
120 	__le16 rate;
121 
122 	/* Time in us that a packet can spend in the target */
123 	__le32 expiry_time;
124 
125 	/* index of the TX queue used for this packet */
126 	u8 xmit_queue;
127 
128 	/* Used to identify a packet */
129 	u8 id;
130 
131 	struct tx_control control;
132 
133 	/*
134 	 * The FW should cut the packet into fragments
135 	 * of this size.
136 	 */
137 	__le16 frag_threshold;
138 
139 	/* Numbers of HW queue blocks to be allocated */
140 	u8 num_mem_blocks;
141 
142 	u8 reserved;
143 } __packed;
144 
145 enum {
146 	TX_SUCCESS              = 0,
147 	TX_DMA_ERROR            = BIT(7),
148 	TX_DISABLED             = BIT(6),
149 	TX_RETRY_EXCEEDED       = BIT(5),
150 	TX_TIMEOUT              = BIT(4),
151 	TX_KEY_NOT_FOUND        = BIT(3),
152 	TX_ENCRYPT_FAIL         = BIT(2),
153 	TX_UNAVAILABLE_PRIORITY = BIT(1),
154 };
155 
156 struct tx_result {
157 	/*
158 	 * Ownership synchronization between the host and
159 	 * the firmware. If done_1 and done_2 are cleared,
160 	 * owned by the FW (no info ready).
161 	 */
162 	u8 done_1;
163 
164 	/* same as double_buffer_desc->id */
165 	u8 id;
166 
167 	/*
168 	 * Total air access duration consumed by this
169 	 * packet, including all retries and overheads.
170 	 */
171 	u16 medium_usage;
172 
173 	/* Total media delay (from 1st EDCA AIFS counter until TX Complete). */
174 	u32 medium_delay;
175 
176 	/* Time between host xfer and tx complete */
177 	u32 fw_hnadling_time;
178 
179 	/* The LS-byte of the last TKIP sequence number. */
180 	u8 lsb_seq_num;
181 
182 	/* Retry count */
183 	u8 ack_failures;
184 
185 	/* At which rate we got a ACK */
186 	u16 rate;
187 
188 	u16 reserved;
189 
190 	/* TX_* */
191 	u8 status;
192 
193 	/* See done_1 */
194 	u8 done_2;
195 } __packed;
196 
wl1251_tx_get_queue(int queue)197 static inline int wl1251_tx_get_queue(int queue)
198 {
199 	switch (queue) {
200 	case 0:
201 		return QOS_AC_VO;
202 	case 1:
203 		return QOS_AC_VI;
204 	case 2:
205 		return QOS_AC_BE;
206 	case 3:
207 		return QOS_AC_BK;
208 	default:
209 		return QOS_AC_BE;
210 	}
211 }
212 
213 void wl1251_tx_work(struct work_struct *work);
214 void wl1251_tx_complete(struct wl1251 *wl);
215 void wl1251_tx_flush(struct wl1251 *wl);
216 
217 #endif
218