1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * BRIEF MODULE DESCRIPTION
4 * PCI init for Ralink RT2880 solution
5 *
6 * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
7 *
8 * May 2007 Bruce Chang
9 * Initial Release
10 *
11 * May 2009 Bruce Chang
12 * support RT2880/RT3883 PCIe
13 *
14 * May 2011 Bruce Chang
15 * support RT6855/MT7620 PCIe
16 */
17
18 #include <linux/bitops.h>
19 #include <linux/clk.h>
20 #include <linux/delay.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/module.h>
23 #include <linux/of.h>
24 #include <linux/of_address.h>
25 #include <linux/of_pci.h>
26 #include <linux/of_platform.h>
27 #include <linux/pci.h>
28 #include <linux/phy/phy.h>
29 #include <linux/platform_device.h>
30 #include <linux/reset.h>
31 #include <linux/sys_soc.h>
32
33 /* MediaTek-specific configuration registers */
34 #define PCIE_FTS_NUM 0x70c
35 #define PCIE_FTS_NUM_MASK GENMASK(15, 8)
36 #define PCIE_FTS_NUM_L0(x) (((x) & 0xff) << 8)
37
38 /* Host-PCI bridge registers */
39 #define RALINK_PCI_PCICFG_ADDR 0x0000
40 #define RALINK_PCI_PCIMSK_ADDR 0x000c
41 #define RALINK_PCI_CONFIG_ADDR 0x0020
42 #define RALINK_PCI_CONFIG_DATA 0x0024
43 #define RALINK_PCI_MEMBASE 0x0028
44 #define RALINK_PCI_IOBASE 0x002c
45
46 /* PCIe RC control registers */
47 #define RALINK_PCI_ID 0x0030
48 #define RALINK_PCI_CLASS 0x0034
49 #define RALINK_PCI_SUBID 0x0038
50 #define RALINK_PCI_STATUS 0x0050
51
52 /* Some definition values */
53 #define PCIE_REVISION_ID BIT(0)
54 #define PCIE_CLASS_CODE (0x60400 << 8)
55 #define PCIE_BAR_MAP_MAX GENMASK(30, 16)
56 #define PCIE_BAR_ENABLE BIT(0)
57 #define PCIE_PORT_INT_EN(x) BIT(20 + (x))
58 #define PCIE_PORT_LINKUP BIT(0)
59 #define PCIE_PORT_CNT 3
60
61 #define PERST_DELAY_MS 100
62
63 /**
64 * struct mt7621_pcie_port - PCIe port information
65 * @base: I/O mapped register base
66 * @list: port list
67 * @pcie: pointer to PCIe host info
68 * @clk: pointer to the port clock gate
69 * @phy: pointer to PHY control block
70 * @pcie_rst: pointer to port reset control
71 * @gpio_rst: gpio reset
72 * @slot: port slot
73 * @enabled: indicates if port is enabled
74 */
75 struct mt7621_pcie_port {
76 void __iomem *base;
77 struct list_head list;
78 struct mt7621_pcie *pcie;
79 struct clk *clk;
80 struct phy *phy;
81 struct reset_control *pcie_rst;
82 struct gpio_desc *gpio_rst;
83 u32 slot;
84 bool enabled;
85 };
86
87 /**
88 * struct mt7621_pcie - PCIe host information
89 * @base: IO Mapped Register Base
90 * @dev: Pointer to PCIe device
91 * @ports: pointer to PCIe port information
92 * @resets_inverted: depends on chip revision
93 * reset lines are inverted.
94 */
95 struct mt7621_pcie {
96 void __iomem *base;
97 struct device *dev;
98 struct list_head ports;
99 bool resets_inverted;
100 };
101
pcie_read(struct mt7621_pcie * pcie,u32 reg)102 static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg)
103 {
104 return readl_relaxed(pcie->base + reg);
105 }
106
pcie_write(struct mt7621_pcie * pcie,u32 val,u32 reg)107 static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg)
108 {
109 writel_relaxed(val, pcie->base + reg);
110 }
111
pcie_rmw(struct mt7621_pcie * pcie,u32 reg,u32 clr,u32 set)112 static inline void pcie_rmw(struct mt7621_pcie *pcie, u32 reg, u32 clr, u32 set)
113 {
114 u32 val = readl_relaxed(pcie->base + reg);
115
116 val &= ~clr;
117 val |= set;
118 writel_relaxed(val, pcie->base + reg);
119 }
120
pcie_port_read(struct mt7621_pcie_port * port,u32 reg)121 static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg)
122 {
123 return readl_relaxed(port->base + reg);
124 }
125
pcie_port_write(struct mt7621_pcie_port * port,u32 val,u32 reg)126 static inline void pcie_port_write(struct mt7621_pcie_port *port,
127 u32 val, u32 reg)
128 {
129 writel_relaxed(val, port->base + reg);
130 }
131
mt7621_pci_get_cfgaddr(unsigned int bus,unsigned int slot,unsigned int func,unsigned int where)132 static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
133 unsigned int func, unsigned int where)
134 {
135 return (((where & 0xf00) >> 8) << 24) | (bus << 16) | (slot << 11) |
136 (func << 8) | (where & 0xfc) | 0x80000000;
137 }
138
mt7621_pcie_map_bus(struct pci_bus * bus,unsigned int devfn,int where)139 static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,
140 unsigned int devfn, int where)
141 {
142 struct mt7621_pcie *pcie = bus->sysdata;
143 u32 address = mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
144 PCI_FUNC(devfn), where);
145
146 writel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
147
148 return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);
149 }
150
151 struct pci_ops mt7621_pci_ops = {
152 .map_bus = mt7621_pcie_map_bus,
153 .read = pci_generic_config_read,
154 .write = pci_generic_config_write,
155 };
156
read_config(struct mt7621_pcie * pcie,unsigned int dev,u32 reg)157 static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
158 {
159 u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
160
161 pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
162 return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);
163 }
164
write_config(struct mt7621_pcie * pcie,unsigned int dev,u32 reg,u32 val)165 static void write_config(struct mt7621_pcie *pcie, unsigned int dev,
166 u32 reg, u32 val)
167 {
168 u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
169
170 pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
171 pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
172 }
173
mt7621_rst_gpio_pcie_assert(struct mt7621_pcie_port * port)174 static inline void mt7621_rst_gpio_pcie_assert(struct mt7621_pcie_port *port)
175 {
176 if (port->gpio_rst)
177 gpiod_set_value(port->gpio_rst, 1);
178 }
179
mt7621_rst_gpio_pcie_deassert(struct mt7621_pcie_port * port)180 static inline void mt7621_rst_gpio_pcie_deassert(struct mt7621_pcie_port *port)
181 {
182 if (port->gpio_rst)
183 gpiod_set_value(port->gpio_rst, 0);
184 }
185
mt7621_pcie_port_is_linkup(struct mt7621_pcie_port * port)186 static inline bool mt7621_pcie_port_is_linkup(struct mt7621_pcie_port *port)
187 {
188 return (pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) != 0;
189 }
190
mt7621_control_assert(struct mt7621_pcie_port * port)191 static inline void mt7621_control_assert(struct mt7621_pcie_port *port)
192 {
193 struct mt7621_pcie *pcie = port->pcie;
194
195 if (pcie->resets_inverted)
196 reset_control_assert(port->pcie_rst);
197 else
198 reset_control_deassert(port->pcie_rst);
199 }
200
mt7621_control_deassert(struct mt7621_pcie_port * port)201 static inline void mt7621_control_deassert(struct mt7621_pcie_port *port)
202 {
203 struct mt7621_pcie *pcie = port->pcie;
204
205 if (pcie->resets_inverted)
206 reset_control_deassert(port->pcie_rst);
207 else
208 reset_control_assert(port->pcie_rst);
209 }
210
setup_cm_memory_region(struct pci_host_bridge * host)211 static int setup_cm_memory_region(struct pci_host_bridge *host)
212 {
213 struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
214 struct device *dev = pcie->dev;
215 struct resource_entry *entry;
216 resource_size_t mask;
217
218 entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
219 if (!entry) {
220 dev_err(dev, "cannot get memory resource\n");
221 return -EINVAL;
222 }
223
224 if (mips_cps_numiocu(0)) {
225 /*
226 * FIXME: hardware doesn't accept mask values with 1s after
227 * 0s (e.g. 0xffef), so it would be great to warn if that's
228 * about to happen
229 */
230 mask = ~(entry->res->end - entry->res->start);
231
232 write_gcr_reg1_base(entry->res->start);
233 write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
234 dev_info(dev, "PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
235 (unsigned long long)read_gcr_reg1_base(),
236 (unsigned long long)read_gcr_reg1_mask());
237 }
238
239 return 0;
240 }
241
mt7621_pcie_parse_port(struct mt7621_pcie * pcie,struct device_node * node,int slot)242 static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
243 struct device_node *node,
244 int slot)
245 {
246 struct mt7621_pcie_port *port;
247 struct device *dev = pcie->dev;
248 struct platform_device *pdev = to_platform_device(dev);
249 char name[10];
250 int err;
251
252 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
253 if (!port)
254 return -ENOMEM;
255
256 port->base = devm_platform_ioremap_resource(pdev, slot + 1);
257 if (IS_ERR(port->base))
258 return PTR_ERR(port->base);
259
260 port->clk = devm_get_clk_from_child(dev, node, NULL);
261 if (IS_ERR(port->clk)) {
262 dev_err(dev, "failed to get pcie%d clock\n", slot);
263 return PTR_ERR(port->clk);
264 }
265
266 port->pcie_rst = of_reset_control_get_exclusive(node, NULL);
267 if (PTR_ERR(port->pcie_rst) == -EPROBE_DEFER) {
268 dev_err(dev, "failed to get pcie%d reset control\n", slot);
269 return PTR_ERR(port->pcie_rst);
270 }
271
272 snprintf(name, sizeof(name), "pcie-phy%d", slot);
273 port->phy = devm_of_phy_get(dev, node, name);
274 if (IS_ERR(port->phy)) {
275 dev_err(dev, "failed to get pcie-phy%d\n", slot);
276 err = PTR_ERR(port->phy);
277 goto remove_reset;
278 }
279
280 port->gpio_rst = devm_gpiod_get_index_optional(dev, "reset", slot,
281 GPIOD_OUT_LOW);
282 if (IS_ERR(port->gpio_rst)) {
283 dev_err(dev, "failed to get GPIO for PCIe%d\n", slot);
284 err = PTR_ERR(port->gpio_rst);
285 goto remove_reset;
286 }
287
288 port->slot = slot;
289 port->pcie = pcie;
290
291 INIT_LIST_HEAD(&port->list);
292 list_add_tail(&port->list, &pcie->ports);
293
294 return 0;
295
296 remove_reset:
297 reset_control_put(port->pcie_rst);
298 return err;
299 }
300
mt7621_pcie_parse_dt(struct mt7621_pcie * pcie)301 static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
302 {
303 struct device *dev = pcie->dev;
304 struct platform_device *pdev = to_platform_device(dev);
305 struct device_node *node = dev->of_node, *child;
306 int err;
307
308 pcie->base = devm_platform_ioremap_resource(pdev, 0);
309 if (IS_ERR(pcie->base))
310 return PTR_ERR(pcie->base);
311
312 for_each_available_child_of_node(node, child) {
313 int slot;
314
315 err = of_pci_get_devfn(child);
316 if (err < 0) {
317 of_node_put(child);
318 dev_err(dev, "failed to parse devfn: %d\n", err);
319 return err;
320 }
321
322 slot = PCI_SLOT(err);
323
324 err = mt7621_pcie_parse_port(pcie, child, slot);
325 if (err) {
326 of_node_put(child);
327 return err;
328 }
329 }
330
331 return 0;
332 }
333
mt7621_pcie_init_port(struct mt7621_pcie_port * port)334 static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
335 {
336 struct mt7621_pcie *pcie = port->pcie;
337 struct device *dev = pcie->dev;
338 u32 slot = port->slot;
339 int err;
340
341 err = phy_init(port->phy);
342 if (err) {
343 dev_err(dev, "failed to initialize port%d phy\n", slot);
344 return err;
345 }
346
347 err = phy_power_on(port->phy);
348 if (err) {
349 dev_err(dev, "failed to power on port%d phy\n", slot);
350 phy_exit(port->phy);
351 return err;
352 }
353
354 port->enabled = true;
355
356 return 0;
357 }
358
mt7621_pcie_reset_assert(struct mt7621_pcie * pcie)359 static void mt7621_pcie_reset_assert(struct mt7621_pcie *pcie)
360 {
361 struct mt7621_pcie_port *port;
362
363 list_for_each_entry(port, &pcie->ports, list) {
364 /* PCIe RC reset assert */
365 mt7621_control_assert(port);
366
367 /* PCIe EP reset assert */
368 mt7621_rst_gpio_pcie_assert(port);
369 }
370
371 msleep(PERST_DELAY_MS);
372 }
373
mt7621_pcie_reset_rc_deassert(struct mt7621_pcie * pcie)374 static void mt7621_pcie_reset_rc_deassert(struct mt7621_pcie *pcie)
375 {
376 struct mt7621_pcie_port *port;
377
378 list_for_each_entry(port, &pcie->ports, list)
379 mt7621_control_deassert(port);
380 }
381
mt7621_pcie_reset_ep_deassert(struct mt7621_pcie * pcie)382 static void mt7621_pcie_reset_ep_deassert(struct mt7621_pcie *pcie)
383 {
384 struct mt7621_pcie_port *port;
385
386 list_for_each_entry(port, &pcie->ports, list)
387 mt7621_rst_gpio_pcie_deassert(port);
388
389 msleep(PERST_DELAY_MS);
390 }
391
mt7621_pcie_init_ports(struct mt7621_pcie * pcie)392 static int mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
393 {
394 struct device *dev = pcie->dev;
395 struct mt7621_pcie_port *port, *tmp;
396 u8 num_disabled = 0;
397 int err;
398
399 mt7621_pcie_reset_assert(pcie);
400 mt7621_pcie_reset_rc_deassert(pcie);
401
402 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
403 u32 slot = port->slot;
404
405 if (slot == 1) {
406 port->enabled = true;
407 continue;
408 }
409
410 err = mt7621_pcie_init_port(port);
411 if (err) {
412 dev_err(dev, "initializing port %d failed\n", slot);
413 list_del(&port->list);
414 }
415 }
416
417 mt7621_pcie_reset_ep_deassert(pcie);
418
419 tmp = NULL;
420 list_for_each_entry(port, &pcie->ports, list) {
421 u32 slot = port->slot;
422
423 if (!mt7621_pcie_port_is_linkup(port)) {
424 dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n",
425 slot);
426 mt7621_control_assert(port);
427 port->enabled = false;
428 num_disabled++;
429
430 if (slot == 0) {
431 tmp = port;
432 continue;
433 }
434
435 if (slot == 1 && tmp && !tmp->enabled)
436 phy_power_off(tmp->phy);
437 }
438 }
439
440 return (num_disabled != PCIE_PORT_CNT) ? 0 : -ENODEV;
441 }
442
mt7621_pcie_enable_port(struct mt7621_pcie_port * port)443 static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
444 {
445 struct mt7621_pcie *pcie = port->pcie;
446 u32 slot = port->slot;
447 u32 val;
448
449 /* enable pcie interrupt */
450 val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
451 val |= PCIE_PORT_INT_EN(slot);
452 pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
453
454 /* map 2G DDR region */
455 pcie_port_write(port, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
456 PCI_BASE_ADDRESS_0);
457
458 /* configure class code and revision ID */
459 pcie_port_write(port, PCIE_CLASS_CODE | PCIE_REVISION_ID,
460 RALINK_PCI_CLASS);
461
462 /* configure RC FTS number to 250 when it leaves L0s */
463 val = read_config(pcie, slot, PCIE_FTS_NUM);
464 val &= ~PCIE_FTS_NUM_MASK;
465 val |= PCIE_FTS_NUM_L0(0x50);
466 write_config(pcie, slot, PCIE_FTS_NUM, val);
467 }
468
mt7621_pcie_enable_ports(struct pci_host_bridge * host)469 static int mt7621_pcie_enable_ports(struct pci_host_bridge *host)
470 {
471 struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
472 struct device *dev = pcie->dev;
473 struct mt7621_pcie_port *port;
474 struct resource_entry *entry;
475 int err;
476
477 entry = resource_list_first_type(&host->windows, IORESOURCE_IO);
478 if (!entry) {
479 dev_err(dev, "cannot get io resource\n");
480 return -EINVAL;
481 }
482
483 /* Setup MEMWIN and IOWIN */
484 pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
485 pcie_write(pcie, entry->res->start - entry->offset, RALINK_PCI_IOBASE);
486
487 list_for_each_entry(port, &pcie->ports, list) {
488 if (port->enabled) {
489 err = clk_prepare_enable(port->clk);
490 if (err) {
491 dev_err(dev, "enabling clk pcie%d\n",
492 port->slot);
493 return err;
494 }
495
496 mt7621_pcie_enable_port(port);
497 dev_info(dev, "PCIE%d enabled\n", port->slot);
498 }
499 }
500
501 return 0;
502 }
503
mt7621_pcie_register_host(struct pci_host_bridge * host)504 static int mt7621_pcie_register_host(struct pci_host_bridge *host)
505 {
506 struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
507
508 host->ops = &mt7621_pci_ops;
509 host->sysdata = pcie;
510 return pci_host_probe(host);
511 }
512
513 static const struct soc_device_attribute mt7621_pci_quirks_match[] = {
514 { .soc_id = "mt7621", .revision = "E2" }
515 };
516
mt7621_pci_probe(struct platform_device * pdev)517 static int mt7621_pci_probe(struct platform_device *pdev)
518 {
519 struct device *dev = &pdev->dev;
520 const struct soc_device_attribute *attr;
521 struct mt7621_pcie_port *port;
522 struct mt7621_pcie *pcie;
523 struct pci_host_bridge *bridge;
524 int err;
525
526 if (!dev->of_node)
527 return -ENODEV;
528
529 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
530 if (!bridge)
531 return -ENOMEM;
532
533 pcie = pci_host_bridge_priv(bridge);
534 pcie->dev = dev;
535 platform_set_drvdata(pdev, pcie);
536 INIT_LIST_HEAD(&pcie->ports);
537
538 attr = soc_device_match(mt7621_pci_quirks_match);
539 if (attr)
540 pcie->resets_inverted = true;
541
542 err = mt7621_pcie_parse_dt(pcie);
543 if (err) {
544 dev_err(dev, "parsing DT failed\n");
545 return err;
546 }
547
548 err = mt7621_pcie_init_ports(pcie);
549 if (err) {
550 dev_err(dev, "nothing connected in virtual bridges\n");
551 return 0;
552 }
553
554 err = mt7621_pcie_enable_ports(bridge);
555 if (err) {
556 dev_err(dev, "error enabling pcie ports\n");
557 goto remove_resets;
558 }
559
560 err = setup_cm_memory_region(bridge);
561 if (err) {
562 dev_err(dev, "error setting up iocu mem regions\n");
563 goto remove_resets;
564 }
565
566 return mt7621_pcie_register_host(bridge);
567
568 remove_resets:
569 list_for_each_entry(port, &pcie->ports, list)
570 reset_control_put(port->pcie_rst);
571
572 return err;
573 }
574
mt7621_pci_remove(struct platform_device * pdev)575 static int mt7621_pci_remove(struct platform_device *pdev)
576 {
577 struct mt7621_pcie *pcie = platform_get_drvdata(pdev);
578 struct mt7621_pcie_port *port;
579
580 list_for_each_entry(port, &pcie->ports, list)
581 reset_control_put(port->pcie_rst);
582
583 return 0;
584 }
585
586 static const struct of_device_id mt7621_pci_ids[] = {
587 { .compatible = "mediatek,mt7621-pci" },
588 {},
589 };
590 MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
591
592 static struct platform_driver mt7621_pci_driver = {
593 .probe = mt7621_pci_probe,
594 .remove = mt7621_pci_remove,
595 .driver = {
596 .name = "mt7621-pci",
597 .of_match_table = of_match_ptr(mt7621_pci_ids),
598 },
599 };
600 builtin_platform_driver(mt7621_pci_driver);
601