1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2021, The Linux Foundation. All rights reserved.
4  * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
5  */
6 
7 #include <linux/module.h>
8 #include <linux/of.h>
9 #include <linux/platform_device.h>
10 #include <linux/pinctrl/pinctrl.h>
11 
12 #include "pinctrl-msm.h"
13 
14 #define FUNCTION(fname)			                \
15 	[msm_mux_##fname] = {		                \
16 		.name = #fname,				\
17 		.groups = fname##_groups,               \
18 		.ngroups = ARRAY_SIZE(fname##_groups),	\
19 	}
20 
21 #define REG_SIZE 0x1000
22 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9)	\
23 	{					        \
24 		.name = "gpio" #id,			\
25 		.pins = gpio##id##_pins,		\
26 		.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins),	\
27 		.funcs = (int[]){			\
28 			msm_mux_gpio, /* gpio mode */	\
29 			msm_mux_##f1,			\
30 			msm_mux_##f2,			\
31 			msm_mux_##f3,			\
32 			msm_mux_##f4,			\
33 			msm_mux_##f5,			\
34 			msm_mux_##f6,			\
35 			msm_mux_##f7,			\
36 			msm_mux_##f8,			\
37 			msm_mux_##f9			\
38 		},				        \
39 		.nfuncs = 10,				\
40 		.ctl_reg = REG_SIZE * id,			\
41 		.io_reg = 0x4 + REG_SIZE * id,		\
42 		.intr_cfg_reg = 0x8 + REG_SIZE * id,		\
43 		.intr_status_reg = 0xc + REG_SIZE * id,	\
44 		.intr_target_reg = 0x8 + REG_SIZE * id,	\
45 		.mux_bit = 2,			\
46 		.pull_bit = 0,			\
47 		.drv_bit = 6,			\
48 		.oe_bit = 9,			\
49 		.in_bit = 0,			\
50 		.out_bit = 1,			\
51 		.intr_enable_bit = 0,		\
52 		.intr_status_bit = 0,		\
53 		.intr_target_bit = 5,		\
54 		.intr_target_kpss_val = 3,	\
55 		.intr_raw_status_bit = 4,	\
56 		.intr_polarity_bit = 1,		\
57 		.intr_detection_bit = 2,	\
58 		.intr_detection_width = 2,	\
59 	}
60 
61 #define SDC_PINGROUP(pg_name, ctl, pull, drv)	\
62 	{					        \
63 		.name = #pg_name,			\
64 		.pins = pg_name##_pins,			\
65 		.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins),	\
66 		.ctl_reg = ctl,				\
67 		.io_reg = 0,				\
68 		.intr_cfg_reg = 0,			\
69 		.intr_status_reg = 0,			\
70 		.intr_target_reg = 0,			\
71 		.mux_bit = -1,				\
72 		.pull_bit = pull,			\
73 		.drv_bit = drv,				\
74 		.oe_bit = -1,				\
75 		.in_bit = -1,				\
76 		.out_bit = -1,				\
77 		.intr_enable_bit = -1,			\
78 		.intr_status_bit = -1,			\
79 		.intr_target_bit = -1,			\
80 		.intr_raw_status_bit = -1,		\
81 		.intr_polarity_bit = -1,		\
82 		.intr_detection_bit = -1,		\
83 		.intr_detection_width = -1,		\
84 	}
85 
86 #define UFS_RESET(pg_name, offset)				\
87 	{					        \
88 		.name = #pg_name,			\
89 		.pins = pg_name##_pins,			\
90 		.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins),	\
91 		.ctl_reg = offset,			\
92 		.io_reg = offset + 0x4,			\
93 		.intr_cfg_reg = 0,			\
94 		.intr_status_reg = 0,			\
95 		.intr_target_reg = 0,			\
96 		.mux_bit = -1,				\
97 		.pull_bit = 3,				\
98 		.drv_bit = 0,				\
99 		.oe_bit = -1,				\
100 		.in_bit = -1,				\
101 		.out_bit = 0,				\
102 		.intr_enable_bit = -1,			\
103 		.intr_status_bit = -1,			\
104 		.intr_target_bit = -1,			\
105 		.intr_raw_status_bit = -1,		\
106 		.intr_polarity_bit = -1,		\
107 		.intr_detection_bit = -1,		\
108 		.intr_detection_width = -1,		\
109 	}
110 static const struct pinctrl_pin_desc sm6350_pins[] = {
111 	PINCTRL_PIN(0, "GPIO_0"),
112 	PINCTRL_PIN(1, "GPIO_1"),
113 	PINCTRL_PIN(2, "GPIO_2"),
114 	PINCTRL_PIN(3, "GPIO_3"),
115 	PINCTRL_PIN(4, "GPIO_4"),
116 	PINCTRL_PIN(5, "GPIO_5"),
117 	PINCTRL_PIN(6, "GPIO_6"),
118 	PINCTRL_PIN(7, "GPIO_7"),
119 	PINCTRL_PIN(8, "GPIO_8"),
120 	PINCTRL_PIN(9, "GPIO_9"),
121 	PINCTRL_PIN(10, "GPIO_10"),
122 	PINCTRL_PIN(11, "GPIO_11"),
123 	PINCTRL_PIN(12, "GPIO_12"),
124 	PINCTRL_PIN(13, "GPIO_13"),
125 	PINCTRL_PIN(14, "GPIO_14"),
126 	PINCTRL_PIN(15, "GPIO_15"),
127 	PINCTRL_PIN(16, "GPIO_16"),
128 	PINCTRL_PIN(17, "GPIO_17"),
129 	PINCTRL_PIN(18, "GPIO_18"),
130 	PINCTRL_PIN(19, "GPIO_19"),
131 	PINCTRL_PIN(20, "GPIO_20"),
132 	PINCTRL_PIN(21, "GPIO_21"),
133 	PINCTRL_PIN(22, "GPIO_22"),
134 	PINCTRL_PIN(23, "GPIO_23"),
135 	PINCTRL_PIN(24, "GPIO_24"),
136 	PINCTRL_PIN(25, "GPIO_25"),
137 	PINCTRL_PIN(26, "GPIO_26"),
138 	PINCTRL_PIN(27, "GPIO_27"),
139 	PINCTRL_PIN(28, "GPIO_28"),
140 	PINCTRL_PIN(29, "GPIO_29"),
141 	PINCTRL_PIN(30, "GPIO_30"),
142 	PINCTRL_PIN(31, "GPIO_31"),
143 	PINCTRL_PIN(32, "GPIO_32"),
144 	PINCTRL_PIN(33, "GPIO_33"),
145 	PINCTRL_PIN(34, "GPIO_34"),
146 	PINCTRL_PIN(35, "GPIO_35"),
147 	PINCTRL_PIN(36, "GPIO_36"),
148 	PINCTRL_PIN(37, "GPIO_37"),
149 	PINCTRL_PIN(38, "GPIO_38"),
150 	PINCTRL_PIN(39, "GPIO_39"),
151 	PINCTRL_PIN(40, "GPIO_40"),
152 	PINCTRL_PIN(41, "GPIO_41"),
153 	PINCTRL_PIN(42, "GPIO_42"),
154 	PINCTRL_PIN(43, "GPIO_43"),
155 	PINCTRL_PIN(44, "GPIO_44"),
156 	PINCTRL_PIN(45, "GPIO_45"),
157 	PINCTRL_PIN(46, "GPIO_46"),
158 	PINCTRL_PIN(47, "GPIO_47"),
159 	PINCTRL_PIN(48, "GPIO_48"),
160 	PINCTRL_PIN(49, "GPIO_49"),
161 	PINCTRL_PIN(50, "GPIO_50"),
162 	PINCTRL_PIN(51, "GPIO_51"),
163 	PINCTRL_PIN(52, "GPIO_52"),
164 	PINCTRL_PIN(53, "GPIO_53"),
165 	PINCTRL_PIN(54, "GPIO_54"),
166 	PINCTRL_PIN(55, "GPIO_55"),
167 	PINCTRL_PIN(56, "GPIO_56"),
168 	PINCTRL_PIN(57, "GPIO_57"),
169 	PINCTRL_PIN(58, "GPIO_58"),
170 	PINCTRL_PIN(59, "GPIO_59"),
171 	PINCTRL_PIN(60, "GPIO_60"),
172 	PINCTRL_PIN(61, "GPIO_61"),
173 	PINCTRL_PIN(62, "GPIO_62"),
174 	PINCTRL_PIN(63, "GPIO_63"),
175 	PINCTRL_PIN(64, "GPIO_64"),
176 	PINCTRL_PIN(65, "GPIO_65"),
177 	PINCTRL_PIN(66, "GPIO_66"),
178 	PINCTRL_PIN(67, "GPIO_67"),
179 	PINCTRL_PIN(68, "GPIO_68"),
180 	PINCTRL_PIN(69, "GPIO_69"),
181 	PINCTRL_PIN(70, "GPIO_70"),
182 	PINCTRL_PIN(71, "GPIO_71"),
183 	PINCTRL_PIN(72, "GPIO_72"),
184 	PINCTRL_PIN(73, "GPIO_73"),
185 	PINCTRL_PIN(74, "GPIO_74"),
186 	PINCTRL_PIN(75, "GPIO_75"),
187 	PINCTRL_PIN(76, "GPIO_76"),
188 	PINCTRL_PIN(77, "GPIO_77"),
189 	PINCTRL_PIN(78, "GPIO_78"),
190 	PINCTRL_PIN(79, "GPIO_79"),
191 	PINCTRL_PIN(80, "GPIO_80"),
192 	PINCTRL_PIN(81, "GPIO_81"),
193 	PINCTRL_PIN(82, "GPIO_82"),
194 	PINCTRL_PIN(83, "GPIO_83"),
195 	PINCTRL_PIN(84, "GPIO_84"),
196 	PINCTRL_PIN(85, "GPIO_85"),
197 	PINCTRL_PIN(86, "GPIO_86"),
198 	PINCTRL_PIN(87, "GPIO_87"),
199 	PINCTRL_PIN(88, "GPIO_88"),
200 	PINCTRL_PIN(89, "GPIO_89"),
201 	PINCTRL_PIN(90, "GPIO_90"),
202 	PINCTRL_PIN(91, "GPIO_91"),
203 	PINCTRL_PIN(92, "GPIO_92"),
204 	PINCTRL_PIN(93, "GPIO_93"),
205 	PINCTRL_PIN(94, "GPIO_94"),
206 	PINCTRL_PIN(95, "GPIO_95"),
207 	PINCTRL_PIN(96, "GPIO_96"),
208 	PINCTRL_PIN(97, "GPIO_97"),
209 	PINCTRL_PIN(98, "GPIO_98"),
210 	PINCTRL_PIN(99, "GPIO_99"),
211 	PINCTRL_PIN(100, "GPIO_100"),
212 	PINCTRL_PIN(101, "GPIO_101"),
213 	PINCTRL_PIN(102, "GPIO_102"),
214 	PINCTRL_PIN(103, "GPIO_103"),
215 	PINCTRL_PIN(104, "GPIO_104"),
216 	PINCTRL_PIN(105, "GPIO_105"),
217 	PINCTRL_PIN(106, "GPIO_106"),
218 	PINCTRL_PIN(107, "GPIO_107"),
219 	PINCTRL_PIN(108, "GPIO_108"),
220 	PINCTRL_PIN(109, "GPIO_109"),
221 	PINCTRL_PIN(110, "GPIO_110"),
222 	PINCTRL_PIN(111, "GPIO_111"),
223 	PINCTRL_PIN(112, "GPIO_112"),
224 	PINCTRL_PIN(113, "GPIO_113"),
225 	PINCTRL_PIN(114, "GPIO_114"),
226 	PINCTRL_PIN(115, "GPIO_115"),
227 	PINCTRL_PIN(116, "GPIO_116"),
228 	PINCTRL_PIN(117, "GPIO_117"),
229 	PINCTRL_PIN(118, "GPIO_118"),
230 	PINCTRL_PIN(119, "GPIO_119"),
231 	PINCTRL_PIN(120, "GPIO_120"),
232 	PINCTRL_PIN(121, "GPIO_121"),
233 	PINCTRL_PIN(122, "GPIO_122"),
234 	PINCTRL_PIN(123, "GPIO_123"),
235 	PINCTRL_PIN(124, "GPIO_124"),
236 	PINCTRL_PIN(125, "GPIO_125"),
237 	PINCTRL_PIN(126, "GPIO_126"),
238 	PINCTRL_PIN(127, "GPIO_127"),
239 	PINCTRL_PIN(128, "GPIO_128"),
240 	PINCTRL_PIN(129, "GPIO_129"),
241 	PINCTRL_PIN(130, "GPIO_130"),
242 	PINCTRL_PIN(131, "GPIO_131"),
243 	PINCTRL_PIN(132, "GPIO_132"),
244 	PINCTRL_PIN(133, "GPIO_133"),
245 	PINCTRL_PIN(134, "GPIO_134"),
246 	PINCTRL_PIN(135, "GPIO_135"),
247 	PINCTRL_PIN(136, "GPIO_136"),
248 	PINCTRL_PIN(137, "GPIO_137"),
249 	PINCTRL_PIN(138, "GPIO_138"),
250 	PINCTRL_PIN(139, "GPIO_139"),
251 	PINCTRL_PIN(140, "GPIO_140"),
252 	PINCTRL_PIN(141, "GPIO_141"),
253 	PINCTRL_PIN(142, "GPIO_142"),
254 	PINCTRL_PIN(143, "GPIO_143"),
255 	PINCTRL_PIN(144, "GPIO_144"),
256 	PINCTRL_PIN(145, "GPIO_145"),
257 	PINCTRL_PIN(146, "GPIO_146"),
258 	PINCTRL_PIN(147, "GPIO_147"),
259 	PINCTRL_PIN(148, "GPIO_148"),
260 	PINCTRL_PIN(149, "GPIO_149"),
261 	PINCTRL_PIN(150, "GPIO_150"),
262 	PINCTRL_PIN(151, "GPIO_151"),
263 	PINCTRL_PIN(152, "GPIO_152"),
264 	PINCTRL_PIN(153, "GPIO_153"),
265 	PINCTRL_PIN(154, "GPIO_154"),
266 	PINCTRL_PIN(155, "GPIO_155"),
267 	PINCTRL_PIN(156, "SDC1_RCLK"),
268 	PINCTRL_PIN(157, "SDC1_CLK"),
269 	PINCTRL_PIN(158, "SDC1_CMD"),
270 	PINCTRL_PIN(159, "SDC1_DATA"),
271 	PINCTRL_PIN(160, "SDC2_CLK"),
272 	PINCTRL_PIN(161, "SDC2_CMD"),
273 	PINCTRL_PIN(162, "SDC2_DATA"),
274 	PINCTRL_PIN(163, "UFS_RESET"),
275 };
276 
277 #define DECLARE_MSM_GPIO_PINS(pin) \
278 	static const unsigned int gpio##pin##_pins[] = { pin }
279 DECLARE_MSM_GPIO_PINS(0);
280 DECLARE_MSM_GPIO_PINS(1);
281 DECLARE_MSM_GPIO_PINS(2);
282 DECLARE_MSM_GPIO_PINS(3);
283 DECLARE_MSM_GPIO_PINS(4);
284 DECLARE_MSM_GPIO_PINS(5);
285 DECLARE_MSM_GPIO_PINS(6);
286 DECLARE_MSM_GPIO_PINS(7);
287 DECLARE_MSM_GPIO_PINS(8);
288 DECLARE_MSM_GPIO_PINS(9);
289 DECLARE_MSM_GPIO_PINS(10);
290 DECLARE_MSM_GPIO_PINS(11);
291 DECLARE_MSM_GPIO_PINS(12);
292 DECLARE_MSM_GPIO_PINS(13);
293 DECLARE_MSM_GPIO_PINS(14);
294 DECLARE_MSM_GPIO_PINS(15);
295 DECLARE_MSM_GPIO_PINS(16);
296 DECLARE_MSM_GPIO_PINS(17);
297 DECLARE_MSM_GPIO_PINS(18);
298 DECLARE_MSM_GPIO_PINS(19);
299 DECLARE_MSM_GPIO_PINS(20);
300 DECLARE_MSM_GPIO_PINS(21);
301 DECLARE_MSM_GPIO_PINS(22);
302 DECLARE_MSM_GPIO_PINS(23);
303 DECLARE_MSM_GPIO_PINS(24);
304 DECLARE_MSM_GPIO_PINS(25);
305 DECLARE_MSM_GPIO_PINS(26);
306 DECLARE_MSM_GPIO_PINS(27);
307 DECLARE_MSM_GPIO_PINS(28);
308 DECLARE_MSM_GPIO_PINS(29);
309 DECLARE_MSM_GPIO_PINS(30);
310 DECLARE_MSM_GPIO_PINS(31);
311 DECLARE_MSM_GPIO_PINS(32);
312 DECLARE_MSM_GPIO_PINS(33);
313 DECLARE_MSM_GPIO_PINS(34);
314 DECLARE_MSM_GPIO_PINS(35);
315 DECLARE_MSM_GPIO_PINS(36);
316 DECLARE_MSM_GPIO_PINS(37);
317 DECLARE_MSM_GPIO_PINS(38);
318 DECLARE_MSM_GPIO_PINS(39);
319 DECLARE_MSM_GPIO_PINS(40);
320 DECLARE_MSM_GPIO_PINS(41);
321 DECLARE_MSM_GPIO_PINS(42);
322 DECLARE_MSM_GPIO_PINS(43);
323 DECLARE_MSM_GPIO_PINS(44);
324 DECLARE_MSM_GPIO_PINS(45);
325 DECLARE_MSM_GPIO_PINS(46);
326 DECLARE_MSM_GPIO_PINS(47);
327 DECLARE_MSM_GPIO_PINS(48);
328 DECLARE_MSM_GPIO_PINS(49);
329 DECLARE_MSM_GPIO_PINS(50);
330 DECLARE_MSM_GPIO_PINS(51);
331 DECLARE_MSM_GPIO_PINS(52);
332 DECLARE_MSM_GPIO_PINS(53);
333 DECLARE_MSM_GPIO_PINS(54);
334 DECLARE_MSM_GPIO_PINS(55);
335 DECLARE_MSM_GPIO_PINS(56);
336 DECLARE_MSM_GPIO_PINS(57);
337 DECLARE_MSM_GPIO_PINS(58);
338 DECLARE_MSM_GPIO_PINS(59);
339 DECLARE_MSM_GPIO_PINS(60);
340 DECLARE_MSM_GPIO_PINS(61);
341 DECLARE_MSM_GPIO_PINS(62);
342 DECLARE_MSM_GPIO_PINS(63);
343 DECLARE_MSM_GPIO_PINS(64);
344 DECLARE_MSM_GPIO_PINS(65);
345 DECLARE_MSM_GPIO_PINS(66);
346 DECLARE_MSM_GPIO_PINS(67);
347 DECLARE_MSM_GPIO_PINS(68);
348 DECLARE_MSM_GPIO_PINS(69);
349 DECLARE_MSM_GPIO_PINS(70);
350 DECLARE_MSM_GPIO_PINS(71);
351 DECLARE_MSM_GPIO_PINS(72);
352 DECLARE_MSM_GPIO_PINS(73);
353 DECLARE_MSM_GPIO_PINS(74);
354 DECLARE_MSM_GPIO_PINS(75);
355 DECLARE_MSM_GPIO_PINS(76);
356 DECLARE_MSM_GPIO_PINS(77);
357 DECLARE_MSM_GPIO_PINS(78);
358 DECLARE_MSM_GPIO_PINS(79);
359 DECLARE_MSM_GPIO_PINS(80);
360 DECLARE_MSM_GPIO_PINS(81);
361 DECLARE_MSM_GPIO_PINS(82);
362 DECLARE_MSM_GPIO_PINS(83);
363 DECLARE_MSM_GPIO_PINS(84);
364 DECLARE_MSM_GPIO_PINS(85);
365 DECLARE_MSM_GPIO_PINS(86);
366 DECLARE_MSM_GPIO_PINS(87);
367 DECLARE_MSM_GPIO_PINS(88);
368 DECLARE_MSM_GPIO_PINS(89);
369 DECLARE_MSM_GPIO_PINS(90);
370 DECLARE_MSM_GPIO_PINS(91);
371 DECLARE_MSM_GPIO_PINS(92);
372 DECLARE_MSM_GPIO_PINS(93);
373 DECLARE_MSM_GPIO_PINS(94);
374 DECLARE_MSM_GPIO_PINS(95);
375 DECLARE_MSM_GPIO_PINS(96);
376 DECLARE_MSM_GPIO_PINS(97);
377 DECLARE_MSM_GPIO_PINS(98);
378 DECLARE_MSM_GPIO_PINS(99);
379 DECLARE_MSM_GPIO_PINS(100);
380 DECLARE_MSM_GPIO_PINS(101);
381 DECLARE_MSM_GPIO_PINS(102);
382 DECLARE_MSM_GPIO_PINS(103);
383 DECLARE_MSM_GPIO_PINS(104);
384 DECLARE_MSM_GPIO_PINS(105);
385 DECLARE_MSM_GPIO_PINS(106);
386 DECLARE_MSM_GPIO_PINS(107);
387 DECLARE_MSM_GPIO_PINS(108);
388 DECLARE_MSM_GPIO_PINS(109);
389 DECLARE_MSM_GPIO_PINS(110);
390 DECLARE_MSM_GPIO_PINS(111);
391 DECLARE_MSM_GPIO_PINS(112);
392 DECLARE_MSM_GPIO_PINS(113);
393 DECLARE_MSM_GPIO_PINS(114);
394 DECLARE_MSM_GPIO_PINS(115);
395 DECLARE_MSM_GPIO_PINS(116);
396 DECLARE_MSM_GPIO_PINS(117);
397 DECLARE_MSM_GPIO_PINS(118);
398 DECLARE_MSM_GPIO_PINS(119);
399 DECLARE_MSM_GPIO_PINS(120);
400 DECLARE_MSM_GPIO_PINS(121);
401 DECLARE_MSM_GPIO_PINS(122);
402 DECLARE_MSM_GPIO_PINS(123);
403 DECLARE_MSM_GPIO_PINS(124);
404 DECLARE_MSM_GPIO_PINS(125);
405 DECLARE_MSM_GPIO_PINS(126);
406 DECLARE_MSM_GPIO_PINS(127);
407 DECLARE_MSM_GPIO_PINS(128);
408 DECLARE_MSM_GPIO_PINS(129);
409 DECLARE_MSM_GPIO_PINS(130);
410 DECLARE_MSM_GPIO_PINS(131);
411 DECLARE_MSM_GPIO_PINS(132);
412 DECLARE_MSM_GPIO_PINS(133);
413 DECLARE_MSM_GPIO_PINS(134);
414 DECLARE_MSM_GPIO_PINS(135);
415 DECLARE_MSM_GPIO_PINS(136);
416 DECLARE_MSM_GPIO_PINS(137);
417 DECLARE_MSM_GPIO_PINS(138);
418 DECLARE_MSM_GPIO_PINS(139);
419 DECLARE_MSM_GPIO_PINS(140);
420 DECLARE_MSM_GPIO_PINS(141);
421 DECLARE_MSM_GPIO_PINS(142);
422 DECLARE_MSM_GPIO_PINS(143);
423 DECLARE_MSM_GPIO_PINS(144);
424 DECLARE_MSM_GPIO_PINS(145);
425 DECLARE_MSM_GPIO_PINS(146);
426 DECLARE_MSM_GPIO_PINS(147);
427 DECLARE_MSM_GPIO_PINS(148);
428 DECLARE_MSM_GPIO_PINS(149);
429 DECLARE_MSM_GPIO_PINS(150);
430 DECLARE_MSM_GPIO_PINS(151);
431 DECLARE_MSM_GPIO_PINS(152);
432 DECLARE_MSM_GPIO_PINS(153);
433 DECLARE_MSM_GPIO_PINS(154);
434 DECLARE_MSM_GPIO_PINS(155);
435 
436 static const unsigned int ufs_reset_pins[] = { 156 };
437 static const unsigned int sdc1_rclk_pins[] = { 157 };
438 static const unsigned int sdc1_clk_pins[] = { 158 };
439 static const unsigned int sdc1_cmd_pins[] = { 159 };
440 static const unsigned int sdc1_data_pins[] = { 160 };
441 static const unsigned int sdc2_clk_pins[] = { 161 };
442 static const unsigned int sdc2_cmd_pins[] = { 162 };
443 static const unsigned int sdc2_data_pins[] = { 163 };
444 
445 enum sm6350_functions {
446 	msm_mux_adsp_ext,
447 	msm_mux_agera_pll,
448 	msm_mux_atest_char,
449 	msm_mux_atest_char0,
450 	msm_mux_atest_char1,
451 	msm_mux_atest_char2,
452 	msm_mux_atest_char3,
453 	msm_mux_atest_tsens,
454 	msm_mux_atest_tsens2,
455 	msm_mux_atest_usb,
456 	msm_mux_audio_ref,
457 	msm_mux_btfm_slimbus,
458 	msm_mux_cam_mclk0,
459 	msm_mux_cam_mclk1,
460 	msm_mux_cam_mclk2,
461 	msm_mux_cam_mclk3,
462 	msm_mux_cam_mclk4,
463 	msm_mux_cci_async,
464 	msm_mux_cci_i2c,
465 	msm_mux_cci_timer0,
466 	msm_mux_cci_timer1,
467 	msm_mux_cci_timer2,
468 	msm_mux_cci_timer3,
469 	msm_mux_cci_timer4,
470 	msm_mux_cri_trng,
471 	msm_mux_dbg_out,
472 	msm_mux_ddr_bist,
473 	msm_mux_ddr_pxi0,
474 	msm_mux_ddr_pxi1,
475 	msm_mux_ddr_pxi2,
476 	msm_mux_ddr_pxi3,
477 	msm_mux_dp_hot,
478 	msm_mux_edp_lcd,
479 	msm_mux_gcc_gp1,
480 	msm_mux_gcc_gp2,
481 	msm_mux_gcc_gp3,
482 	msm_mux_gp_pdm0,
483 	msm_mux_gp_pdm1,
484 	msm_mux_gp_pdm2,
485 	msm_mux_gpio,
486 	msm_mux_gps_tx,
487 	msm_mux_ibi_i3c,
488 	msm_mux_jitter_bist,
489 	msm_mux_ldo_en,
490 	msm_mux_ldo_update,
491 	msm_mux_lpass_ext,
492 	msm_mux_m_voc,
493 	msm_mux_mclk,
494 	msm_mux_mdp_vsync,
495 	msm_mux_mdp_vsync0,
496 	msm_mux_mdp_vsync1,
497 	msm_mux_mdp_vsync2,
498 	msm_mux_mdp_vsync3,
499 	msm_mux_mi2s_0,
500 	msm_mux_mi2s_1,
501 	msm_mux_mi2s_2,
502 	msm_mux_mss_lte,
503 	msm_mux_nav_gpio,
504 	msm_mux_nav_pps,
505 	msm_mux_pa_indicator,
506 	msm_mux_pcie0_clk,
507 	msm_mux_phase_flag,
508 	msm_mux_pll_bist,
509 	msm_mux_pll_bypassnl,
510 	msm_mux_pll_reset,
511 	msm_mux_prng_rosc,
512 	msm_mux_qdss_cti,
513 	msm_mux_qdss_gpio,
514 	msm_mux_qdss_gpio0,
515 	msm_mux_qdss_gpio1,
516 	msm_mux_qdss_gpio10,
517 	msm_mux_qdss_gpio11,
518 	msm_mux_qdss_gpio12,
519 	msm_mux_qdss_gpio13,
520 	msm_mux_qdss_gpio14,
521 	msm_mux_qdss_gpio15,
522 	msm_mux_qdss_gpio2,
523 	msm_mux_qdss_gpio3,
524 	msm_mux_qdss_gpio4,
525 	msm_mux_qdss_gpio5,
526 	msm_mux_qdss_gpio6,
527 	msm_mux_qdss_gpio7,
528 	msm_mux_qdss_gpio8,
529 	msm_mux_qdss_gpio9,
530 	msm_mux_qlink0_enable,
531 	msm_mux_qlink0_request,
532 	msm_mux_qlink0_wmss,
533 	msm_mux_qlink1_enable,
534 	msm_mux_qlink1_request,
535 	msm_mux_qlink1_wmss,
536 	msm_mux_qup00,
537 	msm_mux_qup01,
538 	msm_mux_qup02,
539 	msm_mux_qup10,
540 	msm_mux_qup11,
541 	msm_mux_qup12,
542 	msm_mux_qup13_f1,
543 	msm_mux_qup13_f2,
544 	msm_mux_qup14,
545 	msm_mux_rffe0_clk,
546 	msm_mux_rffe0_data,
547 	msm_mux_rffe1_clk,
548 	msm_mux_rffe1_data,
549 	msm_mux_rffe2_clk,
550 	msm_mux_rffe2_data,
551 	msm_mux_rffe3_clk,
552 	msm_mux_rffe3_data,
553 	msm_mux_rffe4_clk,
554 	msm_mux_rffe4_data,
555 	msm_mux_sd_write,
556 	msm_mux_sdc1_tb,
557 	msm_mux_sdc2_tb,
558 	msm_mux_sp_cmu,
559 	msm_mux_tgu_ch0,
560 	msm_mux_tgu_ch1,
561 	msm_mux_tgu_ch2,
562 	msm_mux_tgu_ch3,
563 	msm_mux_tsense_pwm1,
564 	msm_mux_tsense_pwm2,
565 	msm_mux_uim1_clk,
566 	msm_mux_uim1_data,
567 	msm_mux_uim1_present,
568 	msm_mux_uim1_reset,
569 	msm_mux_uim2_clk,
570 	msm_mux_uim2_data,
571 	msm_mux_uim2_present,
572 	msm_mux_uim2_reset,
573 	msm_mux_usb_phy,
574 	msm_mux_vfr_1,
575 	msm_mux_vsense_trigger,
576 	msm_mux_wlan1_adc0,
577 	msm_mux_wlan1_adc1,
578 	msm_mux_wlan2_adc0,
579 	msm_mux_wlan2_adc1,
580 	msm_mux__,
581 };
582 
583 static const char * const ibi_i3c_groups[] = {
584 	"gpio0", "gpio1",
585 };
586 static const char * const gpio_groups[] = {
587 	"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
588 	"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
589 	"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
590 	"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
591 	"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
592 	"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
593 	"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
594 	"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
595 	"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
596 	"gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
597 	"gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
598 	"gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
599 	"gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
600 	"gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
601 	"gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
602 	"gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
603 	"gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
604 	"gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
605 	"gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
606 	"gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
607 	"gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
608 	"gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
609 	"gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152",
610 	"gpio153", "gpio154", "gpio155",
611 };
612 static const char * const cri_trng_groups[] = {
613 	"gpio0", "gpio1", "gpio2",
614 };
615 static const char * const qup00_groups[] = {
616 	"gpio0", "gpio1", "gpio2", "gpio3",
617 };
618 static const char * const cci_i2c_groups[] = {
619 	"gpio2", "gpio3", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
620 	"gpio44",
621 };
622 static const char * const qdss_cti_groups[] = {
623 	"gpio2", "gpio3", "gpio6", "gpio7", "gpio61", "gpio62", "gpio86",
624 	"gpio87",
625 };
626 static const char * const sp_cmu_groups[] = {
627 	"gpio3",
628 };
629 static const char * const dbg_out_groups[] = {
630 	"gpio3",
631 };
632 static const char * const qup14_groups[] = {
633 	"gpio4", "gpio4", "gpio5", "gpio5",
634 };
635 static const char * const sdc1_tb_groups[] = {
636 	"gpio4",
637 };
638 static const char * const sdc2_tb_groups[] = {
639 	"gpio5",
640 };
641 static const char * const mdp_vsync_groups[] = {
642 	"gpio6", "gpio23", "gpio24", "gpio27", "gpio28",
643 };
644 static const char * const gp_pdm1_groups[] = {
645 	"gpio8", "gpio52",
646 };
647 static const char * const qdss_gpio_groups[] = {
648 	"gpio8", "gpio9", "gpio63", "gpio64",
649 };
650 static const char * const m_voc_groups[] = {
651 	"gpio12",
652 };
653 static const char * const dp_hot_groups[] = {
654 	"gpio12", "gpio118",
655 };
656 static const char * const phase_flag_groups[] = {
657 	"gpio12", "gpio17", "gpio18", "gpio34", "gpio35",
658 	"gpio36", "gpio37", "gpio38", "gpio39", "gpio40",
659 	"gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
660 	"gpio46", "gpio47", "gpio48", "gpio49", "gpio50",
661 	"gpio51", "gpio52", "gpio53", "gpio56", "gpio57",
662 	"gpio60", "gpio61", "gpio62", "gpio63", "gpio64",
663 	"gpio67", "gpio68",
664 };
665 static const char * const qup10_groups[] = {
666 	"gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
667 };
668 static const char * const pll_bypassnl_groups[] = {
669 	"gpio13",
670 };
671 static const char * const pll_reset_groups[] = {
672 	"gpio14",
673 };
674 static const char * const qup12_groups[] = {
675 	"gpio19", "gpio19", "gpio20", "gpio20",
676 };
677 static const char * const ddr_bist_groups[] = {
678 	"gpio19", "gpio20", "gpio21", "gpio22",
679 };
680 static const char * const gcc_gp2_groups[] = {
681 	"gpio21",
682 };
683 static const char * const gcc_gp3_groups[] = {
684 	"gpio22",
685 };
686 static const char * const edp_lcd_groups[] = {
687 	"gpio23",
688 };
689 static const char * const qup13_f1_groups[] = {
690 	"gpio25", "gpio26",
691 };
692 static const char * const qup13_f2_groups[] = {
693 	"gpio25", "gpio26",
694 };
695 static const char * const qup11_groups[] = {
696 	"gpio27", "gpio27", "gpio28", "gpio28",
697 };
698 static const char * const pll_bist_groups[] = {
699 	"gpio27",
700 };
701 static const char * const qdss_gpio14_groups[] = {
702 	"gpio27", "gpio36",
703 };
704 static const char * const qdss_gpio15_groups[] = {
705 	"gpio28", "gpio37",
706 };
707 static const char * const cam_mclk0_groups[] = {
708 	"gpio29",
709 };
710 static const char * const cam_mclk1_groups[] = {
711 	"gpio30",
712 };
713 static const char * const cam_mclk2_groups[] = {
714 	"gpio31",
715 };
716 static const char * const cam_mclk3_groups[] = {
717 	"gpio32",
718 };
719 static const char * const cam_mclk4_groups[] = {
720 	"gpio33",
721 };
722 static const char * const cci_timer0_groups[] = {
723 	"gpio34",
724 };
725 static const char * const qdss_gpio12_groups[] = {
726 	"gpio34", "gpio52",
727 };
728 static const char * const cci_timer1_groups[] = {
729 	"gpio35",
730 };
731 static const char * const cci_async_groups[] = {
732 	"gpio35", "gpio36", "gpio48", "gpio52", "gpio53",
733 };
734 static const char * const qdss_gpio13_groups[] = {
735 	"gpio35", "gpio53",
736 };
737 static const char * const cci_timer2_groups[] = {
738 	"gpio36",
739 };
740 static const char * const cci_timer3_groups[] = {
741 	"gpio37",
742 };
743 static const char * const gp_pdm0_groups[] = {
744 	"gpio37", "gpio68",
745 };
746 static const char * const cci_timer4_groups[] = {
747 	"gpio38",
748 };
749 static const char * const qdss_gpio2_groups[] = {
750 	"gpio38", "gpio41",
751 };
752 static const char * const qdss_gpio0_groups[] = {
753 	"gpio39", "gpio65",
754 };
755 static const char * const qdss_gpio1_groups[] = {
756 	"gpio40", "gpio66",
757 };
758 static const char * const qdss_gpio3_groups[] = {
759 	"gpio42", "gpio47",
760 };
761 static const char * const qdss_gpio4_groups[] = {
762 	"gpio43", "gpio88",
763 };
764 static const char * const qdss_gpio5_groups[] = {
765 	"gpio44", "gpio89",
766 };
767 static const char * const qup02_groups[] = {
768 	"gpio45", "gpio46", "gpio48", "gpio56", "gpio57",
769 };
770 static const char * const qdss_gpio6_groups[] = {
771 	"gpio45", "gpio90",
772 };
773 static const char * const qdss_gpio7_groups[] = {
774 	"gpio46", "gpio91",
775 };
776 static const char * const mdp_vsync0_groups[] = {
777 	"gpio47",
778 };
779 static const char * const mdp_vsync1_groups[] = {
780 	"gpio48",
781 };
782 static const char * const gcc_gp1_groups[] = {
783 	"gpio48", "gpio58",
784 };
785 static const char * const qdss_gpio8_groups[] = {
786 	"gpio48", "gpio92",
787 };
788 static const char * const vfr_1_groups[] = {
789 	"gpio49",
790 };
791 static const char * const qdss_gpio9_groups[] = {
792 	"gpio49", "gpio93",
793 };
794 static const char * const qdss_gpio10_groups[] = {
795 	"gpio50", "gpio56",
796 };
797 static const char * const qdss_gpio11_groups[] = {
798 	"gpio51", "gpio57",
799 };
800 static const char * const mdp_vsync2_groups[] = {
801 	"gpio56",
802 };
803 static const char * const mdp_vsync3_groups[] = {
804 	"gpio57",
805 };
806 static const char * const gp_pdm2_groups[] = {
807 	"gpio57",
808 };
809 static const char * const audio_ref_groups[] = {
810 	"gpio60",
811 };
812 static const char * const lpass_ext_groups[] = {
813 	"gpio60", "gpio93",
814 };
815 static const char * const mi2s_2_groups[] = {
816 	"gpio60", "gpio72", "gpio73", "gpio74",
817 };
818 static const char * const qup01_groups[] = {
819 	"gpio61", "gpio62", "gpio63", "gpio64",
820 };
821 static const char * const tgu_ch0_groups[] = {
822 	"gpio61",
823 };
824 static const char * const tgu_ch1_groups[] = {
825 	"gpio62",
826 };
827 static const char * const tgu_ch2_groups[] = {
828 	"gpio63",
829 };
830 static const char * const tgu_ch3_groups[] = {
831 	"gpio64",
832 };
833 static const char * const mss_lte_groups[] = {
834 	"gpio65", "gpio66",
835 };
836 static const char * const btfm_slimbus_groups[] = {
837 	"gpio67", "gpio68", "gpio86", "gpio87",
838 };
839 static const char * const mi2s_1_groups[] = {
840 	"gpio67", "gpio68", "gpio86", "gpio87",
841 };
842 static const char * const uim2_data_groups[] = {
843 	"gpio75",
844 };
845 static const char * const uim2_clk_groups[] = {
846 	"gpio76",
847 };
848 static const char * const uim2_reset_groups[] = {
849 	"gpio77",
850 };
851 static const char * const uim2_present_groups[] = {
852 	"gpio78",
853 };
854 static const char * const uim1_data_groups[] = {
855 	"gpio79",
856 };
857 static const char * const uim1_clk_groups[] = {
858 	"gpio80",
859 };
860 static const char * const uim1_reset_groups[] = {
861 	"gpio81",
862 };
863 static const char * const uim1_present_groups[] = {
864 	"gpio82",
865 };
866 static const char * const atest_usb_groups[] = {
867 	"gpio83", "gpio84", "gpio85", "gpio86",
868 	"gpio87", "gpio88", "gpio89", "gpio90",
869 	"gpio91", "gpio92",
870 };
871 static const char * const sd_write_groups[] = {
872 	"gpio85",
873 };
874 static const char * const ddr_pxi0_groups[] = {
875 	"gpio86", "gpio90",
876 };
877 static const char * const adsp_ext_groups[] = {
878 	"gpio87",
879 };
880 static const char * const ddr_pxi1_groups[] = {
881 	"gpio87", "gpio91",
882 };
883 static const char * const mi2s_0_groups[] = {
884 	"gpio88", "gpio89", "gpio90", "gpio91",
885 };
886 static const char * const ddr_pxi2_groups[] = {
887 	"gpio88", "gpio92",
888 };
889 static const char * const tsense_pwm1_groups[] = {
890 	"gpio88",
891 };
892 static const char * const tsense_pwm2_groups[] = {
893 	"gpio88",
894 };
895 static const char * const agera_pll_groups[] = {
896 	"gpio89",
897 };
898 static const char * const vsense_trigger_groups[] = {
899 	"gpio89",
900 };
901 static const char * const ddr_pxi3_groups[] = {
902 	"gpio89", "gpio93",
903 };
904 static const char * const jitter_bist_groups[] = {
905 	"gpio90",
906 };
907 static const char * const wlan1_adc0_groups[] = {
908 	"gpio90",
909 };
910 static const char * const wlan2_adc0_groups[] = {
911 	"gpio91",
912 };
913 static const char * const atest_tsens_groups[] = {
914 	"gpio92",
915 };
916 static const char * const wlan1_adc1_groups[] = {
917 	"gpio92",
918 };
919 static const char * const mclk_groups[] = {
920 	"gpio93",
921 };
922 static const char * const atest_tsens2_groups[] = {
923 	"gpio93",
924 };
925 static const char * const wlan2_adc1_groups[] = {
926 	"gpio93",
927 };
928 static const char * const ldo_en_groups[] = {
929 	"gpio95",
930 };
931 static const char * const atest_char_groups[] = {
932 	"gpio95",
933 };
934 static const char * const ldo_update_groups[] = {
935 	"gpio96",
936 };
937 static const char * const atest_char0_groups[] = {
938 	"gpio96",
939 };
940 static const char * const prng_rosc_groups[] = {
941 	"gpio97",
942 };
943 static const char * const atest_char1_groups[] = {
944 	"gpio97",
945 };
946 static const char * const atest_char2_groups[] = {
947 	"gpio98",
948 };
949 static const char * const atest_char3_groups[] = {
950 	"gpio99",
951 };
952 static const char * const nav_gpio_groups[] = {
953 	"gpio101", "gpio102",
954 };
955 static const char * const nav_pps_groups[] = {
956 	"gpio101", "gpio101", "gpio102", "gpio102",
957 };
958 static const char * const gps_tx_groups[] = {
959 	"gpio101", "gpio102", "gpio107", "gpio108",
960 };
961 static const char * const qlink0_wmss_groups[] = {
962 	"gpio103",
963 };
964 static const char * const qlink0_request_groups[] = {
965 	"gpio104",
966 };
967 static const char * const qlink0_enable_groups[] = {
968 	"gpio105",
969 };
970 static const char * const qlink1_wmss_groups[] = {
971 	"gpio106",
972 };
973 static const char * const qlink1_request_groups[] = {
974 	"gpio107",
975 };
976 static const char * const qlink1_enable_groups[] = {
977 	"gpio108",
978 };
979 static const char * const rffe0_data_groups[] = {
980 	"gpio109",
981 };
982 static const char * const rffe0_clk_groups[] = {
983 	"gpio110",
984 };
985 static const char * const rffe1_data_groups[] = {
986 	"gpio111",
987 };
988 static const char * const rffe1_clk_groups[] = {
989 	"gpio112",
990 };
991 static const char * const rffe2_data_groups[] = {
992 	"gpio113",
993 };
994 static const char * const rffe2_clk_groups[] = {
995 	"gpio114",
996 };
997 static const char * const rffe3_data_groups[] = {
998 	"gpio115",
999 };
1000 static const char * const rffe3_clk_groups[] = {
1001 	"gpio116",
1002 };
1003 static const char * const rffe4_data_groups[] = {
1004 	"gpio117",
1005 };
1006 static const char * const rffe4_clk_groups[] = {
1007 	"gpio118",
1008 };
1009 static const char * const pa_indicator_groups[] = {
1010 	"gpio118",
1011 };
1012 static const char * const pcie0_clk_groups[] = {
1013 	"gpio122",
1014 };
1015 static const char * const usb_phy_groups[] = {
1016 	"gpio124",
1017 };
1018 
1019 static const struct msm_function sm6350_functions[] = {
1020 	FUNCTION(adsp_ext),
1021 	FUNCTION(agera_pll),
1022 	FUNCTION(atest_char),
1023 	FUNCTION(atest_char0),
1024 	FUNCTION(atest_char1),
1025 	FUNCTION(atest_char2),
1026 	FUNCTION(atest_char3),
1027 	FUNCTION(atest_tsens),
1028 	FUNCTION(atest_tsens2),
1029 	FUNCTION(atest_usb),
1030 	FUNCTION(audio_ref),
1031 	FUNCTION(btfm_slimbus),
1032 	FUNCTION(cam_mclk0),
1033 	FUNCTION(cam_mclk1),
1034 	FUNCTION(cam_mclk2),
1035 	FUNCTION(cam_mclk3),
1036 	FUNCTION(cam_mclk4),
1037 	FUNCTION(cci_async),
1038 	FUNCTION(cci_i2c),
1039 	FUNCTION(cci_timer0),
1040 	FUNCTION(cci_timer1),
1041 	FUNCTION(cci_timer2),
1042 	FUNCTION(cci_timer3),
1043 	FUNCTION(cci_timer4),
1044 	FUNCTION(cri_trng),
1045 	FUNCTION(dbg_out),
1046 	FUNCTION(ddr_bist),
1047 	FUNCTION(ddr_pxi0),
1048 	FUNCTION(ddr_pxi1),
1049 	FUNCTION(ddr_pxi2),
1050 	FUNCTION(ddr_pxi3),
1051 	FUNCTION(dp_hot),
1052 	FUNCTION(edp_lcd),
1053 	FUNCTION(gcc_gp1),
1054 	FUNCTION(gcc_gp2),
1055 	FUNCTION(gcc_gp3),
1056 	FUNCTION(gp_pdm0),
1057 	FUNCTION(gp_pdm1),
1058 	FUNCTION(gp_pdm2),
1059 	FUNCTION(gpio),
1060 	FUNCTION(gps_tx),
1061 	FUNCTION(ibi_i3c),
1062 	FUNCTION(jitter_bist),
1063 	FUNCTION(ldo_en),
1064 	FUNCTION(ldo_update),
1065 	FUNCTION(lpass_ext),
1066 	FUNCTION(m_voc),
1067 	FUNCTION(mclk),
1068 	FUNCTION(mdp_vsync),
1069 	FUNCTION(mdp_vsync0),
1070 	FUNCTION(mdp_vsync1),
1071 	FUNCTION(mdp_vsync2),
1072 	FUNCTION(mdp_vsync3),
1073 	FUNCTION(mi2s_0),
1074 	FUNCTION(mi2s_1),
1075 	FUNCTION(mi2s_2),
1076 	FUNCTION(mss_lte),
1077 	FUNCTION(nav_gpio),
1078 	FUNCTION(nav_pps),
1079 	FUNCTION(pa_indicator),
1080 	FUNCTION(pcie0_clk),
1081 	FUNCTION(phase_flag),
1082 	FUNCTION(pll_bist),
1083 	FUNCTION(pll_bypassnl),
1084 	FUNCTION(pll_reset),
1085 	FUNCTION(prng_rosc),
1086 	FUNCTION(qdss_cti),
1087 	FUNCTION(qdss_gpio),
1088 	FUNCTION(qdss_gpio0),
1089 	FUNCTION(qdss_gpio1),
1090 	FUNCTION(qdss_gpio10),
1091 	FUNCTION(qdss_gpio11),
1092 	FUNCTION(qdss_gpio12),
1093 	FUNCTION(qdss_gpio13),
1094 	FUNCTION(qdss_gpio14),
1095 	FUNCTION(qdss_gpio15),
1096 	FUNCTION(qdss_gpio2),
1097 	FUNCTION(qdss_gpio3),
1098 	FUNCTION(qdss_gpio4),
1099 	FUNCTION(qdss_gpio5),
1100 	FUNCTION(qdss_gpio6),
1101 	FUNCTION(qdss_gpio7),
1102 	FUNCTION(qdss_gpio8),
1103 	FUNCTION(qdss_gpio9),
1104 	FUNCTION(qlink0_enable),
1105 	FUNCTION(qlink0_request),
1106 	FUNCTION(qlink0_wmss),
1107 	FUNCTION(qlink1_enable),
1108 	FUNCTION(qlink1_request),
1109 	FUNCTION(qlink1_wmss),
1110 	FUNCTION(qup00),
1111 	FUNCTION(qup01),
1112 	FUNCTION(qup02),
1113 	FUNCTION(qup10),
1114 	FUNCTION(qup11),
1115 	FUNCTION(qup12),
1116 	FUNCTION(qup13_f1),
1117 	FUNCTION(qup13_f2),
1118 	FUNCTION(qup14),
1119 	FUNCTION(rffe0_clk),
1120 	FUNCTION(rffe0_data),
1121 	FUNCTION(rffe1_clk),
1122 	FUNCTION(rffe1_data),
1123 	FUNCTION(rffe2_clk),
1124 	FUNCTION(rffe2_data),
1125 	FUNCTION(rffe3_clk),
1126 	FUNCTION(rffe3_data),
1127 	FUNCTION(rffe4_clk),
1128 	FUNCTION(rffe4_data),
1129 	FUNCTION(sd_write),
1130 	FUNCTION(sdc1_tb),
1131 	FUNCTION(sdc2_tb),
1132 	FUNCTION(sp_cmu),
1133 	FUNCTION(tgu_ch0),
1134 	FUNCTION(tgu_ch1),
1135 	FUNCTION(tgu_ch2),
1136 	FUNCTION(tgu_ch3),
1137 	FUNCTION(tsense_pwm1),
1138 	FUNCTION(tsense_pwm2),
1139 	FUNCTION(uim1_clk),
1140 	FUNCTION(uim1_data),
1141 	FUNCTION(uim1_present),
1142 	FUNCTION(uim1_reset),
1143 	FUNCTION(uim2_clk),
1144 	FUNCTION(uim2_data),
1145 	FUNCTION(uim2_present),
1146 	FUNCTION(uim2_reset),
1147 	FUNCTION(usb_phy),
1148 	FUNCTION(vfr_1),
1149 	FUNCTION(vsense_trigger),
1150 	FUNCTION(wlan1_adc0),
1151 	FUNCTION(wlan1_adc1),
1152 	FUNCTION(wlan2_adc0),
1153 	FUNCTION(wlan2_adc1),
1154 };
1155 
1156 /*
1157  * Every pin is maintained as a single group, and missing or non-existing pin
1158  * would be maintained as dummy group to synchronize pin group index with
1159  * pin descriptor registered with pinctrl core.
1160  * Clients would not be able to request these dummy pin groups.
1161  */
1162 static const struct msm_pingroup sm6350_groups[] = {
1163 	[0] = PINGROUP(0, ibi_i3c, qup00, cri_trng, _, _, _, _, _, _),
1164 	[1] = PINGROUP(1, ibi_i3c, qup00, cri_trng, _, _, _, _, _, _),
1165 	[2] = PINGROUP(2, qup00, cci_i2c, cri_trng, qdss_cti, _, _, _, _, _),
1166 	[3] = PINGROUP(3, qup00, cci_i2c, sp_cmu, dbg_out, qdss_cti, _, _, _, _),
1167 	[4] = PINGROUP(4, qup14, qup14, sdc1_tb, _, _, _, _, _, _),
1168 	[5] = PINGROUP(5, qup14, qup14, sdc2_tb, _, _, _, _, _, _),
1169 	[6] = PINGROUP(6, mdp_vsync, qdss_cti, _, _, _, _, _, _, _),
1170 	[7] = PINGROUP(7, qdss_cti, _, _, _, _, _, _, _, _),
1171 	[8] = PINGROUP(8, gp_pdm1, qdss_gpio, _, _, _, _, _, _, _),
1172 	[9] = PINGROUP(9, qdss_gpio, _, _, _, _, _, _, _, _),
1173 	[10] = PINGROUP(10, _, _, _, _, _, _, _, _, _),
1174 	[11] = PINGROUP(11, _, _, _, _, _, _, _, _, _),
1175 	[12] = PINGROUP(12, m_voc, dp_hot, _, phase_flag, _, _, _, _, _),
1176 	[13] = PINGROUP(13, qup10, pll_bypassnl, _, _, _, _, _, _, _),
1177 	[14] = PINGROUP(14, qup10, pll_reset, _, _, _, _, _, _, _),
1178 	[15] = PINGROUP(15, qup10, _, _, _, _, _, _, _, _),
1179 	[16] = PINGROUP(16, qup10, _, _, _, _, _, _, _, _),
1180 	[17] = PINGROUP(17, _, phase_flag, qup10, _, _, _, _, _, _),
1181 	[18] = PINGROUP(18, _, phase_flag, _, _, _, _, _, _, _),
1182 	[19] = PINGROUP(19, qup12, qup12, ddr_bist, _, _, _, _, _, _),
1183 	[20] = PINGROUP(20, qup12, qup12, ddr_bist, _, _, _, _, _, _),
1184 	[21] = PINGROUP(21, gcc_gp2, ddr_bist, _, _, _, _, _, _, _),
1185 	[22] = PINGROUP(22, gcc_gp3, ddr_bist, _, _, _, _, _, _, _),
1186 	[23] = PINGROUP(23, mdp_vsync, edp_lcd, _, _, _, _, _, _, _),
1187 	[24] = PINGROUP(24, mdp_vsync, _, _, _, _, _, _, _, _),
1188 	[25] = PINGROUP(25, qup13_f1, qup13_f2, _, _, _, _, _, _, _),
1189 	[26] = PINGROUP(26, qup13_f1, qup13_f2, _, _, _, _, _, _, _),
1190 	[27] = PINGROUP(27, qup11, qup11, mdp_vsync, pll_bist, _, qdss_gpio14, _, _, _),
1191 	[28] = PINGROUP(28, qup11, qup11, mdp_vsync, _, qdss_gpio15, _, _, _, _),
1192 	[29] = PINGROUP(29, cam_mclk0, _, _, _, _, _, _, _, _),
1193 	[30] = PINGROUP(30, cam_mclk1, _, _, _, _, _, _, _, _),
1194 	[31] = PINGROUP(31, cam_mclk2, _, _, _, _, _, _, _, _),
1195 	[32] = PINGROUP(32, cam_mclk3, _, _, _, _, _, _, _, _),
1196 	[33] = PINGROUP(33, cam_mclk4, _, _, _, _, _, _, _, _),
1197 	[34] = PINGROUP(34, cci_timer0, _, phase_flag, qdss_gpio12, _, _, _, _, _),
1198 	[35] = PINGROUP(35, cci_timer1, cci_async, _, phase_flag, qdss_gpio13, _, _, _, _),
1199 	[36] = PINGROUP(36, cci_timer2, cci_async, _, phase_flag, qdss_gpio14, _, _, _, _),
1200 	[37] = PINGROUP(37, cci_timer3, gp_pdm0, _, phase_flag, qdss_gpio15, _, _, _, _),
1201 	[38] = PINGROUP(38, cci_timer4, _, phase_flag, qdss_gpio2, _, _, _, _, _),
1202 	[39] = PINGROUP(39, cci_i2c, _, phase_flag, qdss_gpio0, _, _, _, _, _),
1203 	[40] = PINGROUP(40, cci_i2c, _, phase_flag, qdss_gpio1, _, _, _, _, _),
1204 	[41] = PINGROUP(41, cci_i2c, _, phase_flag, qdss_gpio2, _, _, _, _, _),
1205 	[42] = PINGROUP(42, cci_i2c, _, phase_flag, qdss_gpio3, _, _, _, _, _),
1206 	[43] = PINGROUP(43, cci_i2c, _, phase_flag, qdss_gpio4, _, _, _, _, _),
1207 	[44] = PINGROUP(44, cci_i2c, _, phase_flag, qdss_gpio5, _, _, _, _, _),
1208 	[45] = PINGROUP(45, qup02, _, phase_flag, qdss_gpio6, _, _, _, _, _),
1209 	[46] = PINGROUP(46, qup02, _, phase_flag, qdss_gpio7, _, _, _, _, _),
1210 	[47] = PINGROUP(47, mdp_vsync0, _, phase_flag, qdss_gpio3, _, _, _, _, _),
1211 	[48] = PINGROUP(48, cci_async, mdp_vsync1, gcc_gp1, _, phase_flag, qdss_gpio8, qup02, _, _),
1212 	[49] = PINGROUP(49, vfr_1, _, phase_flag, qdss_gpio9, _, _, _, _, _),
1213 	[50] = PINGROUP(50, _, phase_flag, qdss_gpio10, _, _, _, _, _, _),
1214 	[51] = PINGROUP(51, _, phase_flag, qdss_gpio11, _, _, _, _, _, _),
1215 	[52] = PINGROUP(52, cci_async, gp_pdm1, _, phase_flag, qdss_gpio12, _, _, _, _),
1216 	[53] = PINGROUP(53, cci_async, _, phase_flag, qdss_gpio13, _, _, _, _, _),
1217 	[54] = PINGROUP(54, _, _, _, _, _, _, _, _, _),
1218 	[55] = PINGROUP(55, _, _, _, _, _, _, _, _, _),
1219 	[56] = PINGROUP(56, qup02, mdp_vsync2, _, phase_flag, qdss_gpio10, _, _, _, _),
1220 	[57] = PINGROUP(57, qup02, mdp_vsync3, gp_pdm2, _, phase_flag, qdss_gpio11, _, _, _),
1221 	[58] = PINGROUP(58, gcc_gp1, _, _, _, _, _, _, _, _),
1222 	[59] = PINGROUP(59, _, _, _, _, _, _, _, _, _),
1223 	[60] = PINGROUP(60, audio_ref, lpass_ext, mi2s_2, _, phase_flag, _, _, _, _),
1224 	[61] = PINGROUP(61, qup01, tgu_ch0, _, phase_flag, qdss_cti, _, _, _, _),
1225 	[62] = PINGROUP(62, qup01, tgu_ch1, _, phase_flag, qdss_cti, _, _, _, _),
1226 	[63] = PINGROUP(63, qup01, tgu_ch2, _, phase_flag, qdss_gpio, _, _, _, _),
1227 	[64] = PINGROUP(64, qup01, tgu_ch3, _, phase_flag, qdss_gpio, _, _, _, _),
1228 	[65] = PINGROUP(65, mss_lte, _, qdss_gpio0, _, _, _, _, _, _),
1229 	[66] = PINGROUP(66, mss_lte, _, qdss_gpio1, _, _, _, _, _, _),
1230 	[67] = PINGROUP(67, btfm_slimbus, mi2s_1, _, phase_flag, _, _, _, _, _),
1231 	[68] = PINGROUP(68, btfm_slimbus, mi2s_1, gp_pdm0, _, phase_flag, _, _, _, _),
1232 	[69] = PINGROUP(69, _, _, _, _, _, _, _, _, _),
1233 	[70] = PINGROUP(70, _, _, _, _, _, _, _, _, _),
1234 	[71] = PINGROUP(71, _, _, _, _, _, _, _, _, _),
1235 	[72] = PINGROUP(72, mi2s_2, _, _, _, _, _, _, _, _),
1236 	[73] = PINGROUP(73, mi2s_2, _, _, _, _, _, _, _, _),
1237 	[74] = PINGROUP(74, mi2s_2, _, _, _, _, _, _, _, _),
1238 	[75] = PINGROUP(75, uim2_data, _, _, _, _, _, _, _, _),
1239 	[76] = PINGROUP(76, uim2_clk, _, _, _, _, _, _, _, _),
1240 	[77] = PINGROUP(77, uim2_reset, _, _, _, _, _, _, _, _),
1241 	[78] = PINGROUP(78, uim2_present, _, _, _, _, _, _, _, _),
1242 	[79] = PINGROUP(79, uim1_data, _, _, _, _, _, _, _, _),
1243 	[80] = PINGROUP(80, uim1_clk, _, _, _, _, _, _, _, _),
1244 	[81] = PINGROUP(81, uim1_reset, _, _, _, _, _, _, _, _),
1245 	[82] = PINGROUP(82, uim1_present, _, _, _, _, _, _, _, _),
1246 	[83] = PINGROUP(83, atest_usb, _, _, _, _, _, _, _, _),
1247 	[84] = PINGROUP(84, _, atest_usb, _, _, _, _, _, _, _),
1248 	[85] = PINGROUP(85, sd_write, _, atest_usb, _, _, _, _, _, _),
1249 	[86] = PINGROUP(86, btfm_slimbus, mi2s_1, _, qdss_cti, atest_usb, ddr_pxi0, _, _, _),
1250 	[87] = PINGROUP(87, btfm_slimbus, mi2s_1, adsp_ext, _, qdss_cti, atest_usb, ddr_pxi1, _, _),
1251 	[88] = PINGROUP(88, mi2s_0, _, qdss_gpio4, _, atest_usb, ddr_pxi2,
1252 			tsense_pwm1, tsense_pwm2, _),
1253 	[89] = PINGROUP(89, mi2s_0, agera_pll, _, qdss_gpio5, _,
1254 			vsense_trigger, atest_usb, ddr_pxi3, _),
1255 	[90] = PINGROUP(90, mi2s_0, jitter_bist, _, qdss_gpio6, _,
1256 			wlan1_adc0, atest_usb, ddr_pxi0, _),
1257 	[91] = PINGROUP(91, mi2s_0, _, qdss_gpio7, _, wlan2_adc0,
1258 			atest_usb, ddr_pxi1, _, _),
1259 	[92] = PINGROUP(92, _, qdss_gpio8, atest_tsens, wlan1_adc1,
1260 			atest_usb, ddr_pxi2, _, _, _),
1261 	[93] = PINGROUP(93, mclk, lpass_ext, _, qdss_gpio9, atest_tsens2,
1262 			wlan2_adc1, ddr_pxi3, _, _),
1263 	[94] = PINGROUP(94, _, _, _, _, _, _, _, _, _),
1264 	[95] = PINGROUP(95, ldo_en, _, atest_char, _, _, _, _, _, _),
1265 	[96] = PINGROUP(96, ldo_update, _, atest_char0, _, _, _, _, _, _),
1266 	[97] = PINGROUP(97, prng_rosc, _, atest_char1, _, _, _, _, _, _),
1267 	[98] = PINGROUP(98, _, atest_char2, _, _, _, _, _, _, _),
1268 	[99] = PINGROUP(99, _, atest_char3, _, _, _, _, _, _, _),
1269 	[100] = PINGROUP(100, _, _, _, _, _, _, _, _, _),
1270 	[101] = PINGROUP(101, nav_gpio, nav_pps, nav_pps, gps_tx, _, _, _, _, _),
1271 	[102] = PINGROUP(102, nav_gpio, nav_pps, nav_pps, gps_tx, _, _, _, _, _),
1272 	[103] = PINGROUP(103, qlink0_wmss, _, _, _, _, _, _, _, _),
1273 	[104] = PINGROUP(104, qlink0_request, _, _, _, _, _, _, _, _),
1274 	[105] = PINGROUP(105, qlink0_enable, _, _, _, _, _, _, _, _),
1275 	[106] = PINGROUP(106, qlink1_wmss, _, _, _, _, _, _, _, _),
1276 	[107] = PINGROUP(107, qlink1_request, gps_tx, _, _, _, _, _, _, _),
1277 	[108] = PINGROUP(108, qlink1_enable, gps_tx, _, _, _, _, _, _, _),
1278 	[109] = PINGROUP(109, rffe0_data, _, _, _, _, _, _, _, _),
1279 	[110] = PINGROUP(110, rffe0_clk, _, _, _, _, _, _, _, _),
1280 	[111] = PINGROUP(111, rffe1_data, _, _, _, _, _, _, _, _),
1281 	[112] = PINGROUP(112, rffe1_clk, _, _, _, _, _, _, _, _),
1282 	[113] = PINGROUP(113, rffe2_data, _, _, _, _, _, _, _, _),
1283 	[114] = PINGROUP(114, rffe2_clk, _, _, _, _, _, _, _, _),
1284 	[115] = PINGROUP(115, rffe3_data, _, _, _, _, _, _, _, _),
1285 	[116] = PINGROUP(116, rffe3_clk, _, _, _, _, _, _, _, _),
1286 	[117] = PINGROUP(117, rffe4_data, _, _, _, _, _, _, _, _),
1287 	[118] = PINGROUP(118, rffe4_clk, _, pa_indicator, dp_hot, _, _, _, _, _),
1288 	[119] = PINGROUP(119, _, _, _, _, _, _, _, _, _),
1289 	[120] = PINGROUP(120, _, _, _, _, _, _, _, _, _),
1290 	[121] = PINGROUP(121, _, _, _, _, _, _, _, _, _),
1291 	[122] = PINGROUP(122, pcie0_clk, _, _, _, _, _, _, _, _),
1292 	[123] = PINGROUP(123, _, _, _, _, _, _, _, _, _),
1293 	[124] = PINGROUP(124, usb_phy, _, _, _, _, _, _, _, _),
1294 	[125] = PINGROUP(125, _, _, _, _, _, _, _, _, _),
1295 	[126] = PINGROUP(126, _, _, _, _, _, _, _, _, _),
1296 	[127] = PINGROUP(127, _, _, _, _, _, _, _, _, _),
1297 	[128] = PINGROUP(128, _, _, _, _, _, _, _, _, _),
1298 	[129] = PINGROUP(129, _, _, _, _, _, _, _, _, _),
1299 	[130] = PINGROUP(130, _, _, _, _, _, _, _, _, _),
1300 	[131] = PINGROUP(131, _, _, _, _, _, _, _, _, _),
1301 	[132] = PINGROUP(132, _, _, _, _, _, _, _, _, _),
1302 	[133] = PINGROUP(133, _, _, _, _, _, _, _, _, _),
1303 	[134] = PINGROUP(134, _, _, _, _, _, _, _, _, _),
1304 	[135] = PINGROUP(135, _, _, _, _, _, _, _, _, _),
1305 	[136] = PINGROUP(136, _, _, _, _, _, _, _, _, _),
1306 	[137] = PINGROUP(137, _, _, _, _, _, _, _, _, _),
1307 	[138] = PINGROUP(138, _, _, _, _, _, _, _, _, _),
1308 	[139] = PINGROUP(139, _, _, _, _, _, _, _, _, _),
1309 	[140] = PINGROUP(140, _, _, _, _, _, _, _, _, _),
1310 	[141] = PINGROUP(141, _, _, _, _, _, _, _, _, _),
1311 	[142] = PINGROUP(142, _, _, _, _, _, _, _, _, _),
1312 	[143] = PINGROUP(143, _, _, _, _, _, _, _, _, _),
1313 	[144] = PINGROUP(144, _, _, _, _, _, _, _, _, _),
1314 	[145] = PINGROUP(145, _, _, _, _, _, _, _, _, _),
1315 	[146] = PINGROUP(146, _, _, _, _, _, _, _, _, _),
1316 	[147] = PINGROUP(147, _, _, _, _, _, _, _, _, _),
1317 	[148] = PINGROUP(148, _, _, _, _, _, _, _, _, _),
1318 	[149] = PINGROUP(149, _, _, _, _, _, _, _, _, _),
1319 	[150] = PINGROUP(150, _, _, _, _, _, _, _, _, _),
1320 	[151] = PINGROUP(151, _, _, _, _, _, _, _, _, _),
1321 	[152] = PINGROUP(152, _, _, _, _, _, _, _, _, _),
1322 	[153] = PINGROUP(153, _, _, _, _, _, _, _, _, _),
1323 	[154] = PINGROUP(154, _, _, _, _, _, _, _, _, _),
1324 	[155] = PINGROUP(155, _, _, _, _, _, _, _, _, _),
1325 	[156] = UFS_RESET(ufs_reset, 0xae000),
1326 	[157] = SDC_PINGROUP(sdc1_rclk, 0xa1000, 15, 0),
1327 	[158] = SDC_PINGROUP(sdc1_clk, 0xa0000, 13, 6),
1328 	[159] = SDC_PINGROUP(sdc1_cmd, 0xa0000, 11, 3),
1329 	[160] = SDC_PINGROUP(sdc1_data, 0xa0000, 9, 0),
1330 	[161] = SDC_PINGROUP(sdc2_clk, 0xa2000, 14, 6),
1331 	[162] = SDC_PINGROUP(sdc2_cmd, 0xa2000, 11, 3),
1332 	[163] = SDC_PINGROUP(sdc2_data, 0xa2000, 9, 0),
1333 };
1334 
1335 static const struct msm_gpio_wakeirq_map sm6350_pdc_map[] = {
1336 	{ 3, 126 }, { 4, 151 }, { 7, 58 }, { 8, 113 }, { 9, 66 }, { 11, 106 },
1337 	{ 12, 59 }, { 13, 112 }, { 16, 73 }, { 17, 74 }, { 18, 75 }, { 19, 76 },
1338 	{ 21, 130 }, { 22, 96 }, { 23, 146 }, { 24, 114 }, { 25, 83 },
1339 	{ 27, 84 }, { 28, 85 }, { 34, 147 }, { 35, 92 }, { 36, 93 }, { 37, 94 },
1340 	{ 38, 68 }, { 48, 100 }, { 50, 57 }, { 51, 81 }, { 52, 80 }, { 53, 69 },
1341 	{ 54, 71 }, { 55, 70 }, { 57, 152 }, { 58, 115 }, { 59, 116 }, { 60, 117 },
1342 	{ 61, 118 }, { 62, 119 }, { 64, 121 }, { 66, 127 }, { 67, 128 },
1343 	{ 69, 60 }, { 73, 78 }, { 78, 135 }, { 82, 138 }, { 83, 140 },
1344 	{ 84, 141 }, { 85, 98 }, { 87, 88 }, { 88, 107 }, { 89, 109 },
1345 	{ 90, 110 }, { 91, 111 }, { 92, 149 }, { 93, 101 }, { 94, 61 },
1346 	{ 95, 65 }, { 96, 95 }, { 97, 72 }, { 98, 145 }, { 99, 150 },
1347 	{ 100, 108 }, { 104, 129 }, { 107, 131 }, { 110, 132 }, { 112, 133 },
1348 	{ 114, 134 }, { 116, 136 }, { 118, 137 }, { 122, 97 }, { 123, 99 },
1349 	{ 124, 148 }, { 125, 82 }, { 128, 144 }, { 129, 86 }, { 131, 87 },
1350 	{ 133, 142 }, { 134, 143 }, { 136, 102 }, { 137, 91 }, { 138, 77 },
1351 	{ 139, 79 }, { 140, 90 }, { 142, 103 }, { 144, 105 }, { 147, 104 },
1352 	{ 153, 120 }, { 155, 67 }
1353 };
1354 
1355 static const struct msm_pinctrl_soc_data sm6350_tlmm = {
1356 	.pins = sm6350_pins,
1357 	.npins = ARRAY_SIZE(sm6350_pins),
1358 	.functions = sm6350_functions,
1359 	.nfunctions = ARRAY_SIZE(sm6350_functions),
1360 	.groups = sm6350_groups,
1361 	.ngroups = ARRAY_SIZE(sm6350_groups),
1362 	.ngpios = 157,
1363 	.wakeirq_map = sm6350_pdc_map,
1364 	.nwakeirq_map = ARRAY_SIZE(sm6350_pdc_map),
1365 	.wakeirq_dual_edge_errata = true,
1366 };
1367 
sm6350_tlmm_probe(struct platform_device * pdev)1368 static int sm6350_tlmm_probe(struct platform_device *pdev)
1369 {
1370 	return msm_pinctrl_probe(pdev, &sm6350_tlmm);
1371 }
1372 
1373 static const struct of_device_id sm6350_tlmm_of_match[] = {
1374 	{ .compatible = "qcom,sm6350-tlmm" },
1375 	{ },
1376 };
1377 
1378 static struct platform_driver sm6350_tlmm_driver = {
1379 	.driver = {
1380 		.name = "sm6350-tlmm",
1381 		.of_match_table = sm6350_tlmm_of_match,
1382 	},
1383 	.probe = sm6350_tlmm_probe,
1384 	.remove = msm_pinctrl_remove,
1385 };
1386 
sm6350_tlmm_init(void)1387 static int __init sm6350_tlmm_init(void)
1388 {
1389 	return platform_driver_register(&sm6350_tlmm_driver);
1390 }
1391 arch_initcall(sm6350_tlmm_init);
1392 
sm6350_tlmm_exit(void)1393 static void __exit sm6350_tlmm_exit(void)
1394 {
1395 	platform_driver_unregister(&sm6350_tlmm_driver);
1396 }
1397 module_exit(sm6350_tlmm_exit);
1398 
1399 MODULE_DESCRIPTION("QTI SM6350 TLMM driver");
1400 MODULE_LICENSE("GPL v2");
1401 MODULE_DEVICE_TABLE(of, sm6350_tlmm_of_match);
1402