1 /*
2  * Allwinner A64 SoCs pinctrl driver.
3  *
4  * Copyright (C) 2016 - ARM Ltd.
5  * Author: Andre Przywara <andre.przywara@arm.com>
6  *
7  * Based on pinctrl-sun7i-a20.c, which is:
8  * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
9  *
10  * This file is licensed under the terms of the GNU General Public
11  * License version 2.  This program is licensed "as is" without any
12  * warranty of any kind, whether express or implied.
13  */
14 
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/of.h>
18 #include <linux/of_device.h>
19 #include <linux/pinctrl/pinctrl.h>
20 
21 #include "pinctrl-sunxi.h"
22 
23 static const struct sunxi_desc_pin a64_pins[] = {
24 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
25 		  SUNXI_FUNCTION(0x0, "gpio_in"),
26 		  SUNXI_FUNCTION(0x1, "gpio_out"),
27 		  SUNXI_FUNCTION(0x2, "uart2"),		/* TX */
28 		  SUNXI_FUNCTION(0x4, "jtag"),		/* MS0 */
29 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),	/* EINT0 */
30 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
31 		  SUNXI_FUNCTION(0x0, "gpio_in"),
32 		  SUNXI_FUNCTION(0x1, "gpio_out"),
33 		  SUNXI_FUNCTION(0x2, "uart2"),		/* RX */
34 		  SUNXI_FUNCTION(0x4, "jtag"),		/* CK0 */
35 		  SUNXI_FUNCTION(0x5, "sim"),		/* VCCEN */
36 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),		/* EINT1 */
37 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
38 		  SUNXI_FUNCTION(0x0, "gpio_in"),
39 		  SUNXI_FUNCTION(0x1, "gpio_out"),
40 		  SUNXI_FUNCTION(0x2, "uart2"),		/* RTS */
41 		  SUNXI_FUNCTION(0x4, "jtag"),		/* DO0 */
42 		  SUNXI_FUNCTION(0x5, "sim"),		/* VPPEN */
43 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),		/* EINT2 */
44 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
45 		  SUNXI_FUNCTION(0x0, "gpio_in"),
46 		  SUNXI_FUNCTION(0x1, "gpio_out"),
47 		  SUNXI_FUNCTION(0x2, "uart2"),		/* CTS */
48 		  SUNXI_FUNCTION(0x3, "i2s0"),		/* MCLK */
49 		  SUNXI_FUNCTION(0x4, "jtag"),		/* DI0 */
50 		  SUNXI_FUNCTION(0x5, "sim"),		/* VPPPP */
51 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),		/* EINT3 */
52 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
53 		  SUNXI_FUNCTION(0x0, "gpio_in"),
54 		  SUNXI_FUNCTION(0x1, "gpio_out"),
55 		  SUNXI_FUNCTION(0x2, "aif2"),		/* SYNC */
56 		  SUNXI_FUNCTION(0x3, "i2s0"),		/* SYNC */
57 		  SUNXI_FUNCTION(0x5, "sim"),		/* CLK */
58 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),		/* EINT4 */
59 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
60 		  SUNXI_FUNCTION(0x0, "gpio_in"),
61 		  SUNXI_FUNCTION(0x1, "gpio_out"),
62 		  SUNXI_FUNCTION(0x2, "aif2"),		/* BCLK */
63 		  SUNXI_FUNCTION(0x3, "i2s0"),		/* BCLK */
64 		  SUNXI_FUNCTION(0x5, "sim"),		/* DATA */
65 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),		/* EINT5 */
66 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
67 		  SUNXI_FUNCTION(0x0, "gpio_in"),
68 		  SUNXI_FUNCTION(0x1, "gpio_out"),
69 		  SUNXI_FUNCTION(0x2, "aif2"),		/* DOUT */
70 		  SUNXI_FUNCTION(0x3, "i2s0"),		/* DOUT */
71 		  SUNXI_FUNCTION(0x5, "sim"),		/* RST */
72 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),		/* EINT6 */
73 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
74 		  SUNXI_FUNCTION(0x0, "gpio_in"),
75 		  SUNXI_FUNCTION(0x1, "gpio_out"),
76 		  SUNXI_FUNCTION(0x2, "aif2"),		/* DIN */
77 		  SUNXI_FUNCTION(0x3, "i2s0"),		/* DIN */
78 		  SUNXI_FUNCTION(0x5, "sim"),		/* DET */
79 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),		/* EINT7 */
80 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
81 		  SUNXI_FUNCTION(0x0, "gpio_in"),
82 		  SUNXI_FUNCTION(0x1, "gpio_out"),
83 		  SUNXI_FUNCTION(0x4, "uart0"),		/* TX */
84 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),		/* EINT8 */
85 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
86 		  SUNXI_FUNCTION(0x0, "gpio_in"),
87 		  SUNXI_FUNCTION(0x1, "gpio_out"),
88 		  SUNXI_FUNCTION(0x4, "uart0"),		/* RX */
89 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),		/* EINT9 */
90 	/* Hole */
91 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
92 		  SUNXI_FUNCTION(0x0, "gpio_in"),
93 		  SUNXI_FUNCTION(0x1, "gpio_out"),
94 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NWE */
95 		  SUNXI_FUNCTION(0x4, "spi0")),		/* MOSI */
96 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
97 		  SUNXI_FUNCTION(0x0, "gpio_in"),
98 		  SUNXI_FUNCTION(0x1, "gpio_out"),
99 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NALE */
100 		  SUNXI_FUNCTION(0x3, "mmc2"),		/* DS */
101 		  SUNXI_FUNCTION(0x4, "spi0")),		/* MISO */
102 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
103 		  SUNXI_FUNCTION(0x0, "gpio_in"),
104 		  SUNXI_FUNCTION(0x1, "gpio_out"),
105 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NCLE */
106 		  SUNXI_FUNCTION(0x4, "spi0")),		/* SCK */
107 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
108 		  SUNXI_FUNCTION(0x0, "gpio_in"),
109 		  SUNXI_FUNCTION(0x1, "gpio_out"),
110 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NCE1 */
111 		  SUNXI_FUNCTION(0x4, "spi0")),		/* CS */
112 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
113 		  SUNXI_FUNCTION(0x0, "gpio_in"),
114 		  SUNXI_FUNCTION(0x1, "gpio_out"),
115 		  SUNXI_FUNCTION(0x2, "nand0")),	/* NCE0 */
116 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
117 		  SUNXI_FUNCTION(0x0, "gpio_in"),
118 		  SUNXI_FUNCTION(0x1, "gpio_out"),
119 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NRE# */
120 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* CLK */
121 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
122 		  SUNXI_FUNCTION(0x0, "gpio_in"),
123 		  SUNXI_FUNCTION(0x1, "gpio_out"),
124 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NRB0 */
125 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* CMD */
126 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
127 		  SUNXI_FUNCTION(0x0, "gpio_in"),
128 		  SUNXI_FUNCTION(0x1, "gpio_out"),
129 		  SUNXI_FUNCTION(0x2, "nand0")),	/* NRB1 */
130 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
131 		  SUNXI_FUNCTION(0x0, "gpio_in"),
132 		  SUNXI_FUNCTION(0x1, "gpio_out"),
133 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ0 */
134 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D0 */
135 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
136 		  SUNXI_FUNCTION(0x0, "gpio_in"),
137 		  SUNXI_FUNCTION(0x1, "gpio_out"),
138 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ1 */
139 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D1 */
140 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
141 		  SUNXI_FUNCTION(0x0, "gpio_in"),
142 		  SUNXI_FUNCTION(0x1, "gpio_out"),
143 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ2 */
144 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D2 */
145 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
146 		  SUNXI_FUNCTION(0x0, "gpio_in"),
147 		  SUNXI_FUNCTION(0x1, "gpio_out"),
148 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ3 */
149 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D3 */
150 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
151 		  SUNXI_FUNCTION(0x0, "gpio_in"),
152 		  SUNXI_FUNCTION(0x1, "gpio_out"),
153 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ4 */
154 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D4 */
155 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
156 		  SUNXI_FUNCTION(0x0, "gpio_in"),
157 		  SUNXI_FUNCTION(0x1, "gpio_out"),
158 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ5 */
159 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D5 */
160 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
161 		  SUNXI_FUNCTION(0x0, "gpio_in"),
162 		  SUNXI_FUNCTION(0x1, "gpio_out"),
163 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ6 */
164 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D6 */
165 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
166 		  SUNXI_FUNCTION(0x0, "gpio_in"),
167 		  SUNXI_FUNCTION(0x1, "gpio_out"),
168 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ7 */
169 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D7 */
170 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
171 		  SUNXI_FUNCTION(0x0, "gpio_in"),
172 		  SUNXI_FUNCTION(0x1, "gpio_out"),
173 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQS */
174 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* RST */
175 	/* Hole */
176 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
177 		  SUNXI_FUNCTION(0x0, "gpio_in"),
178 		  SUNXI_FUNCTION(0x1, "gpio_out"),
179 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D2 */
180 		  SUNXI_FUNCTION(0x3, "uart3"),		/* TX */
181 		  SUNXI_FUNCTION(0x4, "spi1"),		/* CS */
182 		  SUNXI_FUNCTION(0x5, "ccir")),		/* CLK */
183 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
184 		  SUNXI_FUNCTION(0x0, "gpio_in"),
185 		  SUNXI_FUNCTION(0x1, "gpio_out"),
186 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D3 */
187 		  SUNXI_FUNCTION(0x3, "uart3"),		/* RX */
188 		  SUNXI_FUNCTION(0x4, "spi1"),		/* CLK */
189 		  SUNXI_FUNCTION(0x5, "ccir")),		/* DE */
190 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
191 		  SUNXI_FUNCTION(0x0, "gpio_in"),
192 		  SUNXI_FUNCTION(0x1, "gpio_out"),
193 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D4 */
194 		  SUNXI_FUNCTION(0x3, "uart4"),		/* TX */
195 		  SUNXI_FUNCTION(0x4, "spi1"),		/* MOSI */
196 		  SUNXI_FUNCTION(0x5, "ccir")),		/* HSYNC */
197 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
198 		  SUNXI_FUNCTION(0x0, "gpio_in"),
199 		  SUNXI_FUNCTION(0x1, "gpio_out"),
200 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D5 */
201 		  SUNXI_FUNCTION(0x3, "uart4"),		/* RX */
202 		  SUNXI_FUNCTION(0x4, "spi1"),		/* MISO */
203 		  SUNXI_FUNCTION(0x5, "ccir")),		/* VSYNC */
204 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
205 		  SUNXI_FUNCTION(0x0, "gpio_in"),
206 		  SUNXI_FUNCTION(0x1, "gpio_out"),
207 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D6 */
208 		  SUNXI_FUNCTION(0x3, "uart4"),		/* RTS */
209 		  SUNXI_FUNCTION(0x5, "ccir")),		/* D0 */
210 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
211 		  SUNXI_FUNCTION(0x0, "gpio_in"),
212 		  SUNXI_FUNCTION(0x1, "gpio_out"),
213 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D7 */
214 		  SUNXI_FUNCTION(0x3, "uart4"),		/* CTS */
215 		  SUNXI_FUNCTION(0x5, "ccir")),		/* D1 */
216 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
217 		  SUNXI_FUNCTION(0x0, "gpio_in"),
218 		  SUNXI_FUNCTION(0x1, "gpio_out"),
219 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D10 */
220 		  SUNXI_FUNCTION(0x5, "ccir")),		/* D2 */
221 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
222 		  SUNXI_FUNCTION(0x0, "gpio_in"),
223 		  SUNXI_FUNCTION(0x1, "gpio_out"),
224 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D11 */
225 		  SUNXI_FUNCTION(0x5, "ccir")),		/* D3 */
226 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
227 		  SUNXI_FUNCTION(0x0, "gpio_in"),
228 		  SUNXI_FUNCTION(0x1, "gpio_out"),
229 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D12 */
230 		  SUNXI_FUNCTION(0x4, "emac"),		/* ERXD3 */
231 		  SUNXI_FUNCTION(0x5, "ccir")),		/* D4 */
232 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
233 		  SUNXI_FUNCTION(0x0, "gpio_in"),
234 		  SUNXI_FUNCTION(0x1, "gpio_out"),
235 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D13 */
236 		  SUNXI_FUNCTION(0x4, "emac"),		/* ERXD2 */
237 		  SUNXI_FUNCTION(0x5, "ccir")),		/* D5 */
238 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
239 		  SUNXI_FUNCTION(0x0, "gpio_in"),
240 		  SUNXI_FUNCTION(0x1, "gpio_out"),
241 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D14 */
242 		  SUNXI_FUNCTION(0x4, "emac")),		/* ERXD1 */
243 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
244 		  SUNXI_FUNCTION(0x0, "gpio_in"),
245 		  SUNXI_FUNCTION(0x1, "gpio_out"),
246 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D15 */
247 		  SUNXI_FUNCTION(0x4, "emac")),		/* ERXD0 */
248 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
249 		  SUNXI_FUNCTION(0x0, "gpio_in"),
250 		  SUNXI_FUNCTION(0x1, "gpio_out"),
251 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D18 */
252 		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VP0 */
253 		  SUNXI_FUNCTION(0x4, "emac")),		/* ERXCK */
254 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
255 		  SUNXI_FUNCTION(0x0, "gpio_in"),
256 		  SUNXI_FUNCTION(0x1, "gpio_out"),
257 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D19 */
258 		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VN0 */
259 		  SUNXI_FUNCTION(0x4, "emac")),		/* ERXCTL */
260 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
261 		  SUNXI_FUNCTION(0x0, "gpio_in"),
262 		  SUNXI_FUNCTION(0x1, "gpio_out"),
263 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D20 */
264 		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VP1 */
265 		  SUNXI_FUNCTION(0x4, "emac")),		/* ENULL */
266 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
267 		  SUNXI_FUNCTION(0x0, "gpio_in"),
268 		  SUNXI_FUNCTION(0x1, "gpio_out"),
269 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D21 */
270 		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VN1 */
271 		  SUNXI_FUNCTION(0x4, "emac"),		/* ETXD3 */
272 		  SUNXI_FUNCTION(0x5, "ccir")),		/* D6 */
273 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
274 		  SUNXI_FUNCTION(0x0, "gpio_in"),
275 		  SUNXI_FUNCTION(0x1, "gpio_out"),
276 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D22 */
277 		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VP2 */
278 		  SUNXI_FUNCTION(0x4, "emac"),		/* ETXD2 */
279 		  SUNXI_FUNCTION(0x5, "ccir")),		/* D7 */
280 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
281 		  SUNXI_FUNCTION(0x0, "gpio_in"),
282 		  SUNXI_FUNCTION(0x1, "gpio_out"),
283 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D23 */
284 		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VN2 */
285 		  SUNXI_FUNCTION(0x4, "emac")),		/* ETXD1 */
286 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
287 		  SUNXI_FUNCTION(0x0, "gpio_in"),
288 		  SUNXI_FUNCTION(0x1, "gpio_out"),
289 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* CLK */
290 		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VPC */
291 		  SUNXI_FUNCTION(0x4, "emac")),		/* ETXD0 */
292 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
293 		  SUNXI_FUNCTION(0x0, "gpio_in"),
294 		  SUNXI_FUNCTION(0x1, "gpio_out"),
295 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* DE */
296 		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VNC */
297 		  SUNXI_FUNCTION(0x4, "emac")),		/* ETXCK */
298 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
299 		  SUNXI_FUNCTION(0x0, "gpio_in"),
300 		  SUNXI_FUNCTION(0x1, "gpio_out"),
301 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* HSYNC */
302 		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VP3 */
303 		  SUNXI_FUNCTION(0x4, "emac")),		/* ETXCTL */
304 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
305 		  SUNXI_FUNCTION(0x0, "gpio_in"),
306 		  SUNXI_FUNCTION(0x1, "gpio_out"),
307 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* VSYNC */
308 		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VN3 */
309 		  SUNXI_FUNCTION(0x4, "emac")),		/* ECLKIN */
310 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
311 		  SUNXI_FUNCTION(0x0, "gpio_in"),
312 		  SUNXI_FUNCTION(0x1, "gpio_out"),
313 		  SUNXI_FUNCTION(0x2, "pwm"),		/* PWM0 */
314 		  SUNXI_FUNCTION(0x4, "emac")),		/* EMDC */
315 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
316 		  SUNXI_FUNCTION(0x0, "gpio_in"),
317 		  SUNXI_FUNCTION(0x1, "gpio_out"),
318 		  SUNXI_FUNCTION(0x4, "emac")),		/* EMDIO */
319 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
320 		  SUNXI_FUNCTION(0x0, "gpio_in"),
321 		  SUNXI_FUNCTION(0x1, "gpio_out")),
322 	/* Hole */
323 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
324 		  SUNXI_FUNCTION(0x0, "gpio_in"),
325 		  SUNXI_FUNCTION(0x1, "gpio_out"),
326 		  SUNXI_FUNCTION(0x2, "csi"),		/* PCK */
327 		  SUNXI_FUNCTION(0x4, "ts")),		/* CLK */
328 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
329 		  SUNXI_FUNCTION(0x0, "gpio_in"),
330 		  SUNXI_FUNCTION(0x1, "gpio_out"),
331 		  SUNXI_FUNCTION(0x2, "csi"),		/* CK */
332 		  SUNXI_FUNCTION(0x4, "ts")),		/* ERR */
333 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
334 		  SUNXI_FUNCTION(0x0, "gpio_in"),
335 		  SUNXI_FUNCTION(0x1, "gpio_out"),
336 		  SUNXI_FUNCTION(0x2, "csi"),		/* HSYNC */
337 		  SUNXI_FUNCTION(0x4, "ts")),		/* SYNC */
338 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
339 		  SUNXI_FUNCTION(0x0, "gpio_in"),
340 		  SUNXI_FUNCTION(0x1, "gpio_out"),
341 		  SUNXI_FUNCTION(0x2, "csi"),		/* VSYNC */
342 		  SUNXI_FUNCTION(0x4, "ts")),		/* DVLD */
343 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
344 		  SUNXI_FUNCTION(0x0, "gpio_in"),
345 		  SUNXI_FUNCTION(0x1, "gpio_out"),
346 		  SUNXI_FUNCTION(0x2, "csi"),		/* D0 */
347 		  SUNXI_FUNCTION(0x4, "ts")),		/* D0 */
348 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
349 		  SUNXI_FUNCTION(0x0, "gpio_in"),
350 		  SUNXI_FUNCTION(0x1, "gpio_out"),
351 		  SUNXI_FUNCTION(0x2, "csi"),		/* D1 */
352 		  SUNXI_FUNCTION(0x4, "ts")),		/* D1 */
353 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
354 		  SUNXI_FUNCTION(0x0, "gpio_in"),
355 		  SUNXI_FUNCTION(0x1, "gpio_out"),
356 		  SUNXI_FUNCTION(0x2, "csi"),		/* D2 */
357 		  SUNXI_FUNCTION(0x4, "ts")),		/* D2 */
358 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
359 		  SUNXI_FUNCTION(0x0, "gpio_in"),
360 		  SUNXI_FUNCTION(0x1, "gpio_out"),
361 		  SUNXI_FUNCTION(0x2, "csi"),		/* D3 */
362 		  SUNXI_FUNCTION(0x4, "ts")),		/* D3 */
363 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
364 		  SUNXI_FUNCTION(0x0, "gpio_in"),
365 		  SUNXI_FUNCTION(0x1, "gpio_out"),
366 		  SUNXI_FUNCTION(0x2, "csi"),		/* D4 */
367 		  SUNXI_FUNCTION(0x4, "ts")),		/* D4 */
368 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
369 		  SUNXI_FUNCTION(0x0, "gpio_in"),
370 		  SUNXI_FUNCTION(0x1, "gpio_out"),
371 		  SUNXI_FUNCTION(0x2, "csi"),		/* D5 */
372 		  SUNXI_FUNCTION(0x4, "ts")),		/* D5 */
373 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
374 		  SUNXI_FUNCTION(0x0, "gpio_in"),
375 		  SUNXI_FUNCTION(0x1, "gpio_out"),
376 		  SUNXI_FUNCTION(0x2, "csi"),		/* D6 */
377 		  SUNXI_FUNCTION(0x4, "ts")),		/* D6 */
378 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
379 		  SUNXI_FUNCTION(0x0, "gpio_in"),
380 		  SUNXI_FUNCTION(0x1, "gpio_out"),
381 		  SUNXI_FUNCTION(0x2, "csi"),		/* D7 */
382 		  SUNXI_FUNCTION(0x4, "ts")),		/* D7 */
383 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
384 		  SUNXI_FUNCTION(0x0, "gpio_in"),
385 		  SUNXI_FUNCTION(0x1, "gpio_out"),
386 		  SUNXI_FUNCTION(0x2, "csi")),		/* SCK */
387 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
388 		  SUNXI_FUNCTION(0x0, "gpio_in"),
389 		  SUNXI_FUNCTION(0x1, "gpio_out"),
390 		  SUNXI_FUNCTION(0x2, "csi")),		/* SDA */
391 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
392 		  SUNXI_FUNCTION(0x0, "gpio_in"),
393 		  SUNXI_FUNCTION(0x1, "gpio_out"),
394 		  SUNXI_FUNCTION(0x2, "pll"),		/* LOCK_DBG */
395 		  SUNXI_FUNCTION(0x3, "i2c2")),		/* SCK */
396 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
397 		  SUNXI_FUNCTION(0x0, "gpio_in"),
398 		  SUNXI_FUNCTION(0x1, "gpio_out"),
399 		  SUNXI_FUNCTION(0x3, "i2c2")),		/* SDA */
400 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
401 		  SUNXI_FUNCTION(0x0, "gpio_in"),
402 		  SUNXI_FUNCTION(0x1, "gpio_out")),
403 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
404 		  SUNXI_FUNCTION(0x0, "gpio_in"),
405 		  SUNXI_FUNCTION(0x1, "gpio_out")),
406 	/* Hole */
407 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
408 		  SUNXI_FUNCTION(0x0, "gpio_in"),
409 		  SUNXI_FUNCTION(0x1, "gpio_out"),
410 		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D1 */
411 		  SUNXI_FUNCTION(0x3, "jtag")),		/* MSI */
412 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
413 		  SUNXI_FUNCTION(0x0, "gpio_in"),
414 		  SUNXI_FUNCTION(0x1, "gpio_out"),
415 		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D0 */
416 		  SUNXI_FUNCTION(0x3, "jtag")),		/* DI1 */
417 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
418 		  SUNXI_FUNCTION(0x0, "gpio_in"),
419 		  SUNXI_FUNCTION(0x1, "gpio_out"),
420 		  SUNXI_FUNCTION(0x2, "mmc0"),		/* CLK */
421 		  SUNXI_FUNCTION(0x3, "uart0")),	/* TX */
422 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
423 		  SUNXI_FUNCTION(0x0, "gpio_in"),
424 		  SUNXI_FUNCTION(0x1, "gpio_out"),
425 		  SUNXI_FUNCTION(0x2, "mmc0"),		/* CMD */
426 		  SUNXI_FUNCTION(0x3, "jtag")),		/* DO1 */
427 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
428 		  SUNXI_FUNCTION(0x0, "gpio_in"),
429 		  SUNXI_FUNCTION(0x1, "gpio_out"),
430 		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D3 */
431 		  SUNXI_FUNCTION(0x3, "uart0")),	/* RX */
432 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
433 		  SUNXI_FUNCTION(0x0, "gpio_in"),
434 		  SUNXI_FUNCTION(0x1, "gpio_out"),
435 		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D2 */
436 		  SUNXI_FUNCTION(0x3, "jtag")),		/* CK1 */
437 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
438 		  SUNXI_FUNCTION(0x0, "gpio_in"),
439 		  SUNXI_FUNCTION(0x1, "gpio_out")),
440 	/* Hole */
441 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
442 		  SUNXI_FUNCTION(0x0, "gpio_in"),
443 		  SUNXI_FUNCTION(0x1, "gpio_out"),
444 		  SUNXI_FUNCTION(0x2, "mmc1"),		/* CLK */
445 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),	/* EINT0 */
446 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
447 		  SUNXI_FUNCTION(0x0, "gpio_in"),
448 		  SUNXI_FUNCTION(0x1, "gpio_out"),
449 		  SUNXI_FUNCTION(0x2, "mmc1"),		/* CMD */
450 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),	/* EINT1 */
451 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
452 		  SUNXI_FUNCTION(0x0, "gpio_in"),
453 		  SUNXI_FUNCTION(0x1, "gpio_out"),
454 		  SUNXI_FUNCTION(0x2, "mmc1"),		/* D0 */
455 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),	/* EINT2 */
456 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
457 		  SUNXI_FUNCTION(0x0, "gpio_in"),
458 		  SUNXI_FUNCTION(0x1, "gpio_out"),
459 		  SUNXI_FUNCTION(0x2, "mmc1"),		/* D1 */
460 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),	/* EINT3 */
461 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
462 		  SUNXI_FUNCTION(0x0, "gpio_in"),
463 		  SUNXI_FUNCTION(0x1, "gpio_out"),
464 		  SUNXI_FUNCTION(0x2, "mmc1"),		/* D2 */
465 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),	/* EINT4 */
466 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
467 		  SUNXI_FUNCTION(0x0, "gpio_in"),
468 		  SUNXI_FUNCTION(0x1, "gpio_out"),
469 		  SUNXI_FUNCTION(0x2, "mmc1"),		/* D3 */
470 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),	/* EINT5 */
471 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
472 		  SUNXI_FUNCTION(0x0, "gpio_in"),
473 		  SUNXI_FUNCTION(0x1, "gpio_out"),
474 		  SUNXI_FUNCTION(0x2, "uart1"),		/* TX */
475 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),	/* EINT6 */
476 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
477 		  SUNXI_FUNCTION(0x0, "gpio_in"),
478 		  SUNXI_FUNCTION(0x1, "gpio_out"),
479 		  SUNXI_FUNCTION(0x2, "uart1"),		/* RX */
480 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)),	/* EINT7 */
481 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
482 		  SUNXI_FUNCTION(0x0, "gpio_in"),
483 		  SUNXI_FUNCTION(0x1, "gpio_out"),
484 		  SUNXI_FUNCTION(0x2, "uart1"),		/* RTS */
485 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)),	/* EINT8 */
486 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
487 		  SUNXI_FUNCTION(0x0, "gpio_in"),
488 		  SUNXI_FUNCTION(0x1, "gpio_out"),
489 		  SUNXI_FUNCTION(0x2, "uart1"),		/* CTS */
490 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)),	/* EINT9 */
491 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
492 		  SUNXI_FUNCTION(0x0, "gpio_in"),
493 		  SUNXI_FUNCTION(0x1, "gpio_out"),
494 		  SUNXI_FUNCTION(0x2, "aif3"),		/* SYNC */
495 		  SUNXI_FUNCTION(0x3, "i2s1"),		/* SYNC */
496 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)),	/* EINT10 */
497 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
498 		  SUNXI_FUNCTION(0x0, "gpio_in"),
499 		  SUNXI_FUNCTION(0x1, "gpio_out"),
500 		  SUNXI_FUNCTION(0x2, "aif3"),		/* BCLK */
501 		  SUNXI_FUNCTION(0x3, "i2s1"),		/* BCLK */
502 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)),	/* EINT11 */
503 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
504 		  SUNXI_FUNCTION(0x0, "gpio_in"),
505 		  SUNXI_FUNCTION(0x1, "gpio_out"),
506 		  SUNXI_FUNCTION(0x2, "aif3"),		/* DOUT */
507 		  SUNXI_FUNCTION(0x3, "i2s1"),		/* DOUT */
508 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)),	/* EINT12 */
509 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
510 		  SUNXI_FUNCTION(0x0, "gpio_in"),
511 		  SUNXI_FUNCTION(0x1, "gpio_out"),
512 		  SUNXI_FUNCTION(0x2, "aif3"),		/* DIN */
513 		  SUNXI_FUNCTION(0x3, "i2s1"),		/* DIN */
514 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)),	/* EINT13 */
515 	/* Hole */
516 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
517 		  SUNXI_FUNCTION(0x0, "gpio_in"),
518 		  SUNXI_FUNCTION(0x1, "gpio_out"),
519 		  SUNXI_FUNCTION(0x2, "i2c0"),		/* SCK */
520 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)),	/* EINT0 */
521 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
522 		  SUNXI_FUNCTION(0x0, "gpio_in"),
523 		  SUNXI_FUNCTION(0x1, "gpio_out"),
524 		  SUNXI_FUNCTION(0x2, "i2c0"),		/* SDA */
525 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),	/* EINT1 */
526 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
527 		  SUNXI_FUNCTION(0x0, "gpio_in"),
528 		  SUNXI_FUNCTION(0x1, "gpio_out"),
529 		  SUNXI_FUNCTION(0x2, "i2c1"),		/* SCK */
530 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)),	/* EINT2 */
531 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
532 		  SUNXI_FUNCTION(0x0, "gpio_in"),
533 		  SUNXI_FUNCTION(0x1, "gpio_out"),
534 		  SUNXI_FUNCTION(0x2, "i2c1"),		/* SDA */
535 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)),	/* EINT3 */
536 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
537 		  SUNXI_FUNCTION(0x0, "gpio_in"),
538 		  SUNXI_FUNCTION(0x1, "gpio_out"),
539 		  SUNXI_FUNCTION(0x2, "uart3"),		/* TX */
540 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)),	/* EINT4 */
541 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
542 		  SUNXI_FUNCTION(0x0, "gpio_in"),
543 		  SUNXI_FUNCTION(0x1, "gpio_out"),
544 		  SUNXI_FUNCTION(0x2, "uart3"),		/* RX */
545 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)),	/* EINT5 */
546 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
547 		  SUNXI_FUNCTION(0x0, "gpio_in"),
548 		  SUNXI_FUNCTION(0x1, "gpio_out"),
549 		  SUNXI_FUNCTION(0x2, "uart3"),		/* RTS */
550 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)),	/* EINT6 */
551 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
552 		  SUNXI_FUNCTION(0x0, "gpio_in"),
553 		  SUNXI_FUNCTION(0x1, "gpio_out"),
554 		  SUNXI_FUNCTION(0x2, "uart3"),		/* CTS */
555 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)),	/* EINT7 */
556 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
557 		  SUNXI_FUNCTION(0x0, "gpio_in"),
558 		  SUNXI_FUNCTION(0x1, "gpio_out"),
559 		  SUNXI_FUNCTION(0x2, "spdif"),		/* OUT */
560 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)),	/* EINT8 */
561 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
562 		  SUNXI_FUNCTION(0x0, "gpio_in"),
563 		  SUNXI_FUNCTION(0x1, "gpio_out"),
564 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)),	/* EINT9 */
565 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
566 		  SUNXI_FUNCTION(0x0, "gpio_in"),
567 		  SUNXI_FUNCTION(0x1, "gpio_out"),
568 		  SUNXI_FUNCTION(0x2, "mic"),		/* CLK */
569 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)),	/* EINT10 */
570 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
571 		  SUNXI_FUNCTION(0x0, "gpio_in"),
572 		  SUNXI_FUNCTION(0x1, "gpio_out"),
573 		  SUNXI_FUNCTION(0x2, "mic"),		/* DATA */
574 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)),	/* EINT11 */
575 };
576 
577 static const struct sunxi_pinctrl_desc a64_pinctrl_data = {
578 	.pins = a64_pins,
579 	.npins = ARRAY_SIZE(a64_pins),
580 	.irq_banks = 3,
581 };
582 
a64_pinctrl_probe(struct platform_device * pdev)583 static int a64_pinctrl_probe(struct platform_device *pdev)
584 {
585 	return sunxi_pinctrl_init(pdev,
586 				  &a64_pinctrl_data);
587 }
588 
589 static const struct of_device_id a64_pinctrl_match[] = {
590 	{ .compatible = "allwinner,sun50i-a64-pinctrl", },
591 	{}
592 };
593 
594 static struct platform_driver a64_pinctrl_driver = {
595 	.probe	= a64_pinctrl_probe,
596 	.driver	= {
597 		.name		= "sun50i-a64-pinctrl",
598 		.of_match_table	= a64_pinctrl_match,
599 	},
600 };
601 builtin_platform_driver(a64_pinctrl_driver);
602