1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * CXL Flash Device Driver 4 * 5 * Written by: Manoj N. Kumar <manoj@linux.vnet.ibm.com>, IBM Corporation 6 * Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation 7 * 8 * Copyright (C) 2015 IBM Corporation 9 */ 10 11 #ifndef _CXLFLASH_MAIN_H 12 #define _CXLFLASH_MAIN_H 13 14 #include <linux/list.h> 15 #include <linux/types.h> 16 #include <scsi/scsi.h> 17 #include <scsi/scsi_device.h> 18 19 #include "backend.h" 20 21 #define CXLFLASH_NAME "cxlflash" 22 #define CXLFLASH_ADAPTER_NAME "IBM POWER CXL Flash Adapter" 23 #define CXLFLASH_MAX_ADAPTERS 32 24 25 #define PCI_DEVICE_ID_IBM_CORSA 0x04F0 26 #define PCI_DEVICE_ID_IBM_FLASH_GT 0x0600 27 #define PCI_DEVICE_ID_IBM_BRIARD 0x0624 28 29 /* Since there is only one target, make it 0 */ 30 #define CXLFLASH_TARGET 0 31 #define CXLFLASH_MAX_CDB_LEN 16 32 33 /* Really only one target per bus since the Texan is directly attached */ 34 #define CXLFLASH_MAX_NUM_TARGETS_PER_BUS 1 35 #define CXLFLASH_MAX_NUM_LUNS_PER_TARGET 65536 36 37 #define CXLFLASH_PCI_ERROR_RECOVERY_TIMEOUT (120 * HZ) 38 39 /* FC defines */ 40 #define FC_MTIP_CMDCONFIG 0x010 41 #define FC_MTIP_STATUS 0x018 42 #define FC_MAX_NUM_LUNS 0x080 /* Max LUNs host can provision for port */ 43 #define FC_CUR_NUM_LUNS 0x088 /* Cur number LUNs provisioned for port */ 44 #define FC_MAX_CAP_PORT 0x090 /* Max capacity all LUNs for port (4K blocks) */ 45 #define FC_CUR_CAP_PORT 0x098 /* Cur capacity all LUNs for port (4K blocks) */ 46 47 #define FC_PNAME 0x300 48 #define FC_CONFIG 0x320 49 #define FC_CONFIG2 0x328 50 #define FC_STATUS 0x330 51 #define FC_ERROR 0x380 52 #define FC_ERRCAP 0x388 53 #define FC_ERRMSK 0x390 54 #define FC_CNT_CRCERR 0x538 55 #define FC_CRC_THRESH 0x580 56 57 #define FC_MTIP_CMDCONFIG_ONLINE 0x20ULL 58 #define FC_MTIP_CMDCONFIG_OFFLINE 0x40ULL 59 60 #define FC_MTIP_STATUS_MASK 0x30ULL 61 #define FC_MTIP_STATUS_ONLINE 0x20ULL 62 #define FC_MTIP_STATUS_OFFLINE 0x10ULL 63 64 /* TIMEOUT and RETRY definitions */ 65 66 /* AFU command timeout values */ 67 #define MC_AFU_SYNC_TIMEOUT 5 /* 5 secs */ 68 #define MC_LUN_PROV_TIMEOUT 5 /* 5 secs */ 69 #define MC_AFU_DEBUG_TIMEOUT 5 /* 5 secs */ 70 71 /* AFU command room retry limit */ 72 #define MC_ROOM_RETRY_CNT 10 73 74 /* FC CRC clear periodic timer */ 75 #define MC_CRC_THRESH 100 /* threshold in 5 mins */ 76 77 #define FC_PORT_STATUS_RETRY_CNT 100 /* 100 100ms retries = 10 seconds */ 78 #define FC_PORT_STATUS_RETRY_INTERVAL_US 100000 /* microseconds */ 79 80 /* VPD defines */ 81 #define CXLFLASH_VPD_LEN 256 82 #define WWPN_LEN 16 83 #define WWPN_BUF_LEN (WWPN_LEN + 1) 84 85 enum undo_level { 86 UNDO_NOOP = 0, 87 FREE_IRQ, 88 UNMAP_ONE, 89 UNMAP_TWO, 90 UNMAP_THREE 91 }; 92 93 struct dev_dependent_vals { 94 u64 max_sectors; 95 u64 flags; 96 #define CXLFLASH_NOTIFY_SHUTDOWN 0x0000000000000001ULL 97 #define CXLFLASH_WWPN_VPD_REQUIRED 0x0000000000000002ULL 98 #define CXLFLASH_OCXL_DEV 0x0000000000000004ULL 99 }; 100 101 static inline const struct cxlflash_backend_ops * cxlflash_assign_ops(struct dev_dependent_vals * ddv)102cxlflash_assign_ops(struct dev_dependent_vals *ddv) 103 { 104 const struct cxlflash_backend_ops *ops = NULL; 105 106 #ifdef CONFIG_OCXL_BASE 107 if (ddv->flags & CXLFLASH_OCXL_DEV) 108 ops = &cxlflash_ocxl_ops; 109 #endif 110 111 #ifdef CONFIG_CXL_BASE 112 if (!(ddv->flags & CXLFLASH_OCXL_DEV)) 113 ops = &cxlflash_cxl_ops; 114 #endif 115 116 return ops; 117 } 118 119 struct asyc_intr_info { 120 u64 status; 121 char *desc; 122 u8 port; 123 u8 action; 124 #define CLR_FC_ERROR 0x01 125 #define LINK_RESET 0x02 126 #define SCAN_HOST 0x04 127 }; 128 129 #endif /* _CXLFLASH_MAIN_H */ 130