1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2019 MediaTek Inc. 4 */ 5 6 #ifndef _UFS_MEDIATEK_H 7 #define _UFS_MEDIATEK_H 8 9 #include <linux/bitops.h> 10 #include <linux/soc/mediatek/mtk_sip_svc.h> 11 12 /* 13 * Vendor specific UFSHCI Registers 14 */ 15 #define REG_UFS_REFCLK_CTRL 0x144 16 #define REG_UFS_EXTREG 0x2100 17 #define REG_UFS_MPHYCTRL 0x2200 18 #define REG_UFS_MTK_IP_VER 0x2240 19 #define REG_UFS_REJECT_MON 0x22AC 20 #define REG_UFS_DEBUG_SEL 0x22C0 21 #define REG_UFS_PROBE 0x22C8 22 #define REG_UFS_DEBUG_SEL_B0 0x22D0 23 #define REG_UFS_DEBUG_SEL_B1 0x22D4 24 #define REG_UFS_DEBUG_SEL_B2 0x22D8 25 #define REG_UFS_DEBUG_SEL_B3 0x22DC 26 27 /* 28 * Ref-clk control 29 * 30 * Values for register REG_UFS_REFCLK_CTRL 31 */ 32 #define REFCLK_RELEASE 0x0 33 #define REFCLK_REQUEST BIT(0) 34 #define REFCLK_ACK BIT(1) 35 36 #define REFCLK_REQ_TIMEOUT_US 3000 37 #define REFCLK_DEFAULT_WAIT_US 32 38 39 /* 40 * Other attributes 41 */ 42 #define VS_DEBUGCLOCKENABLE 0xD0A1 43 #define VS_SAVEPOWERCONTROL 0xD0A6 44 #define VS_UNIPROPOWERDOWNCONTROL 0xD0A8 45 46 /* 47 * Vendor specific link state 48 */ 49 enum { 50 VS_LINK_DISABLED = 0, 51 VS_LINK_DOWN = 1, 52 VS_LINK_UP = 2, 53 VS_LINK_HIBERN8 = 3, 54 VS_LINK_LOST = 4, 55 VS_LINK_CFG = 5, 56 }; 57 58 /* 59 * Vendor specific host controller state 60 */ 61 enum { 62 VS_HCE_RESET = 0, 63 VS_HCE_BASE = 1, 64 VS_HCE_OOCPR_WAIT = 2, 65 VS_HCE_DME_RESET = 3, 66 VS_HCE_MIDDLE = 4, 67 VS_HCE_DME_ENABLE = 5, 68 VS_HCE_DEFAULTS = 6, 69 VS_HIB_IDLEEN = 7, 70 VS_HIB_ENTER = 8, 71 VS_HIB_ENTER_CONF = 9, 72 VS_HIB_MIDDLE = 10, 73 VS_HIB_WAITTIMER = 11, 74 VS_HIB_EXIT_CONF = 12, 75 VS_HIB_EXIT = 13, 76 }; 77 78 /* 79 * SiP commands 80 */ 81 #define MTK_SIP_UFS_CONTROL MTK_SIP_SMC_CMD(0x276) 82 #define UFS_MTK_SIP_VA09_PWR_CTRL BIT(0) 83 #define UFS_MTK_SIP_DEVICE_RESET BIT(1) 84 #define UFS_MTK_SIP_CRYPTO_CTRL BIT(2) 85 #define UFS_MTK_SIP_REF_CLK_NOTIFICATION BIT(3) 86 87 /* 88 * VS_DEBUGCLOCKENABLE 89 */ 90 enum { 91 TX_SYMBOL_CLK_REQ_FORCE = 5, 92 }; 93 94 /* 95 * VS_SAVEPOWERCONTROL 96 */ 97 enum { 98 RX_SYMBOL_CLK_GATE_EN = 0, 99 SYS_CLK_GATE_EN = 2, 100 TX_CLK_GATE_EN = 3, 101 }; 102 103 /* 104 * Host capability 105 */ 106 enum ufs_mtk_host_caps { 107 UFS_MTK_CAP_BOOST_CRYPT_ENGINE = 1 << 0, 108 UFS_MTK_CAP_VA09_PWR_CTRL = 1 << 1, 109 UFS_MTK_CAP_DISABLE_AH8 = 1 << 2, 110 UFS_MTK_CAP_BROKEN_VCC = 1 << 3, 111 }; 112 113 struct ufs_mtk_crypt_cfg { 114 struct regulator *reg_vcore; 115 struct clk *clk_crypt_perf; 116 struct clk *clk_crypt_mux; 117 struct clk *clk_crypt_lp; 118 int vcore_volt; 119 }; 120 121 struct ufs_mtk_hw_ver { 122 u8 step; 123 u8 minor; 124 u8 major; 125 }; 126 127 struct ufs_mtk_host { 128 struct phy *mphy; 129 struct regulator *reg_va09; 130 struct reset_control *hci_reset; 131 struct reset_control *unipro_reset; 132 struct reset_control *crypto_reset; 133 struct ufs_hba *hba; 134 struct ufs_mtk_crypt_cfg *crypt; 135 struct ufs_mtk_hw_ver hw_ver; 136 enum ufs_mtk_host_caps caps; 137 bool mphy_powered_on; 138 bool unipro_lpm; 139 bool ref_clk_enabled; 140 u16 ref_clk_ungating_wait_us; 141 u16 ref_clk_gating_wait_us; 142 u32 ip_ver; 143 }; 144 145 #endif /* !_UFS_MEDIATEK_H */ 146