1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
3 */
4
5 #ifndef UFS_QCOM_H_
6 #define UFS_QCOM_H_
7
8 #include <linux/reset-controller.h>
9 #include <linux/reset.h>
10
11 #define MAX_UFS_QCOM_HOSTS 1
12 #define MAX_U32 (~(u32)0)
13 #define MPHY_TX_FSM_STATE 0x41
14 #define TX_FSM_HIBERN8 0x1
15 #define HBRN8_POLL_TOUT_MS 100
16 #define DEFAULT_CLK_RATE_HZ 1000000
17 #define BUS_VECTOR_NAME_LEN 32
18
19 #define UFS_HW_VER_MAJOR_SHFT (28)
20 #define UFS_HW_VER_MAJOR_MASK (0x000F << UFS_HW_VER_MAJOR_SHFT)
21 #define UFS_HW_VER_MINOR_SHFT (16)
22 #define UFS_HW_VER_MINOR_MASK (0x0FFF << UFS_HW_VER_MINOR_SHFT)
23 #define UFS_HW_VER_STEP_SHFT (0)
24 #define UFS_HW_VER_STEP_MASK (0xFFFF << UFS_HW_VER_STEP_SHFT)
25
26 /* vendor specific pre-defined parameters */
27 #define SLOW 1
28 #define FAST 2
29
30 #define UFS_QCOM_LIMIT_HS_RATE PA_HS_MODE_B
31
32 /* QCOM UFS host controller vendor specific registers */
33 enum {
34 REG_UFS_SYS1CLK_1US = 0xC0,
35 REG_UFS_TX_SYMBOL_CLK_NS_US = 0xC4,
36 REG_UFS_LOCAL_PORT_ID_REG = 0xC8,
37 REG_UFS_PA_ERR_CODE = 0xCC,
38 REG_UFS_RETRY_TIMER_REG = 0xD0,
39 REG_UFS_PA_LINK_STARTUP_TIMER = 0xD8,
40 REG_UFS_CFG1 = 0xDC,
41 REG_UFS_CFG2 = 0xE0,
42 REG_UFS_HW_VERSION = 0xE4,
43
44 UFS_TEST_BUS = 0xE8,
45 UFS_TEST_BUS_CTRL_0 = 0xEC,
46 UFS_TEST_BUS_CTRL_1 = 0xF0,
47 UFS_TEST_BUS_CTRL_2 = 0xF4,
48 UFS_UNIPRO_CFG = 0xF8,
49
50 /*
51 * QCOM UFS host controller vendor specific registers
52 * added in HW Version 3.0.0
53 */
54 UFS_AH8_CFG = 0xFC,
55 };
56
57 /* QCOM UFS host controller vendor specific debug registers */
58 enum {
59 UFS_DBG_RD_REG_UAWM = 0x100,
60 UFS_DBG_RD_REG_UARM = 0x200,
61 UFS_DBG_RD_REG_TXUC = 0x300,
62 UFS_DBG_RD_REG_RXUC = 0x400,
63 UFS_DBG_RD_REG_DFC = 0x500,
64 UFS_DBG_RD_REG_TRLUT = 0x600,
65 UFS_DBG_RD_REG_TMRLUT = 0x700,
66 UFS_UFS_DBG_RD_REG_OCSC = 0x800,
67
68 UFS_UFS_DBG_RD_DESC_RAM = 0x1500,
69 UFS_UFS_DBG_RD_PRDT_RAM = 0x1700,
70 UFS_UFS_DBG_RD_RESP_RAM = 0x1800,
71 UFS_UFS_DBG_RD_EDTL_RAM = 0x1900,
72 };
73
74 #define UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(x) (0x000 + x)
75 #define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x) (0x400 + x)
76
77 /* bit definitions for REG_UFS_CFG1 register */
78 #define QUNIPRO_SEL 0x1
79 #define UTP_DBG_RAMS_EN 0x20000
80 #define TEST_BUS_EN BIT(18)
81 #define TEST_BUS_SEL GENMASK(22, 19)
82 #define UFS_REG_TEST_BUS_EN BIT(30)
83
84 /* bit definitions for REG_UFS_CFG2 register */
85 #define UAWM_HW_CGC_EN (1 << 0)
86 #define UARM_HW_CGC_EN (1 << 1)
87 #define TXUC_HW_CGC_EN (1 << 2)
88 #define RXUC_HW_CGC_EN (1 << 3)
89 #define DFC_HW_CGC_EN (1 << 4)
90 #define TRLUT_HW_CGC_EN (1 << 5)
91 #define TMRLUT_HW_CGC_EN (1 << 6)
92 #define OCSC_HW_CGC_EN (1 << 7)
93
94 /* bit definition for UFS_UFS_TEST_BUS_CTRL_n */
95 #define TEST_BUS_SUB_SEL_MASK 0x1F /* All XXX_SEL fields are 5 bits wide */
96
97 #define REG_UFS_CFG2_CGC_EN_ALL (UAWM_HW_CGC_EN | UARM_HW_CGC_EN |\
98 TXUC_HW_CGC_EN | RXUC_HW_CGC_EN |\
99 DFC_HW_CGC_EN | TRLUT_HW_CGC_EN |\
100 TMRLUT_HW_CGC_EN | OCSC_HW_CGC_EN)
101
102 /* bit offset */
103 enum {
104 OFFSET_UFS_PHY_SOFT_RESET = 1,
105 OFFSET_CLK_NS_REG = 10,
106 };
107
108 /* bit masks */
109 enum {
110 MASK_UFS_PHY_SOFT_RESET = 0x2,
111 MASK_TX_SYMBOL_CLK_1US_REG = 0x3FF,
112 MASK_CLK_NS_REG = 0xFFFC00,
113 };
114
115 /* QCOM UFS debug print bit mask */
116 #define UFS_QCOM_DBG_PRINT_REGS_EN BIT(0)
117 #define UFS_QCOM_DBG_PRINT_ICE_REGS_EN BIT(1)
118 #define UFS_QCOM_DBG_PRINT_TEST_BUS_EN BIT(2)
119
120 #define UFS_QCOM_DBG_PRINT_ALL \
121 (UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_ICE_REGS_EN | \
122 UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
123
124 /* QUniPro Vendor specific attributes */
125 #define PA_VS_CONFIG_REG1 0x9000
126 #define DME_VS_CORE_CLK_CTRL 0xD002
127 /* bit and mask definitions for DME_VS_CORE_CLK_CTRL attribute */
128 #define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT BIT(8)
129 #define DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK 0xFF
130
131 static inline void
ufs_qcom_get_controller_revision(struct ufs_hba * hba,u8 * major,u16 * minor,u16 * step)132 ufs_qcom_get_controller_revision(struct ufs_hba *hba,
133 u8 *major, u16 *minor, u16 *step)
134 {
135 u32 ver = ufshcd_readl(hba, REG_UFS_HW_VERSION);
136
137 *major = (ver & UFS_HW_VER_MAJOR_MASK) >> UFS_HW_VER_MAJOR_SHFT;
138 *minor = (ver & UFS_HW_VER_MINOR_MASK) >> UFS_HW_VER_MINOR_SHFT;
139 *step = (ver & UFS_HW_VER_STEP_MASK) >> UFS_HW_VER_STEP_SHFT;
140 };
141
ufs_qcom_assert_reset(struct ufs_hba * hba)142 static inline void ufs_qcom_assert_reset(struct ufs_hba *hba)
143 {
144 ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET,
145 1 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
146
147 /*
148 * Make sure assertion of ufs phy reset is written to
149 * register before returning
150 */
151 mb();
152 }
153
ufs_qcom_deassert_reset(struct ufs_hba * hba)154 static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba)
155 {
156 ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET,
157 0 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
158
159 /*
160 * Make sure de-assertion of ufs phy reset is written to
161 * register before returning
162 */
163 mb();
164 }
165
166 /* Host controller hardware version: major.minor.step */
167 struct ufs_hw_version {
168 u16 step;
169 u16 minor;
170 u8 major;
171 };
172
173 struct ufs_qcom_testbus {
174 u8 select_major;
175 u8 select_minor;
176 };
177
178 struct gpio_desc;
179
180 struct ufs_qcom_host {
181 /*
182 * Set this capability if host controller supports the QUniPro mode
183 * and if driver wants the Host controller to operate in QUniPro mode.
184 * Note: By default this capability will be kept enabled if host
185 * controller supports the QUniPro mode.
186 */
187 #define UFS_QCOM_CAP_QUNIPRO 0x1
188
189 /*
190 * Set this capability if host controller can retain the secure
191 * configuration even after UFS controller core power collapse.
192 */
193 #define UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE 0x2
194 u32 caps;
195
196 struct phy *generic_phy;
197 struct ufs_hba *hba;
198 struct ufs_pa_layer_attr dev_req_params;
199 struct clk *rx_l0_sync_clk;
200 struct clk *tx_l0_sync_clk;
201 struct clk *rx_l1_sync_clk;
202 struct clk *tx_l1_sync_clk;
203 bool is_lane_clks_enabled;
204
205 void __iomem *dev_ref_clk_ctrl_mmio;
206 bool is_dev_ref_clk_enabled;
207 struct ufs_hw_version hw_ver;
208 #ifdef CONFIG_SCSI_UFS_CRYPTO
209 void __iomem *ice_mmio;
210 #endif
211
212 u32 dev_ref_clk_en_mask;
213
214 /* Bitmask for enabling debug prints */
215 u32 dbg_print_en;
216 struct ufs_qcom_testbus testbus;
217
218 /* Reset control of HCI */
219 struct reset_control *core_reset;
220 struct reset_controller_dev rcdev;
221
222 struct gpio_desc *device_reset;
223 };
224
225 static inline u32
ufs_qcom_get_debug_reg_offset(struct ufs_qcom_host * host,u32 reg)226 ufs_qcom_get_debug_reg_offset(struct ufs_qcom_host *host, u32 reg)
227 {
228 if (host->hw_ver.major <= 0x02)
229 return UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(reg);
230
231 return UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(reg);
232 };
233
234 #define ufs_qcom_is_link_off(hba) ufshcd_is_link_off(hba)
235 #define ufs_qcom_is_link_active(hba) ufshcd_is_link_active(hba)
236 #define ufs_qcom_is_link_hibern8(hba) ufshcd_is_link_hibern8(hba)
237
238 int ufs_qcom_testbus_config(struct ufs_qcom_host *host);
239
ufs_qcom_cap_qunipro(struct ufs_qcom_host * host)240 static inline bool ufs_qcom_cap_qunipro(struct ufs_qcom_host *host)
241 {
242 if (host->caps & UFS_QCOM_CAP_QUNIPRO)
243 return true;
244 else
245 return false;
246 }
247
248 /* ufs-qcom-ice.c */
249
250 #ifdef CONFIG_SCSI_UFS_CRYPTO
251 int ufs_qcom_ice_init(struct ufs_qcom_host *host);
252 int ufs_qcom_ice_enable(struct ufs_qcom_host *host);
253 int ufs_qcom_ice_resume(struct ufs_qcom_host *host);
254 int ufs_qcom_ice_program_key(struct ufs_hba *hba,
255 const union ufs_crypto_cfg_entry *cfg, int slot);
256 #else
ufs_qcom_ice_init(struct ufs_qcom_host * host)257 static inline int ufs_qcom_ice_init(struct ufs_qcom_host *host)
258 {
259 return 0;
260 }
ufs_qcom_ice_enable(struct ufs_qcom_host * host)261 static inline int ufs_qcom_ice_enable(struct ufs_qcom_host *host)
262 {
263 return 0;
264 }
ufs_qcom_ice_resume(struct ufs_qcom_host * host)265 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host)
266 {
267 return 0;
268 }
269 #define ufs_qcom_ice_program_key NULL
270 #endif /* !CONFIG_SCSI_UFS_CRYPTO */
271
272 #endif /* UFS_QCOM_H_ */
273