1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * drivers/scsi/ufs/unipro.h 4 * 5 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 6 */ 7 8 #ifndef _UNIPRO_H_ 9 #define _UNIPRO_H_ 10 11 /* 12 * M-TX Configuration Attributes 13 */ 14 #define TX_HIBERN8TIME_CAPABILITY 0x000F 15 #define TX_MODE 0x0021 16 #define TX_HSRATE_SERIES 0x0022 17 #define TX_HSGEAR 0x0023 18 #define TX_PWMGEAR 0x0024 19 #define TX_AMPLITUDE 0x0025 20 #define TX_HS_SLEWRATE 0x0026 21 #define TX_SYNC_SOURCE 0x0027 22 #define TX_HS_SYNC_LENGTH 0x0028 23 #define TX_HS_PREPARE_LENGTH 0x0029 24 #define TX_LS_PREPARE_LENGTH 0x002A 25 #define TX_HIBERN8_CONTROL 0x002B 26 #define TX_LCC_ENABLE 0x002C 27 #define TX_PWM_BURST_CLOSURE_EXTENSION 0x002D 28 #define TX_BYPASS_8B10B_ENABLE 0x002E 29 #define TX_DRIVER_POLARITY 0x002F 30 #define TX_HS_UNTERMINATED_LINE_DRIVE_ENABLE 0x0030 31 #define TX_LS_TERMINATED_LINE_DRIVE_ENABLE 0x0031 32 #define TX_LCC_SEQUENCER 0x0032 33 #define TX_MIN_ACTIVATETIME 0x0033 34 #define TX_PWM_G6_G7_SYNC_LENGTH 0x0034 35 #define TX_REFCLKFREQ 0x00EB 36 #define TX_CFGCLKFREQVAL 0x00EC 37 #define CFGEXTRATTR 0x00F0 38 #define DITHERCTRL2 0x00F1 39 40 /* 41 * M-RX Configuration Attributes 42 */ 43 #define RX_MODE 0x00A1 44 #define RX_HSRATE_SERIES 0x00A2 45 #define RX_HSGEAR 0x00A3 46 #define RX_PWMGEAR 0x00A4 47 #define RX_LS_TERMINATED_ENABLE 0x00A5 48 #define RX_HS_UNTERMINATED_ENABLE 0x00A6 49 #define RX_ENTER_HIBERN8 0x00A7 50 #define RX_BYPASS_8B10B_ENABLE 0x00A8 51 #define RX_TERMINATION_FORCE_ENABLE 0x00A9 52 #define RX_MIN_ACTIVATETIME_CAPABILITY 0x008F 53 #define RX_HIBERN8TIME_CAPABILITY 0x0092 54 #define RX_REFCLKFREQ 0x00EB 55 #define RX_CFGCLKFREQVAL 0x00EC 56 #define CFGWIDEINLN 0x00F0 57 #define CFGRXCDR8 0x00BA 58 #define ENARXDIRECTCFG4 0x00F2 59 #define CFGRXOVR8 0x00BD 60 #define RXDIRECTCTRL2 0x00C7 61 #define ENARXDIRECTCFG3 0x00F3 62 #define RXCALCTRL 0x00B4 63 #define ENARXDIRECTCFG2 0x00F4 64 #define CFGRXOVR4 0x00E9 65 #define RXSQCTRL 0x00B5 66 #define CFGRXOVR6 0x00BF 67 #define RX_HS_G1_SYNC_LENGTH_CAP 0x008B 68 #define RX_HS_G1_PREP_LENGTH_CAP 0x008C 69 #define RX_HS_G2_SYNC_LENGTH_CAP 0x0094 70 #define RX_HS_G3_SYNC_LENGTH_CAP 0x0095 71 #define RX_HS_G2_PREP_LENGTH_CAP 0x0096 72 #define RX_HS_G3_PREP_LENGTH_CAP 0x0097 73 #define RX_ADV_GRANULARITY_CAP 0x0098 74 #define RX_MIN_ACTIVATETIME_CAP 0x008F 75 #define RX_HIBERN8TIME_CAP 0x0092 76 #define RX_ADV_HIBERN8TIME_CAP 0x0099 77 #define RX_ADV_MIN_ACTIVATETIME_CAP 0x009A 78 79 80 #define is_mphy_tx_attr(attr) (attr < RX_MODE) 81 #define RX_ADV_FINE_GRAN_STEP(x) ((((x) & 0x3) << 1) | 0x1) 82 #define SYNC_LEN_FINE(x) ((x) & 0x3F) 83 #define SYNC_LEN_COARSE(x) ((1 << 6) | ((x) & 0x3F)) 84 #define PREP_LEN(x) ((x) & 0xF) 85 86 #define RX_MIN_ACTIVATETIME_UNIT_US 100 87 #define HIBERN8TIME_UNIT_US 100 88 89 /* 90 * Common Block Attributes 91 */ 92 #define TX_GLOBALHIBERNATE UNIPRO_CB_OFFSET(0x002B) 93 #define REFCLKMODE UNIPRO_CB_OFFSET(0x00BF) 94 #define DIRECTCTRL19 UNIPRO_CB_OFFSET(0x00CD) 95 #define DIRECTCTRL10 UNIPRO_CB_OFFSET(0x00E6) 96 #define CDIRECTCTRL6 UNIPRO_CB_OFFSET(0x00EA) 97 #define RTOBSERVESELECT UNIPRO_CB_OFFSET(0x00F0) 98 #define CBDIVFACTOR UNIPRO_CB_OFFSET(0x00F1) 99 #define CBDCOCTRL5 UNIPRO_CB_OFFSET(0x00F3) 100 #define CBPRGPLL2 UNIPRO_CB_OFFSET(0x00F8) 101 #define CBPRGTUNING UNIPRO_CB_OFFSET(0x00FB) 102 103 #define UNIPRO_CB_OFFSET(x) (0x8000 | x) 104 105 /* 106 * PHY Adpater attributes 107 */ 108 #define PA_ACTIVETXDATALANES 0x1560 109 #define PA_ACTIVERXDATALANES 0x1580 110 #define PA_TXTRAILINGCLOCKS 0x1564 111 #define PA_PHY_TYPE 0x1500 112 #define PA_AVAILTXDATALANES 0x1520 113 #define PA_AVAILRXDATALANES 0x1540 114 #define PA_MINRXTRAILINGCLOCKS 0x1543 115 #define PA_TXPWRSTATUS 0x1567 116 #define PA_RXPWRSTATUS 0x1582 117 #define PA_TXFORCECLOCK 0x1562 118 #define PA_TXPWRMODE 0x1563 119 #define PA_LEGACYDPHYESCDL 0x1570 120 #define PA_MAXTXSPEEDFAST 0x1521 121 #define PA_MAXTXSPEEDSLOW 0x1522 122 #define PA_MAXRXSPEEDFAST 0x1541 123 #define PA_MAXRXSPEEDSLOW 0x1542 124 #define PA_TXLINKSTARTUPHS 0x1544 125 #define PA_LOCAL_TX_LCC_ENABLE 0x155E 126 #define PA_TXSPEEDFAST 0x1565 127 #define PA_TXSPEEDSLOW 0x1566 128 #define PA_REMOTEVERINFO 0x15A0 129 #define PA_TXGEAR 0x1568 130 #define PA_TXTERMINATION 0x1569 131 #define PA_HSSERIES 0x156A 132 #define PA_PWRMODE 0x1571 133 #define PA_RXGEAR 0x1583 134 #define PA_RXTERMINATION 0x1584 135 #define PA_MAXRXPWMGEAR 0x1586 136 #define PA_MAXRXHSGEAR 0x1587 137 #define PA_RXHSUNTERMCAP 0x15A5 138 #define PA_RXLSTERMCAP 0x15A6 139 #define PA_GRANULARITY 0x15AA 140 #define PA_PACPREQTIMEOUT 0x1590 141 #define PA_PACPREQEOBTIMEOUT 0x1591 142 #define PA_HIBERN8TIME 0x15A7 143 #define PA_LOCALVERINFO 0x15A9 144 #define PA_GRANULARITY 0x15AA 145 #define PA_TACTIVATE 0x15A8 146 #define PA_PACPFRAMECOUNT 0x15C0 147 #define PA_PACPERRORCOUNT 0x15C1 148 #define PA_PHYTESTCONTROL 0x15C2 149 #define PA_PWRMODEUSERDATA0 0x15B0 150 #define PA_PWRMODEUSERDATA1 0x15B1 151 #define PA_PWRMODEUSERDATA2 0x15B2 152 #define PA_PWRMODEUSERDATA3 0x15B3 153 #define PA_PWRMODEUSERDATA4 0x15B4 154 #define PA_PWRMODEUSERDATA5 0x15B5 155 #define PA_PWRMODEUSERDATA6 0x15B6 156 #define PA_PWRMODEUSERDATA7 0x15B7 157 #define PA_PWRMODEUSERDATA8 0x15B8 158 #define PA_PWRMODEUSERDATA9 0x15B9 159 #define PA_PWRMODEUSERDATA10 0x15BA 160 #define PA_PWRMODEUSERDATA11 0x15BB 161 #define PA_CONNECTEDTXDATALANES 0x1561 162 #define PA_CONNECTEDRXDATALANES 0x1581 163 #define PA_LOGICALLANEMAP 0x15A1 164 #define PA_SLEEPNOCONFIGTIME 0x15A2 165 #define PA_STALLNOCONFIGTIME 0x15A3 166 #define PA_SAVECONFIGTIME 0x15A4 167 #define PA_TXHSADAPTTYPE 0x15D4 168 169 /* Adpat type for PA_TXHSADAPTTYPE attribute */ 170 #define PA_REFRESH_ADAPT 0x00 171 #define PA_INITIAL_ADAPT 0x01 172 #define PA_NO_ADAPT 0x03 173 174 #define PA_TACTIVATE_TIME_UNIT_US 10 175 #define PA_HIBERN8_TIME_UNIT_US 100 176 177 /*Other attributes*/ 178 #define VS_MPHYCFGUPDT 0xD085 179 #define VS_DEBUGOMC 0xD09E 180 #define VS_POWERSTATE 0xD083 181 182 #define PA_GRANULARITY_MIN_VAL 1 183 #define PA_GRANULARITY_MAX_VAL 6 184 185 /* PHY Adapter Protocol Constants */ 186 #define PA_MAXDATALANES 4 187 188 #define DL_FC0ProtectionTimeOutVal_Default 8191 189 #define DL_TC0ReplayTimeOutVal_Default 65535 190 #define DL_AFC0ReqTimeOutVal_Default 32767 191 #define DL_FC1ProtectionTimeOutVal_Default 8191 192 #define DL_TC1ReplayTimeOutVal_Default 65535 193 #define DL_AFC1ReqTimeOutVal_Default 32767 194 195 #define DME_LocalFC0ProtectionTimeOutVal 0xD041 196 #define DME_LocalTC0ReplayTimeOutVal 0xD042 197 #define DME_LocalAFC0ReqTimeOutVal 0xD043 198 199 /* PA power modes */ 200 enum { 201 FAST_MODE = 1, 202 SLOW_MODE = 2, 203 FASTAUTO_MODE = 4, 204 SLOWAUTO_MODE = 5, 205 UNCHANGED = 7, 206 }; 207 208 #define PWRMODE_MASK 0xF 209 #define PWRMODE_RX_OFFSET 4 210 211 /* PA TX/RX Frequency Series */ 212 enum { 213 PA_HS_MODE_A = 1, 214 PA_HS_MODE_B = 2, 215 }; 216 217 enum ufs_pwm_gear_tag { 218 UFS_PWM_DONT_CHANGE, /* Don't change Gear */ 219 UFS_PWM_G1, /* PWM Gear 1 (default for reset) */ 220 UFS_PWM_G2, /* PWM Gear 2 */ 221 UFS_PWM_G3, /* PWM Gear 3 */ 222 UFS_PWM_G4, /* PWM Gear 4 */ 223 UFS_PWM_G5, /* PWM Gear 5 */ 224 UFS_PWM_G6, /* PWM Gear 6 */ 225 UFS_PWM_G7, /* PWM Gear 7 */ 226 }; 227 228 enum ufs_hs_gear_tag { 229 UFS_HS_DONT_CHANGE, /* Don't change Gear */ 230 UFS_HS_G1, /* HS Gear 1 (default for reset) */ 231 UFS_HS_G2, /* HS Gear 2 */ 232 UFS_HS_G3, /* HS Gear 3 */ 233 UFS_HS_G4, /* HS Gear 4 */ 234 }; 235 236 enum ufs_unipro_ver { 237 UFS_UNIPRO_VER_RESERVED = 0, 238 UFS_UNIPRO_VER_1_40 = 1, /* UniPro version 1.40 */ 239 UFS_UNIPRO_VER_1_41 = 2, /* UniPro version 1.41 */ 240 UFS_UNIPRO_VER_1_6 = 3, /* UniPro version 1.6 */ 241 UFS_UNIPRO_VER_1_61 = 4, /* UniPro version 1.61 */ 242 UFS_UNIPRO_VER_1_8 = 5, /* UniPro version 1.8 */ 243 UFS_UNIPRO_VER_MAX = 6, /* UniPro unsupported version */ 244 /* UniPro version field mask in PA_LOCALVERINFO */ 245 UFS_UNIPRO_VER_MASK = 0xF, 246 }; 247 248 /* 249 * Data Link Layer Attributes 250 */ 251 #define DL_TC0TXFCTHRESHOLD 0x2040 252 #define DL_FC0PROTTIMEOUTVAL 0x2041 253 #define DL_TC0REPLAYTIMEOUTVAL 0x2042 254 #define DL_AFC0REQTIMEOUTVAL 0x2043 255 #define DL_AFC0CREDITTHRESHOLD 0x2044 256 #define DL_TC0OUTACKTHRESHOLD 0x2045 257 #define DL_TC1TXFCTHRESHOLD 0x2060 258 #define DL_FC1PROTTIMEOUTVAL 0x2061 259 #define DL_TC1REPLAYTIMEOUTVAL 0x2062 260 #define DL_AFC1REQTIMEOUTVAL 0x2063 261 #define DL_AFC1CREDITTHRESHOLD 0x2064 262 #define DL_TC1OUTACKTHRESHOLD 0x2065 263 #define DL_TXPREEMPTIONCAP 0x2000 264 #define DL_TC0TXMAXSDUSIZE 0x2001 265 #define DL_TC0RXINITCREDITVAL 0x2002 266 #define DL_TC0TXBUFFERSIZE 0x2005 267 #define DL_PEERTC0PRESENT 0x2046 268 #define DL_PEERTC0RXINITCREVAL 0x2047 269 #define DL_TC1TXMAXSDUSIZE 0x2003 270 #define DL_TC1RXINITCREDITVAL 0x2004 271 #define DL_TC1TXBUFFERSIZE 0x2006 272 #define DL_PEERTC1PRESENT 0x2066 273 #define DL_PEERTC1RXINITCREVAL 0x2067 274 275 /* 276 * Network Layer Attributes 277 */ 278 #define N_DEVICEID 0x3000 279 #define N_DEVICEID_VALID 0x3001 280 #define N_TC0TXMAXSDUSIZE 0x3020 281 #define N_TC1TXMAXSDUSIZE 0x3021 282 283 /* 284 * Transport Layer Attributes 285 */ 286 #define T_NUMCPORTS 0x4000 287 #define T_NUMTESTFEATURES 0x4001 288 #define T_CONNECTIONSTATE 0x4020 289 #define T_PEERDEVICEID 0x4021 290 #define T_PEERCPORTID 0x4022 291 #define T_TRAFFICCLASS 0x4023 292 #define T_PROTOCOLID 0x4024 293 #define T_CPORTFLAGS 0x4025 294 #define T_TXTOKENVALUE 0x4026 295 #define T_RXTOKENVALUE 0x4027 296 #define T_LOCALBUFFERSPACE 0x4028 297 #define T_PEERBUFFERSPACE 0x4029 298 #define T_CREDITSTOSEND 0x402A 299 #define T_CPORTMODE 0x402B 300 #define T_TC0TXMAXSDUSIZE 0x4060 301 #define T_TC1TXMAXSDUSIZE 0x4061 302 303 #ifdef FALSE 304 #undef FALSE 305 #endif 306 307 #ifdef TRUE 308 #undef TRUE 309 #endif 310 311 /* Boolean attribute values */ 312 enum { 313 FALSE = 0, 314 TRUE, 315 }; 316 317 /* CPort setting */ 318 #define E2EFC_ON (1 << 0) 319 #define E2EFC_OFF (0 << 0) 320 #define CSD_N_ON (0 << 1) 321 #define CSD_N_OFF (1 << 1) 322 #define CSV_N_ON (0 << 2) 323 #define CSV_N_OFF (1 << 2) 324 #define CPORT_DEF_FLAGS (CSV_N_OFF | CSD_N_OFF | E2EFC_OFF) 325 326 /* CPort connection state */ 327 enum { 328 CPORT_IDLE = 0, 329 CPORT_CONNECTED, 330 }; 331 332 #endif /* _UNIPRO_H_ */ 333