1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Copyright (C) 2016-2017 Dmitry Osipenko <digetx@gmail.com> */ 3 #ifndef _UAPI_TEGRA_VDE_H_ 4 #define _UAPI_TEGRA_VDE_H_ 5 6 #include <linux/types.h> 7 #include <asm/ioctl.h> 8 9 #define FLAG_B_FRAME 0x1 10 #define FLAG_REFERENCE 0x2 11 12 struct tegra_vde_h264_frame { 13 __s32 y_fd; 14 __s32 cb_fd; 15 __s32 cr_fd; 16 __s32 aux_fd; 17 __u32 y_offset; 18 __u32 cb_offset; 19 __u32 cr_offset; 20 __u32 aux_offset; 21 __u32 frame_num; 22 __u32 flags; 23 24 // Must be zero'ed 25 __u32 reserved[6]; 26 }; 27 28 struct tegra_vde_h264_decoder_ctx { 29 __s32 bitstream_data_fd; 30 __u32 bitstream_data_offset; 31 32 __u64 dpb_frames_ptr; 33 __u32 dpb_frames_nb; 34 __u32 dpb_ref_frames_with_earlier_poc_nb; 35 36 // SPS 37 __u32 baseline_profile; 38 __u32 level_idc; 39 __u32 log2_max_pic_order_cnt_lsb; 40 __u32 log2_max_frame_num; 41 __u32 pic_order_cnt_type; 42 __u32 direct_8x8_inference_flag; 43 __u32 pic_width_in_mbs; 44 __u32 pic_height_in_mbs; 45 46 // PPS 47 __u32 pic_init_qp; 48 __u32 deblocking_filter_control_present_flag; 49 __u32 constrained_intra_pred_flag; 50 __u32 chroma_qp_index_offset; 51 __u32 pic_order_present_flag; 52 53 // Slice header 54 __u32 num_ref_idx_l0_active_minus1; 55 __u32 num_ref_idx_l1_active_minus1; 56 57 // Must be zero'ed 58 __u32 reserved[11]; 59 }; 60 61 #define VDE_IOCTL_BASE ('v' + 0x20) 62 63 #define VDE_IO(nr) _IO(VDE_IOCTL_BASE, nr) 64 #define VDE_IOR(nr, type) _IOR(VDE_IOCTL_BASE, nr, type) 65 #define VDE_IOW(nr, type) _IOW(VDE_IOCTL_BASE, nr, type) 66 #define VDE_IOWR(nr, type) _IOWR(VDE_IOCTL_BASE, nr, type) 67 68 #define TEGRA_VDE_DECODE_H264 0x00 69 70 #define TEGRA_VDE_IOCTL_DECODE_H264 \ 71 VDE_IOW(TEGRA_VDE_DECODE_H264, struct tegra_vde_h264_decoder_ctx) 72 73 #endif // _UAPI_TEGRA_VDE_H_ 74