1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2007 - 2011 Realtek Corporation. */ 3 4 #ifndef __INC_HAL8188EPHYCFG_H__ 5 #define __INC_HAL8188EPHYCFG_H__ 6 7 /*--------------------------Define Parameters-------------------------------*/ 8 #define LOOP_LIMIT 5 9 #define MAX_STALL_TIME 50 /* us */ 10 #define AntennaDiversityValue 0x80 11 #define MAX_TXPWR_IDX_NMODE_92S 63 12 #define Reset_Cnt_Limit 3 13 14 #define IQK_MAC_REG_NUM 4 15 #define IQK_ADDA_REG_NUM 16 16 #define IQK_BB_REG_NUM 9 17 #define HP_THERMAL_NUM 8 18 19 #define MAX_AGGR_NUM 0x07 20 21 /*--------------------------Define Parameters-------------------------------*/ 22 23 /*------------------------------Define structure----------------------------*/ 24 25 enum hw90_block { 26 HW90_BLOCK_MAC = 0, 27 HW90_BLOCK_PHY0 = 1, 28 HW90_BLOCK_PHY1 = 2, 29 HW90_BLOCK_RF = 3, 30 HW90_BLOCK_MAXIMUM = 4, /* Never use this */ 31 }; 32 33 enum rf_radio_path { 34 RF_PATH_A = 0, /* Radio Path A */ 35 RF_PATH_B = 1, /* Radio Path B */ 36 RF_PATH_C = 2, /* Radio Path C */ 37 RF_PATH_D = 3, /* Radio Path D */ 38 }; 39 40 #define MAX_PG_GROUP 13 41 42 #define RF_PATH_MAX 3 43 #define MAX_TX_COUNT 4 /* path numbers */ 44 45 #define CHANNEL_MAX_NUMBER 14 /* 14 is the max chnl number */ 46 #define MAX_CHNL_GROUP_24G 6 /* ch1~2, ch3~5, ch6~8, 47 *ch9~11, ch12~13, CH 14 48 * total three groups */ 49 #define CHANNEL_GROUP_MAX_88E 6 50 51 /* BB/RF related */ 52 enum RF_TYPE_8190P { 53 RF_TYPE_MIN, /* 0 */ 54 RF_8225 = 1, /* 1 11b/g RF for verification only */ 55 RF_8256 = 2, /* 2 11b/g/n */ 56 RF_6052 = 4, /* 4 11b/g/n RF */ 57 /* TODO: We should remove this psudo PHY RF after we get new RF. */ 58 RF_PSEUDO_11N = 5, /* 5, It is a temporality RF. */ 59 }; 60 61 struct bb_reg_def { 62 u32 rfintfs; /* set software control: */ 63 /* 0x870~0x877[8 bytes] */ 64 u32 rfintfi; /* readback data: */ 65 /* 0x8e0~0x8e7[8 bytes] */ 66 u32 rfintfo; /* output data: */ 67 /* 0x860~0x86f [16 bytes] */ 68 u32 rfintfe; /* output enable: */ 69 /* 0x860~0x86f [16 bytes] */ 70 u32 rf3wireOffset; /* LSSI data: */ 71 /* 0x840~0x84f [16 bytes] */ 72 u32 rfLSSI_Select; /* BB Band Select: */ 73 /* 0x878~0x87f [8 bytes] */ 74 u32 rfTxGainStage; /* Tx gain stage: */ 75 /* 0x80c~0x80f [4 bytes] */ 76 u32 rfHSSIPara1; /* wire parameter control1 : */ 77 /* 0x820~0x823,0x828~0x82b, 78 * 0x830~0x833, 0x838~0x83b [16 bytes] */ 79 u32 rfHSSIPara2; /* wire parameter control2 : */ 80 /* 0x824~0x827,0x82c~0x82f, 0x834~0x837, 81 * 0x83c~0x83f [16 bytes] */ 82 u32 rfSwitchControl; /* Tx Rx antenna control : */ 83 /* 0x858~0x85f [16 bytes] */ 84 u32 rfAGCControl1; /* AGC parameter control1 : */ 85 /* 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 86 * 0xc68~0xc6b [16 bytes] */ 87 u32 rfAGCControl2; /* AGC parameter control2 : */ 88 /* 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 89 * 0xc6c~0xc6f [16 bytes] */ 90 u32 rfRxIQImbalance; /* OFDM Rx IQ imbalance matrix : */ 91 /* 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 92 * 0xc2c~0xc2f [16 bytes] */ 93 u32 rfRxAFE; /* Rx IQ DC ofset and Rx digital filter, 94 * Rx DC notch filter : */ 95 /* 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 96 * 0xc28~0xc2b [16 bytes] */ 97 u32 rfTxIQImbalance; /* OFDM Tx IQ imbalance matrix */ 98 /* 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 99 * 0xc98~0xc9b [16 bytes] */ 100 u32 rfTxAFE; /* Tx IQ DC Offset and Tx DFIR type */ 101 /* 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 102 * 0xc9c~0xc9f [16 bytes] */ 103 u32 rfLSSIReadBack; /* LSSI RF readback data SI mode */ 104 /* 0x8a0~0x8af [16 bytes] */ 105 u32 rfLSSIReadBackPi; /* LSSI RF readback data PI mode 0x8b8-8bc for 106 * Path A and B */ 107 }; 108 109 /*------------------------------Define structure----------------------------*/ 110 111 /*------------------------Export global variable----------------------------*/ 112 /*------------------------Export global variable----------------------------*/ 113 114 /*------------------------Export Marco Definition---------------------------*/ 115 /*------------------------Export Marco Definition---------------------------*/ 116 117 /*--------------------------Exported Function prototype---------------------*/ 118 /* */ 119 /* BB and RF register read/write */ 120 /* */ 121 u32 rtl8188e_PHY_QueryBBReg(struct adapter *adapter, u32 regaddr, u32 mask); 122 void rtl8188e_PHY_SetBBReg(struct adapter *Adapter, u32 RegAddr, 123 u32 mask, u32 data); 124 u32 rtl8188e_PHY_QueryRFReg(struct adapter *adapter, enum rf_radio_path rfpath, 125 u32 regaddr, u32 mask); 126 void rtl8188e_PHY_SetRFReg(struct adapter *adapter, enum rf_radio_path rfpath, 127 u32 regaddr, u32 mask, u32 data); 128 129 /* Initialization related function */ 130 /* MAC/BB/RF HAL config */ 131 int PHY_MACConfig8188E(struct adapter *adapter); 132 int PHY_BBConfig8188E(struct adapter *adapter); 133 int PHY_RFConfig8188E(struct adapter *adapter); 134 135 /* BB TX Power R/W */ 136 void PHY_SetTxPowerLevel8188E(struct adapter *adapter, u8 channel); 137 138 /* Switch bandwidth for 8192S */ 139 void PHY_SetBWMode8188E(struct adapter *adapter, 140 enum ht_channel_width chnlwidth, unsigned char offset); 141 142 /* channel switch related funciton */ 143 void PHY_SwChnl8188E(struct adapter *adapter, u8 channel); 144 145 void storePwrIndexDiffRateOffset(struct adapter *adapter, u32 regaddr, 146 u32 mask, u32 data); 147 /*--------------------------Exported Function prototype---------------------*/ 148 149 #define PHY_QueryBBReg(adapt, regaddr, mask) \ 150 rtl8188e_PHY_QueryBBReg((adapt), (regaddr), (mask)) 151 #define PHY_SetBBReg(adapt, regaddr, bitmask, data) \ 152 rtl8188e_PHY_SetBBReg((adapt), (regaddr), (bitmask), (data)) 153 #define PHY_QueryRFReg(adapt, rfpath, regaddr, bitmask) \ 154 rtl8188e_PHY_QueryRFReg((adapt), (rfpath), (regaddr), (bitmask)) 155 #define PHY_SetRFReg(adapt, rfpath, regaddr, bitmask, data) \ 156 rtl8188e_PHY_SetRFReg((adapt), (rfpath), (regaddr), (bitmask), (data)) 157 158 #endif /* __INC_HAL8192CPHYCFG_H */ 159