1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (C) Maxime Coquelin 2015
4  * Copyright (C) STMicroelectronics SA 2017
5  * Authors:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
6  *	     Gerald Baeza <gerald_baeza@yahoo.fr>
7  */
8 
9 #define DRIVER_NAME "stm32-usart"
10 
11 struct stm32_usart_offsets {
12 	u8 cr1;
13 	u8 cr2;
14 	u8 cr3;
15 	u8 brr;
16 	u8 gtpr;
17 	u8 rtor;
18 	u8 rqr;
19 	u8 isr;
20 	u8 icr;
21 	u8 rdr;
22 	u8 tdr;
23 };
24 
25 struct stm32_usart_config {
26 	u8 uart_enable_bit; /* USART_CR1_UE */
27 	bool has_7bits_data;
28 	bool has_swap;
29 	bool has_wakeup;
30 	bool has_fifo;
31 	int fifosize;
32 };
33 
34 struct stm32_usart_info {
35 	struct stm32_usart_offsets ofs;
36 	struct stm32_usart_config cfg;
37 };
38 
39 #define UNDEF_REG 0xff
40 
41 /* Register offsets */
42 struct stm32_usart_info stm32f4_info = {
43 	.ofs = {
44 		.isr	= 0x00,
45 		.rdr	= 0x04,
46 		.tdr	= 0x04,
47 		.brr	= 0x08,
48 		.cr1	= 0x0c,
49 		.cr2	= 0x10,
50 		.cr3	= 0x14,
51 		.gtpr	= 0x18,
52 		.rtor	= UNDEF_REG,
53 		.rqr	= UNDEF_REG,
54 		.icr	= UNDEF_REG,
55 	},
56 	.cfg = {
57 		.uart_enable_bit = 13,
58 		.has_7bits_data = false,
59 		.fifosize = 1,
60 	}
61 };
62 
63 struct stm32_usart_info stm32f7_info = {
64 	.ofs = {
65 		.cr1	= 0x00,
66 		.cr2	= 0x04,
67 		.cr3	= 0x08,
68 		.brr	= 0x0c,
69 		.gtpr	= 0x10,
70 		.rtor	= 0x14,
71 		.rqr	= 0x18,
72 		.isr	= 0x1c,
73 		.icr	= 0x20,
74 		.rdr	= 0x24,
75 		.tdr	= 0x28,
76 	},
77 	.cfg = {
78 		.uart_enable_bit = 0,
79 		.has_7bits_data = true,
80 		.has_swap = true,
81 		.fifosize = 1,
82 	}
83 };
84 
85 struct stm32_usart_info stm32h7_info = {
86 	.ofs = {
87 		.cr1	= 0x00,
88 		.cr2	= 0x04,
89 		.cr3	= 0x08,
90 		.brr	= 0x0c,
91 		.gtpr	= 0x10,
92 		.rtor	= 0x14,
93 		.rqr	= 0x18,
94 		.isr	= 0x1c,
95 		.icr	= 0x20,
96 		.rdr	= 0x24,
97 		.tdr	= 0x28,
98 	},
99 	.cfg = {
100 		.uart_enable_bit = 0,
101 		.has_7bits_data = true,
102 		.has_swap = true,
103 		.has_wakeup = true,
104 		.has_fifo = true,
105 		.fifosize = 16,
106 	}
107 };
108 
109 /* USART_SR (F4) / USART_ISR (F7) */
110 #define USART_SR_PE		BIT(0)
111 #define USART_SR_FE		BIT(1)
112 #define USART_SR_NE		BIT(2)		/* F7 (NF for F4) */
113 #define USART_SR_ORE		BIT(3)
114 #define USART_SR_IDLE		BIT(4)
115 #define USART_SR_RXNE		BIT(5)
116 #define USART_SR_TC		BIT(6)
117 #define USART_SR_TXE		BIT(7)
118 #define USART_SR_CTSIF		BIT(9)
119 #define USART_SR_CTS		BIT(10)		/* F7 */
120 #define USART_SR_RTOF		BIT(11)		/* F7 */
121 #define USART_SR_EOBF		BIT(12)		/* F7 */
122 #define USART_SR_ABRE		BIT(14)		/* F7 */
123 #define USART_SR_ABRF		BIT(15)		/* F7 */
124 #define USART_SR_BUSY		BIT(16)		/* F7 */
125 #define USART_SR_CMF		BIT(17)		/* F7 */
126 #define USART_SR_SBKF		BIT(18)		/* F7 */
127 #define USART_SR_WUF		BIT(20)		/* H7 */
128 #define USART_SR_TEACK		BIT(21)		/* F7 */
129 #define USART_SR_ERR_MASK	(USART_SR_ORE | USART_SR_NE | USART_SR_FE |\
130 				 USART_SR_PE)
131 /* Dummy bits */
132 #define USART_SR_DUMMY_RX	BIT(16)
133 
134 /* USART_DR */
135 #define USART_DR_MASK		GENMASK(8, 0)
136 
137 /* USART_BRR */
138 #define USART_BRR_DIV_F_MASK	GENMASK(3, 0)
139 #define USART_BRR_DIV_M_MASK	GENMASK(15, 4)
140 #define USART_BRR_DIV_M_SHIFT	4
141 #define USART_BRR_04_R_SHIFT	1
142 
143 /* USART_CR1 */
144 #define USART_CR1_SBK		BIT(0)
145 #define USART_CR1_RWU		BIT(1)		/* F4 */
146 #define USART_CR1_UESM		BIT(1)		/* H7 */
147 #define USART_CR1_RE		BIT(2)
148 #define USART_CR1_TE		BIT(3)
149 #define USART_CR1_IDLEIE	BIT(4)
150 #define USART_CR1_RXNEIE	BIT(5)
151 #define USART_CR1_TCIE		BIT(6)
152 #define USART_CR1_TXEIE		BIT(7)
153 #define USART_CR1_PEIE		BIT(8)
154 #define USART_CR1_PS		BIT(9)
155 #define USART_CR1_PCE		BIT(10)
156 #define USART_CR1_WAKE		BIT(11)
157 #define USART_CR1_M0		BIT(12)		/* F7 (CR1_M for F4) */
158 #define USART_CR1_MME		BIT(13)		/* F7 */
159 #define USART_CR1_CMIE		BIT(14)		/* F7 */
160 #define USART_CR1_OVER8		BIT(15)
161 #define USART_CR1_DEDT_MASK	GENMASK(20, 16)	/* F7 */
162 #define USART_CR1_DEAT_MASK	GENMASK(25, 21)	/* F7 */
163 #define USART_CR1_RTOIE		BIT(26)		/* F7 */
164 #define USART_CR1_EOBIE		BIT(27)		/* F7 */
165 #define USART_CR1_M1		BIT(28)		/* F7 */
166 #define USART_CR1_IE_MASK	(GENMASK(8, 4) | BIT(14) | BIT(26) | BIT(27))
167 #define USART_CR1_FIFOEN	BIT(29)		/* H7 */
168 #define USART_CR1_DEAT_SHIFT 21
169 #define USART_CR1_DEDT_SHIFT 16
170 
171 /* USART_CR2 */
172 #define USART_CR2_ADD_MASK	GENMASK(3, 0)	/* F4 */
173 #define USART_CR2_ADDM7		BIT(4)		/* F7 */
174 #define USART_CR2_LBCL		BIT(8)
175 #define USART_CR2_CPHA		BIT(9)
176 #define USART_CR2_CPOL		BIT(10)
177 #define USART_CR2_CLKEN		BIT(11)
178 #define USART_CR2_STOP_2B	BIT(13)
179 #define USART_CR2_STOP_MASK	GENMASK(13, 12)
180 #define USART_CR2_LINEN		BIT(14)
181 #define USART_CR2_SWAP		BIT(15)		/* F7 */
182 #define USART_CR2_RXINV		BIT(16)		/* F7 */
183 #define USART_CR2_TXINV		BIT(17)		/* F7 */
184 #define USART_CR2_DATAINV	BIT(18)		/* F7 */
185 #define USART_CR2_MSBFIRST	BIT(19)		/* F7 */
186 #define USART_CR2_ABREN		BIT(20)		/* F7 */
187 #define USART_CR2_ABRMOD_MASK	GENMASK(22, 21)	/* F7 */
188 #define USART_CR2_RTOEN		BIT(23)		/* F7 */
189 #define USART_CR2_ADD_F7_MASK	GENMASK(31, 24)	/* F7 */
190 
191 /* USART_CR3 */
192 #define USART_CR3_EIE		BIT(0)
193 #define USART_CR3_IREN		BIT(1)
194 #define USART_CR3_IRLP		BIT(2)
195 #define USART_CR3_HDSEL		BIT(3)
196 #define USART_CR3_NACK		BIT(4)
197 #define USART_CR3_SCEN		BIT(5)
198 #define USART_CR3_DMAR		BIT(6)
199 #define USART_CR3_DMAT		BIT(7)
200 #define USART_CR3_RTSE		BIT(8)
201 #define USART_CR3_CTSE		BIT(9)
202 #define USART_CR3_CTSIE		BIT(10)
203 #define USART_CR3_ONEBIT	BIT(11)
204 #define USART_CR3_OVRDIS	BIT(12)		/* F7 */
205 #define USART_CR3_DDRE		BIT(13)		/* F7 */
206 #define USART_CR3_DEM		BIT(14)		/* F7 */
207 #define USART_CR3_DEP		BIT(15)		/* F7 */
208 #define USART_CR3_SCARCNT_MASK	GENMASK(19, 17)	/* F7 */
209 #define USART_CR3_WUS_MASK	GENMASK(21, 20)	/* H7 */
210 #define USART_CR3_WUS_START_BIT	BIT(21)		/* H7 */
211 #define USART_CR3_WUFIE		BIT(22)		/* H7 */
212 #define USART_CR3_TXFTIE	BIT(23)		/* H7 */
213 #define USART_CR3_TCBGTIE	BIT(24)		/* H7 */
214 #define USART_CR3_RXFTCFG_MASK	GENMASK(27, 25)	/* H7 */
215 #define USART_CR3_RXFTCFG_SHIFT	25		/* H7 */
216 #define USART_CR3_RXFTIE	BIT(28)		/* H7 */
217 #define USART_CR3_TXFTCFG_MASK	GENMASK(31, 29)	/* H7 */
218 #define USART_CR3_TXFTCFG_SHIFT	29		/* H7 */
219 
220 /* USART_GTPR */
221 #define USART_GTPR_PSC_MASK	GENMASK(7, 0)
222 #define USART_GTPR_GT_MASK	GENMASK(15, 8)
223 
224 /* USART_RTOR */
225 #define USART_RTOR_RTO_MASK	GENMASK(23, 0)	/* F7 */
226 #define USART_RTOR_BLEN_MASK	GENMASK(31, 24)	/* F7 */
227 
228 /* USART_RQR */
229 #define USART_RQR_ABRRQ		BIT(0)		/* F7 */
230 #define USART_RQR_SBKRQ		BIT(1)		/* F7 */
231 #define USART_RQR_MMRQ		BIT(2)		/* F7 */
232 #define USART_RQR_RXFRQ		BIT(3)		/* F7 */
233 #define USART_RQR_TXFRQ		BIT(4)		/* F7 */
234 
235 /* USART_ICR */
236 #define USART_ICR_PECF		BIT(0)		/* F7 */
237 #define USART_ICR_FECF		BIT(1)		/* F7 */
238 #define USART_ICR_ORECF		BIT(3)		/* F7 */
239 #define USART_ICR_IDLECF	BIT(4)		/* F7 */
240 #define USART_ICR_TCCF		BIT(6)		/* F7 */
241 #define USART_ICR_CTSCF		BIT(9)		/* F7 */
242 #define USART_ICR_RTOCF		BIT(11)		/* F7 */
243 #define USART_ICR_EOBCF		BIT(12)		/* F7 */
244 #define USART_ICR_CMCF		BIT(17)		/* F7 */
245 #define USART_ICR_WUCF		BIT(20)		/* H7 */
246 
247 #define STM32_SERIAL_NAME "ttySTM"
248 #define STM32_MAX_PORTS 8
249 
250 #define RX_BUF_L 4096		 /* dma rx buffer length     */
251 #define RX_BUF_P (RX_BUF_L / 2)	 /* dma rx buffer period     */
252 #define TX_BUF_L RX_BUF_L	 /* dma tx buffer length     */
253 
254 struct stm32_port {
255 	struct uart_port port;
256 	struct clk *clk;
257 	const struct stm32_usart_info *info;
258 	struct dma_chan *rx_ch;  /* dma rx channel            */
259 	dma_addr_t rx_dma_buf;   /* dma rx buffer bus address */
260 	unsigned char *rx_buf;   /* dma rx buffer cpu address */
261 	struct dma_chan *tx_ch;  /* dma tx channel            */
262 	dma_addr_t tx_dma_buf;   /* dma tx buffer bus address */
263 	unsigned char *tx_buf;   /* dma tx buffer cpu address */
264 	u32 cr1_irq;		 /* USART_CR1_RXNEIE or RTOIE */
265 	u32 cr3_irq;		 /* USART_CR3_RXFTIE */
266 	int last_res;
267 	bool tx_dma_busy;	 /* dma tx busy               */
268 	bool throttled;		 /* port throttled            */
269 	bool hw_flow_control;
270 	bool swap;		 /* swap RX & TX pins */
271 	bool fifoen;
272 	int rxftcfg;		/* RX FIFO threshold CFG      */
273 	int txftcfg;		/* TX FIFO threshold CFG      */
274 	bool wakeup_src;
275 	int rdr_mask;		/* receive data register mask */
276 	struct mctrl_gpios *gpios; /* modem control gpios */
277 	struct dma_tx_state rx_dma_state;
278 };
279 
280 static struct stm32_port stm32_ports[STM32_MAX_PORTS];
281 static struct uart_driver stm32_usart_driver;
282