1// SPDX-License-Identifier: GPL-2.0-or-later 2// Copyright 2019 IBM Corp. 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/interrupt-controller/aspeed-scu-ic.h> 6#include <dt-bindings/clock/ast2600-clock.h> 7 8/ { 9 model = "Aspeed BMC"; 10 compatible = "aspeed,ast2600"; 11 #address-cells = <1>; 12 #size-cells = <1>; 13 interrupt-parent = <&gic>; 14 15 aliases { 16 i2c0 = &i2c0; 17 i2c1 = &i2c1; 18 i2c2 = &i2c2; 19 i2c3 = &i2c3; 20 i2c4 = &i2c4; 21 i2c5 = &i2c5; 22 i2c6 = &i2c6; 23 i2c7 = &i2c7; 24 i2c8 = &i2c8; 25 i2c9 = &i2c9; 26 i2c10 = &i2c10; 27 i2c11 = &i2c11; 28 i2c12 = &i2c12; 29 i2c13 = &i2c13; 30 i2c14 = &i2c14; 31 i2c15 = &i2c15; 32 serial0 = &uart1; 33 serial1 = &uart2; 34 serial2 = &uart3; 35 serial3 = &uart4; 36 serial4 = &uart5; 37 serial5 = &vuart1; 38 serial6 = &vuart2; 39 }; 40 41 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 enable-method = "aspeed,ast2600-smp"; 46 47 cpu@f00 { 48 compatible = "arm,cortex-a7"; 49 device_type = "cpu"; 50 reg = <0xf00>; 51 }; 52 53 cpu@f01 { 54 compatible = "arm,cortex-a7"; 55 device_type = "cpu"; 56 reg = <0xf01>; 57 }; 58 }; 59 60 timer { 61 compatible = "arm,armv7-timer"; 62 interrupt-parent = <&gic>; 63 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 64 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 65 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 66 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 67 clocks = <&syscon ASPEED_CLK_HPLL>; 68 arm,cpu-registers-not-fw-configured; 69 always-on; 70 }; 71 72 edac: sdram@1e6e0000 { 73 compatible = "aspeed,ast2600-sdram-edac", "syscon"; 74 reg = <0x1e6e0000 0x174>; 75 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 76 }; 77 78 ahb { 79 compatible = "simple-bus"; 80 #address-cells = <1>; 81 #size-cells = <1>; 82 device_type = "soc"; 83 ranges; 84 85 gic: interrupt-controller@40461000 { 86 compatible = "arm,cortex-a7-gic"; 87 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 88 #interrupt-cells = <3>; 89 interrupt-controller; 90 interrupt-parent = <&gic>; 91 reg = <0x40461000 0x1000>, 92 <0x40462000 0x1000>, 93 <0x40464000 0x2000>, 94 <0x40466000 0x2000>; 95 }; 96 97 fmc: spi@1e620000 { 98 reg = < 0x1e620000 0xc4 99 0x20000000 0x10000000 >; 100 #address-cells = <1>; 101 #size-cells = <0>; 102 compatible = "aspeed,ast2600-fmc"; 103 clocks = <&syscon ASPEED_CLK_AHB>; 104 status = "disabled"; 105 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 106 flash@0 { 107 reg = < 0 >; 108 compatible = "jedec,spi-nor"; 109 spi-max-frequency = <50000000>; 110 status = "disabled"; 111 }; 112 flash@1 { 113 reg = < 1 >; 114 compatible = "jedec,spi-nor"; 115 spi-max-frequency = <50000000>; 116 status = "disabled"; 117 }; 118 flash@2 { 119 reg = < 2 >; 120 compatible = "jedec,spi-nor"; 121 spi-max-frequency = <50000000>; 122 status = "disabled"; 123 }; 124 }; 125 126 spi1: spi@1e630000 { 127 reg = < 0x1e630000 0xc4 128 0x30000000 0x10000000 >; 129 #address-cells = <1>; 130 #size-cells = <0>; 131 compatible = "aspeed,ast2600-spi"; 132 clocks = <&syscon ASPEED_CLK_AHB>; 133 status = "disabled"; 134 flash@0 { 135 reg = < 0 >; 136 compatible = "jedec,spi-nor"; 137 spi-max-frequency = <50000000>; 138 status = "disabled"; 139 }; 140 flash@1 { 141 reg = < 1 >; 142 compatible = "jedec,spi-nor"; 143 spi-max-frequency = <50000000>; 144 status = "disabled"; 145 }; 146 }; 147 148 spi2: spi@1e631000 { 149 reg = < 0x1e631000 0xc4 150 0x50000000 0x10000000 >; 151 #address-cells = <1>; 152 #size-cells = <0>; 153 compatible = "aspeed,ast2600-spi"; 154 clocks = <&syscon ASPEED_CLK_AHB>; 155 status = "disabled"; 156 flash@0 { 157 reg = < 0 >; 158 compatible = "jedec,spi-nor"; 159 spi-max-frequency = <50000000>; 160 status = "disabled"; 161 }; 162 flash@1 { 163 reg = < 1 >; 164 compatible = "jedec,spi-nor"; 165 spi-max-frequency = <50000000>; 166 status = "disabled"; 167 }; 168 flash@2 { 169 reg = < 2 >; 170 compatible = "jedec,spi-nor"; 171 spi-max-frequency = <50000000>; 172 status = "disabled"; 173 }; 174 }; 175 176 mdio0: mdio@1e650000 { 177 compatible = "aspeed,ast2600-mdio"; 178 reg = <0x1e650000 0x8>; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 status = "disabled"; 182 pinctrl-names = "default"; 183 pinctrl-0 = <&pinctrl_mdio1_default>; 184 }; 185 186 mdio1: mdio@1e650008 { 187 compatible = "aspeed,ast2600-mdio"; 188 reg = <0x1e650008 0x8>; 189 #address-cells = <1>; 190 #size-cells = <0>; 191 status = "disabled"; 192 pinctrl-names = "default"; 193 pinctrl-0 = <&pinctrl_mdio2_default>; 194 }; 195 196 mdio2: mdio@1e650010 { 197 compatible = "aspeed,ast2600-mdio"; 198 reg = <0x1e650010 0x8>; 199 #address-cells = <1>; 200 #size-cells = <0>; 201 status = "disabled"; 202 pinctrl-names = "default"; 203 pinctrl-0 = <&pinctrl_mdio3_default>; 204 }; 205 206 mdio3: mdio@1e650018 { 207 compatible = "aspeed,ast2600-mdio"; 208 reg = <0x1e650018 0x8>; 209 #address-cells = <1>; 210 #size-cells = <0>; 211 status = "disabled"; 212 pinctrl-names = "default"; 213 pinctrl-0 = <&pinctrl_mdio4_default>; 214 }; 215 216 mac0: ftgmac@1e660000 { 217 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 218 reg = <0x1e660000 0x180>; 219 #address-cells = <1>; 220 #size-cells = <0>; 221 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 222 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; 223 status = "disabled"; 224 }; 225 226 mac1: ftgmac@1e680000 { 227 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 228 reg = <0x1e680000 0x180>; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; 233 status = "disabled"; 234 }; 235 236 mac2: ftgmac@1e670000 { 237 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 238 reg = <0x1e670000 0x180>; 239 #address-cells = <1>; 240 #size-cells = <0>; 241 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>; 243 status = "disabled"; 244 }; 245 246 mac3: ftgmac@1e690000 { 247 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 248 reg = <0x1e690000 0x180>; 249 #address-cells = <1>; 250 #size-cells = <0>; 251 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>; 253 status = "disabled"; 254 }; 255 256 ehci0: usb@1e6a1000 { 257 compatible = "aspeed,ast2600-ehci", "generic-ehci"; 258 reg = <0x1e6a1000 0x100>; 259 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 260 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; 261 pinctrl-names = "default"; 262 pinctrl-0 = <&pinctrl_usb2ah_default>; 263 status = "disabled"; 264 }; 265 266 ehci1: usb@1e6a3000 { 267 compatible = "aspeed,ast2600-ehci", "generic-ehci"; 268 reg = <0x1e6a3000 0x100>; 269 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>; 271 pinctrl-names = "default"; 272 pinctrl-0 = <&pinctrl_usb2bh_default>; 273 status = "disabled"; 274 }; 275 276 uhci: usb@1e6b0000 { 277 compatible = "aspeed,ast2600-uhci", "generic-uhci"; 278 reg = <0x1e6b0000 0x100>; 279 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 280 #ports = <2>; 281 clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>; 282 status = "disabled"; 283 /* 284 * No default pinmux, it will follow EHCI, use an 285 * explicit pinmux override if EHCI is not enabled. 286 */ 287 }; 288 289 vhub: usb-vhub@1e6a0000 { 290 compatible = "aspeed,ast2600-usb-vhub"; 291 reg = <0x1e6a0000 0x350>; 292 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 293 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; 294 aspeed,vhub-downstream-ports = <7>; 295 aspeed,vhub-generic-endpoints = <21>; 296 pinctrl-names = "default"; 297 pinctrl-0 = <&pinctrl_usb2ad_default>; 298 status = "disabled"; 299 }; 300 301 apb { 302 compatible = "simple-bus"; 303 #address-cells = <1>; 304 #size-cells = <1>; 305 ranges; 306 307 syscon: syscon@1e6e2000 { 308 compatible = "aspeed,ast2600-scu", "syscon", "simple-mfd"; 309 reg = <0x1e6e2000 0x1000>; 310 ranges = <0 0x1e6e2000 0x1000>; 311 #address-cells = <1>; 312 #size-cells = <1>; 313 #clock-cells = <1>; 314 #reset-cells = <1>; 315 316 pinctrl: pinctrl { 317 compatible = "aspeed,ast2600-pinctrl"; 318 }; 319 320 silicon-id@14 { 321 compatible = "aspeed,ast2600-silicon-id", "aspeed,silicon-id"; 322 reg = <0x14 0x4 0x5b0 0x8>; 323 }; 324 325 smp-memram@180 { 326 compatible = "aspeed,ast2600-smpmem"; 327 reg = <0x180 0x40>; 328 }; 329 330 scu_ic0: interrupt-controller@560 { 331 #interrupt-cells = <1>; 332 compatible = "aspeed,ast2600-scu-ic0"; 333 reg = <0x560 0x4>; 334 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 335 interrupt-controller; 336 }; 337 338 scu_ic1: interrupt-controller@570 { 339 #interrupt-cells = <1>; 340 compatible = "aspeed,ast2600-scu-ic1"; 341 reg = <0x570 0x4>; 342 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 343 interrupt-controller; 344 }; 345 }; 346 347 rng: hwrng@1e6e2524 { 348 compatible = "timeriomem_rng"; 349 reg = <0x1e6e2524 0x4>; 350 period = <1>; 351 quality = <100>; 352 }; 353 354 xdma: xdma@1e6e7000 { 355 compatible = "aspeed,ast2600-xdma"; 356 reg = <0x1e6e7000 0x100>; 357 clocks = <&syscon ASPEED_CLK_GATE_BCLK>; 358 resets = <&syscon ASPEED_RESET_DEV_XDMA>, <&syscon ASPEED_RESET_RC_XDMA>; 359 reset-names = "device", "root-complex"; 360 interrupts-extended = <&gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 361 <&scu_ic0 ASPEED_AST2600_SCU_IC0_PCIE_PERST_LO_TO_HI>; 362 aspeed,pcie-device = "bmc"; 363 aspeed,scu = <&syscon>; 364 status = "disabled"; 365 }; 366 367 adc0: adc@1e6e9000 { 368 compatible = "aspeed,ast2600-adc0"; 369 reg = <0x1e6e9000 0x100>; 370 clocks = <&syscon ASPEED_CLK_APB2>; 371 resets = <&syscon ASPEED_RESET_ADC>; 372 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 373 #io-channel-cells = <1>; 374 status = "disabled"; 375 }; 376 377 adc1: adc@1e6e9100 { 378 compatible = "aspeed,ast2600-adc1"; 379 reg = <0x1e6e9100 0x100>; 380 clocks = <&syscon ASPEED_CLK_APB2>; 381 resets = <&syscon ASPEED_RESET_ADC>; 382 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 383 #io-channel-cells = <1>; 384 status = "disabled"; 385 }; 386 387 gpio0: gpio@1e780000 { 388 #gpio-cells = <2>; 389 gpio-controller; 390 compatible = "aspeed,ast2600-gpio"; 391 reg = <0x1e780000 0x400>; 392 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 393 gpio-ranges = <&pinctrl 0 0 208>; 394 ngpios = <208>; 395 clocks = <&syscon ASPEED_CLK_APB2>; 396 interrupt-controller; 397 #interrupt-cells = <2>; 398 }; 399 400 sgpiom0: sgpiom@1e780500 { 401 #gpio-cells = <2>; 402 gpio-controller; 403 compatible = "aspeed,ast2600-sgpiom"; 404 reg = <0x1e780500 0x100>; 405 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&syscon ASPEED_CLK_APB2>; 407 interrupt-controller; 408 bus-frequency = <12000000>; 409 pinctrl-names = "default"; 410 pinctrl-0 = <&pinctrl_sgpm1_default>; 411 status = "disabled"; 412 }; 413 414 sgpiom1: sgpiom@1e780600 { 415 #gpio-cells = <2>; 416 gpio-controller; 417 compatible = "aspeed,ast2600-sgpiom"; 418 reg = <0x1e780600 0x100>; 419 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&syscon ASPEED_CLK_APB2>; 421 interrupt-controller; 422 bus-frequency = <12000000>; 423 pinctrl-names = "default"; 424 pinctrl-0 = <&pinctrl_sgpm2_default>; 425 status = "disabled"; 426 }; 427 428 gpio1: gpio@1e780800 { 429 #gpio-cells = <2>; 430 gpio-controller; 431 compatible = "aspeed,ast2600-gpio"; 432 reg = <0x1e780800 0x800>; 433 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 434 gpio-ranges = <&pinctrl 0 208 36>; 435 ngpios = <36>; 436 clocks = <&syscon ASPEED_CLK_APB1>; 437 interrupt-controller; 438 #interrupt-cells = <2>; 439 }; 440 441 rtc: rtc@1e781000 { 442 compatible = "aspeed,ast2600-rtc"; 443 reg = <0x1e781000 0x18>; 444 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 445 status = "disabled"; 446 }; 447 448 timer: timer@1e782000 { 449 compatible = "aspeed,ast2600-timer"; 450 reg = <0x1e782000 0x90>; 451 interrupts-extended = <&gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 452 <&gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 453 <&gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 454 <&gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 455 <&gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 456 <&gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 457 <&gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 458 <&gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&syscon ASPEED_CLK_APB1>; 460 clock-names = "PCLK"; 461 status = "disabled"; 462 }; 463 464 uart1: serial@1e783000 { 465 compatible = "ns16550a"; 466 reg = <0x1e783000 0x20>; 467 reg-shift = <2>; 468 reg-io-width = <4>; 469 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 470 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; 471 resets = <&lpc_reset 4>; 472 no-loopback-test; 473 pinctrl-names = "default"; 474 pinctrl-0 = <&pinctrl_txd1_default &pinctrl_rxd1_default>; 475 status = "disabled"; 476 }; 477 478 uart5: serial@1e784000 { 479 compatible = "ns16550a"; 480 reg = <0x1e784000 0x1000>; 481 reg-shift = <2>; 482 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 483 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>; 484 no-loopback-test; 485 }; 486 487 wdt1: watchdog@1e785000 { 488 compatible = "aspeed,ast2600-wdt"; 489 reg = <0x1e785000 0x40>; 490 }; 491 492 wdt2: watchdog@1e785040 { 493 compatible = "aspeed,ast2600-wdt"; 494 reg = <0x1e785040 0x40>; 495 status = "disabled"; 496 }; 497 498 wdt3: watchdog@1e785080 { 499 compatible = "aspeed,ast2600-wdt"; 500 reg = <0x1e785080 0x40>; 501 status = "disabled"; 502 }; 503 504 wdt4: watchdog@1e7850c0 { 505 compatible = "aspeed,ast2600-wdt"; 506 reg = <0x1e7850C0 0x40>; 507 status = "disabled"; 508 }; 509 510 lpc: lpc@1e789000 { 511 compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"; 512 reg = <0x1e789000 0x1000>; 513 reg-io-width = <4>; 514 515 #address-cells = <1>; 516 #size-cells = <1>; 517 ranges = <0x0 0x1e789000 0x1000>; 518 519 kcs1: kcs@24 { 520 compatible = "aspeed,ast2500-kcs-bmc-v2"; 521 reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>; 522 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 523 kcs_chan = <1>; 524 status = "disabled"; 525 }; 526 527 kcs2: kcs@28 { 528 compatible = "aspeed,ast2500-kcs-bmc-v2"; 529 reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>; 530 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 531 status = "disabled"; 532 }; 533 534 kcs3: kcs@2c { 535 compatible = "aspeed,ast2500-kcs-bmc-v2"; 536 reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>; 537 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 538 status = "disabled"; 539 }; 540 541 kcs4: kcs@114 { 542 compatible = "aspeed,ast2500-kcs-bmc-v2"; 543 reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>; 544 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 545 status = "disabled"; 546 }; 547 548 lpc_ctrl: lpc-ctrl@80 { 549 compatible = "aspeed,ast2600-lpc-ctrl"; 550 reg = <0x80 0x80>; 551 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 552 status = "disabled"; 553 }; 554 555 lpc_snoop: lpc-snoop@80 { 556 compatible = "aspeed,ast2600-lpc-snoop"; 557 reg = <0x80 0x80>; 558 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 559 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 560 status = "disabled"; 561 }; 562 563 lhc: lhc@a0 { 564 compatible = "aspeed,ast2600-lhc"; 565 reg = <0xa0 0x24 0xc8 0x8>; 566 }; 567 568 lpc_reset: reset-controller@98 { 569 compatible = "aspeed,ast2600-lpc-reset"; 570 reg = <0x98 0x4>; 571 #reset-cells = <1>; 572 }; 573 574 uart_routing: uart-routing@98 { 575 compatible = "aspeed,ast2600-uart-routing"; 576 reg = <0x98 0x8>; 577 status = "disabled"; 578 }; 579 580 ibt: ibt@140 { 581 compatible = "aspeed,ast2600-ibt-bmc"; 582 reg = <0x140 0x18>; 583 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 584 status = "disabled"; 585 }; 586 }; 587 588 sdc: sdc@1e740000 { 589 compatible = "aspeed,ast2600-sd-controller"; 590 reg = <0x1e740000 0x100>; 591 #address-cells = <1>; 592 #size-cells = <1>; 593 ranges = <0 0x1e740000 0x10000>; 594 clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; 595 status = "disabled"; 596 597 sdhci0: sdhci@1e740100 { 598 compatible = "aspeed,ast2600-sdhci", "sdhci"; 599 reg = <0x100 0x100>; 600 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 601 sdhci,auto-cmd12; 602 clocks = <&syscon ASPEED_CLK_SDIO>; 603 status = "disabled"; 604 }; 605 606 sdhci1: sdhci@1e740200 { 607 compatible = "aspeed,ast2600-sdhci", "sdhci"; 608 reg = <0x200 0x100>; 609 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 610 sdhci,auto-cmd12; 611 clocks = <&syscon ASPEED_CLK_SDIO>; 612 status = "disabled"; 613 }; 614 }; 615 616 emmc_controller: sdc@1e750000 { 617 compatible = "aspeed,ast2600-sd-controller"; 618 reg = <0x1e750000 0x100>; 619 #address-cells = <1>; 620 #size-cells = <1>; 621 ranges = <0 0x1e750000 0x10000>; 622 clocks = <&syscon ASPEED_CLK_GATE_EMMCCLK>; 623 status = "disabled"; 624 625 emmc: sdhci@1e750100 { 626 compatible = "aspeed,ast2600-sdhci"; 627 reg = <0x100 0x100>; 628 sdhci,auto-cmd12; 629 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 630 clocks = <&syscon ASPEED_CLK_EMMC>; 631 pinctrl-names = "default"; 632 pinctrl-0 = <&pinctrl_emmc_default>; 633 }; 634 }; 635 636 vuart1: serial@1e787000 { 637 compatible = "aspeed,ast2500-vuart"; 638 reg = <0x1e787000 0x40>; 639 reg-shift = <2>; 640 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 641 clocks = <&syscon ASPEED_CLK_APB1>; 642 no-loopback-test; 643 status = "disabled"; 644 }; 645 646 vuart2: serial@1e788000 { 647 compatible = "aspeed,ast2500-vuart"; 648 reg = <0x1e788000 0x40>; 649 reg-shift = <2>; 650 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 651 clocks = <&syscon ASPEED_CLK_APB1>; 652 no-loopback-test; 653 status = "disabled"; 654 }; 655 656 uart2: serial@1e78d000 { 657 compatible = "ns16550a"; 658 reg = <0x1e78d000 0x20>; 659 reg-shift = <2>; 660 reg-io-width = <4>; 661 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 662 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; 663 resets = <&lpc_reset 5>; 664 no-loopback-test; 665 pinctrl-names = "default"; 666 pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; 667 status = "disabled"; 668 }; 669 670 uart3: serial@1e78e000 { 671 compatible = "ns16550a"; 672 reg = <0x1e78e000 0x20>; 673 reg-shift = <2>; 674 reg-io-width = <4>; 675 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 676 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; 677 resets = <&lpc_reset 6>; 678 no-loopback-test; 679 pinctrl-names = "default"; 680 pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>; 681 status = "disabled"; 682 }; 683 684 uart4: serial@1e78f000 { 685 compatible = "ns16550a"; 686 reg = <0x1e78f000 0x20>; 687 reg-shift = <2>; 688 reg-io-width = <4>; 689 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 690 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; 691 resets = <&lpc_reset 7>; 692 no-loopback-test; 693 pinctrl-names = "default"; 694 pinctrl-0 = <&pinctrl_txd4_default &pinctrl_rxd4_default>; 695 status = "disabled"; 696 }; 697 698 i2c: bus@1e78a000 { 699 compatible = "simple-bus"; 700 #address-cells = <1>; 701 #size-cells = <1>; 702 ranges = <0 0x1e78a000 0x1000>; 703 }; 704 705 fsim0: fsi@1e79b000 { 706 compatible = "aspeed,ast2600-fsi-master", "fsi-master"; 707 reg = <0x1e79b000 0x94>; 708 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 709 pinctrl-names = "default"; 710 pinctrl-0 = <&pinctrl_fsi1_default>; 711 clocks = <&syscon ASPEED_CLK_GATE_FSICLK>; 712 status = "disabled"; 713 }; 714 715 fsim1: fsi@1e79b100 { 716 compatible = "aspeed,ast2600-fsi-master", "fsi-master"; 717 reg = <0x1e79b100 0x94>; 718 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 719 pinctrl-names = "default"; 720 pinctrl-0 = <&pinctrl_fsi2_default>; 721 clocks = <&syscon ASPEED_CLK_GATE_FSICLK>; 722 status = "disabled"; 723 }; 724 }; 725 }; 726}; 727 728#include "aspeed-g6-pinctrl.dtsi" 729 730&i2c { 731 i2c0: i2c-bus@80 { 732 #address-cells = <1>; 733 #size-cells = <0>; 734 #interrupt-cells = <1>; 735 reg = <0x80 0x80>; 736 compatible = "aspeed,ast2600-i2c-bus"; 737 clocks = <&syscon ASPEED_CLK_APB2>; 738 resets = <&syscon ASPEED_RESET_I2C>; 739 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 740 bus-frequency = <100000>; 741 pinctrl-names = "default"; 742 pinctrl-0 = <&pinctrl_i2c1_default>; 743 status = "disabled"; 744 }; 745 746 i2c1: i2c-bus@100 { 747 #address-cells = <1>; 748 #size-cells = <0>; 749 #interrupt-cells = <1>; 750 reg = <0x100 0x80>; 751 compatible = "aspeed,ast2600-i2c-bus"; 752 clocks = <&syscon ASPEED_CLK_APB2>; 753 resets = <&syscon ASPEED_RESET_I2C>; 754 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 755 bus-frequency = <100000>; 756 pinctrl-names = "default"; 757 pinctrl-0 = <&pinctrl_i2c2_default>; 758 status = "disabled"; 759 }; 760 761 i2c2: i2c-bus@180 { 762 #address-cells = <1>; 763 #size-cells = <0>; 764 #interrupt-cells = <1>; 765 reg = <0x180 0x80>; 766 compatible = "aspeed,ast2600-i2c-bus"; 767 clocks = <&syscon ASPEED_CLK_APB2>; 768 resets = <&syscon ASPEED_RESET_I2C>; 769 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 770 bus-frequency = <100000>; 771 pinctrl-names = "default"; 772 pinctrl-0 = <&pinctrl_i2c3_default>; 773 status = "disabled"; 774 }; 775 776 i2c3: i2c-bus@200 { 777 #address-cells = <1>; 778 #size-cells = <0>; 779 #interrupt-cells = <1>; 780 reg = <0x200 0x80>; 781 compatible = "aspeed,ast2600-i2c-bus"; 782 clocks = <&syscon ASPEED_CLK_APB2>; 783 resets = <&syscon ASPEED_RESET_I2C>; 784 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 785 bus-frequency = <100000>; 786 pinctrl-names = "default"; 787 pinctrl-0 = <&pinctrl_i2c4_default>; 788 status = "disabled"; 789 }; 790 791 i2c4: i2c-bus@280 { 792 #address-cells = <1>; 793 #size-cells = <0>; 794 #interrupt-cells = <1>; 795 reg = <0x280 0x80>; 796 compatible = "aspeed,ast2600-i2c-bus"; 797 clocks = <&syscon ASPEED_CLK_APB2>; 798 resets = <&syscon ASPEED_RESET_I2C>; 799 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 800 bus-frequency = <100000>; 801 pinctrl-names = "default"; 802 pinctrl-0 = <&pinctrl_i2c5_default>; 803 status = "disabled"; 804 }; 805 806 i2c5: i2c-bus@300 { 807 #address-cells = <1>; 808 #size-cells = <0>; 809 #interrupt-cells = <1>; 810 reg = <0x300 0x80>; 811 compatible = "aspeed,ast2600-i2c-bus"; 812 clocks = <&syscon ASPEED_CLK_APB2>; 813 resets = <&syscon ASPEED_RESET_I2C>; 814 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 815 bus-frequency = <100000>; 816 pinctrl-names = "default"; 817 pinctrl-0 = <&pinctrl_i2c6_default>; 818 status = "disabled"; 819 }; 820 821 i2c6: i2c-bus@380 { 822 #address-cells = <1>; 823 #size-cells = <0>; 824 #interrupt-cells = <1>; 825 reg = <0x380 0x80>; 826 compatible = "aspeed,ast2600-i2c-bus"; 827 clocks = <&syscon ASPEED_CLK_APB2>; 828 resets = <&syscon ASPEED_RESET_I2C>; 829 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 830 bus-frequency = <100000>; 831 pinctrl-names = "default"; 832 pinctrl-0 = <&pinctrl_i2c7_default>; 833 status = "disabled"; 834 }; 835 836 i2c7: i2c-bus@400 { 837 #address-cells = <1>; 838 #size-cells = <0>; 839 #interrupt-cells = <1>; 840 reg = <0x400 0x80>; 841 compatible = "aspeed,ast2600-i2c-bus"; 842 clocks = <&syscon ASPEED_CLK_APB2>; 843 resets = <&syscon ASPEED_RESET_I2C>; 844 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 845 bus-frequency = <100000>; 846 pinctrl-names = "default"; 847 pinctrl-0 = <&pinctrl_i2c8_default>; 848 status = "disabled"; 849 }; 850 851 i2c8: i2c-bus@480 { 852 #address-cells = <1>; 853 #size-cells = <0>; 854 #interrupt-cells = <1>; 855 reg = <0x480 0x80>; 856 compatible = "aspeed,ast2600-i2c-bus"; 857 clocks = <&syscon ASPEED_CLK_APB2>; 858 resets = <&syscon ASPEED_RESET_I2C>; 859 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 860 bus-frequency = <100000>; 861 pinctrl-names = "default"; 862 pinctrl-0 = <&pinctrl_i2c9_default>; 863 status = "disabled"; 864 }; 865 866 i2c9: i2c-bus@500 { 867 #address-cells = <1>; 868 #size-cells = <0>; 869 #interrupt-cells = <1>; 870 reg = <0x500 0x80>; 871 compatible = "aspeed,ast2600-i2c-bus"; 872 clocks = <&syscon ASPEED_CLK_APB2>; 873 resets = <&syscon ASPEED_RESET_I2C>; 874 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 875 bus-frequency = <100000>; 876 pinctrl-names = "default"; 877 pinctrl-0 = <&pinctrl_i2c10_default>; 878 status = "disabled"; 879 }; 880 881 i2c10: i2c-bus@580 { 882 #address-cells = <1>; 883 #size-cells = <0>; 884 #interrupt-cells = <1>; 885 reg = <0x580 0x80>; 886 compatible = "aspeed,ast2600-i2c-bus"; 887 clocks = <&syscon ASPEED_CLK_APB2>; 888 resets = <&syscon ASPEED_RESET_I2C>; 889 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 890 bus-frequency = <100000>; 891 pinctrl-names = "default"; 892 pinctrl-0 = <&pinctrl_i2c11_default>; 893 status = "disabled"; 894 }; 895 896 i2c11: i2c-bus@600 { 897 #address-cells = <1>; 898 #size-cells = <0>; 899 #interrupt-cells = <1>; 900 reg = <0x600 0x80>; 901 compatible = "aspeed,ast2600-i2c-bus"; 902 clocks = <&syscon ASPEED_CLK_APB2>; 903 resets = <&syscon ASPEED_RESET_I2C>; 904 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 905 bus-frequency = <100000>; 906 pinctrl-names = "default"; 907 pinctrl-0 = <&pinctrl_i2c12_default>; 908 status = "disabled"; 909 }; 910 911 i2c12: i2c-bus@680 { 912 #address-cells = <1>; 913 #size-cells = <0>; 914 #interrupt-cells = <1>; 915 reg = <0x680 0x80>; 916 compatible = "aspeed,ast2600-i2c-bus"; 917 clocks = <&syscon ASPEED_CLK_APB2>; 918 resets = <&syscon ASPEED_RESET_I2C>; 919 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 920 bus-frequency = <100000>; 921 pinctrl-names = "default"; 922 pinctrl-0 = <&pinctrl_i2c13_default>; 923 status = "disabled"; 924 }; 925 926 i2c13: i2c-bus@700 { 927 #address-cells = <1>; 928 #size-cells = <0>; 929 #interrupt-cells = <1>; 930 reg = <0x700 0x80>; 931 compatible = "aspeed,ast2600-i2c-bus"; 932 clocks = <&syscon ASPEED_CLK_APB2>; 933 resets = <&syscon ASPEED_RESET_I2C>; 934 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 935 bus-frequency = <100000>; 936 pinctrl-names = "default"; 937 pinctrl-0 = <&pinctrl_i2c14_default>; 938 status = "disabled"; 939 }; 940 941 i2c14: i2c-bus@780 { 942 #address-cells = <1>; 943 #size-cells = <0>; 944 #interrupt-cells = <1>; 945 reg = <0x780 0x80>; 946 compatible = "aspeed,ast2600-i2c-bus"; 947 clocks = <&syscon ASPEED_CLK_APB2>; 948 resets = <&syscon ASPEED_RESET_I2C>; 949 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 950 bus-frequency = <100000>; 951 pinctrl-names = "default"; 952 pinctrl-0 = <&pinctrl_i2c15_default>; 953 status = "disabled"; 954 }; 955 956 i2c15: i2c-bus@800 { 957 #address-cells = <1>; 958 #size-cells = <0>; 959 #interrupt-cells = <1>; 960 reg = <0x800 0x80>; 961 compatible = "aspeed,ast2600-i2c-bus"; 962 clocks = <&syscon ASPEED_CLK_APB2>; 963 resets = <&syscon ASPEED_RESET_I2C>; 964 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 965 bus-frequency = <100000>; 966 pinctrl-names = "default"; 967 pinctrl-0 = <&pinctrl_i2c16_default>; 968 status = "disabled"; 969 }; 970}; 971