1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/qcom,gcc-msm8974.h>
10#include <dt-bindings/gpio/gpio.h>
11
12/ {
13	#address-cells = <1>;
14	#size-cells = <1>;
15	interrupt-parent = <&intc>;
16
17	chosen { };
18
19	memory@0 {
20		device_type = "memory";
21		reg = <0x0 0x0>;
22	};
23
24	clocks {
25		xo_board: xo_board {
26			compatible = "fixed-clock";
27			#clock-cells = <0>;
28			clock-frequency = <19200000>;
29		};
30
31		sleep_clk: sleep_clk {
32			compatible = "fixed-clock";
33			#clock-cells = <0>;
34			clock-frequency = <32768>;
35		};
36	};
37
38	firmware {
39		scm {
40			compatible = "qcom,scm-msm8226", "qcom,scm";
41			clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
42			clock-names = "core", "bus", "iface";
43		};
44	};
45
46	tcsr_mutex: hwlock {
47		compatible = "qcom,tcsr-mutex";
48		syscon = <&tcsr_mutex_block 0 0x80>;
49
50		#hwlock-cells = <1>;
51	};
52
53	reserved-memory {
54		#address-cells = <1>;
55		#size-cells = <1>;
56		ranges;
57
58		smem_region: smem@3000000 {
59			reg = <0x3000000 0x100000>;
60			no-map;
61		};
62	};
63
64	smd {
65		compatible = "qcom,smd";
66
67		rpm {
68			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
69			qcom,ipc = <&apcs 8 0>;
70			qcom,smd-edge = <15>;
71
72			rpm_requests: rpm-requests {
73				compatible = "qcom,rpm-msm8226";
74				qcom,smd-channels = "rpm_requests";
75			};
76		};
77	};
78
79	smem {
80		compatible = "qcom,smem";
81
82		memory-region = <&smem_region>;
83		qcom,rpm-msg-ram = <&rpm_msg_ram>;
84
85		hwlocks = <&tcsr_mutex 3>;
86	};
87
88	soc: soc {
89		compatible = "simple-bus";
90		#address-cells = <1>;
91		#size-cells = <1>;
92		ranges;
93
94		intc: interrupt-controller@f9000000 {
95			compatible = "qcom,msm-qgic2";
96			reg = <0xf9000000 0x1000>,
97			      <0xf9002000 0x1000>;
98			interrupt-controller;
99			#interrupt-cells = <3>;
100		};
101
102		apcs: syscon@f9011000 {
103			compatible = "syscon";
104			reg = <0xf9011000 0x1000>;
105		};
106
107		sdhc_1: sdhci@f9824900 {
108			compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
109			reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
110			reg-names = "hc_mem", "core_mem";
111			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
112				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
113			interrupt-names = "hc_irq", "pwr_irq";
114			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
115				 <&gcc GCC_SDCC1_AHB_CLK>,
116				 <&xo_board>;
117			clock-names = "core", "iface", "xo";
118			status = "disabled";
119		};
120
121		sdhc_2: sdhci@f98a4900 {
122			compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
123			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
124			reg-names = "hc_mem", "core_mem";
125			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
126				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
127			interrupt-names = "hc_irq", "pwr_irq";
128			clocks = <&gcc GCC_SDCC2_APPS_CLK>,
129				 <&gcc GCC_SDCC2_AHB_CLK>,
130				 <&xo_board>;
131			clock-names = "core", "iface", "xo";
132			status = "disabled";
133		};
134
135		sdhc_3: sdhci@f9864900 {
136			compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
137			reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
138			reg-names = "hc_mem", "core_mem";
139			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
140				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
141			interrupt-names = "hc_irq", "pwr_irq";
142			clocks = <&gcc GCC_SDCC3_APPS_CLK>,
143				 <&gcc GCC_SDCC3_AHB_CLK>,
144				 <&xo_board>;
145			clock-names = "core", "iface", "xo";
146			status = "disabled";
147		};
148
149		blsp1_uart3: serial@f991f000 {
150			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
151			reg = <0xf991f000 0x1000>;
152			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
153			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
154			clock-names = "core", "iface";
155			status = "disabled";
156		};
157
158		blsp1_uart4: serial@f9920000 {
159			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
160			reg = <0xf9920000 0x1000>;
161			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
162			clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
163			clock-names = "core", "iface";
164			status = "disabled";
165		};
166
167		blsp1_i2c1: i2c@f9923000 {
168			status = "disabled";
169			compatible = "qcom,i2c-qup-v2.1.1";
170			reg = <0xf9923000 0x1000>;
171			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
172			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
173			clock-names = "core", "iface";
174			pinctrl-names = "default";
175			pinctrl-0 = <&blsp1_i2c1_pins>;
176			#address-cells = <1>;
177			#size-cells = <0>;
178		};
179
180		blsp1_i2c2: i2c@f9924000 {
181			status = "disabled";
182			compatible = "qcom,i2c-qup-v2.1.1";
183			reg = <0xf9924000 0x1000>;
184			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
185			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
186			clock-names = "core", "iface";
187			pinctrl-names = "default";
188			pinctrl-0 = <&blsp1_i2c2_pins>;
189			#address-cells = <1>;
190			#size-cells = <0>;
191		};
192
193		blsp1_i2c3: i2c@f9925000 {
194			status = "disabled";
195			compatible = "qcom,i2c-qup-v2.1.1";
196			reg = <0xf9925000 0x1000>;
197			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
198			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
199			clock-names = "core", "iface";
200			pinctrl-names = "default";
201			pinctrl-0 = <&blsp1_i2c3_pins>;
202			#address-cells = <1>;
203			#size-cells = <0>;
204		};
205
206		blsp1_i2c4: i2c@f9926000 {
207			status = "disabled";
208			compatible = "qcom,i2c-qup-v2.1.1";
209			reg = <0xf9926000 0x1000>;
210			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
211			clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
212			clock-names = "core", "iface";
213			pinctrl-names = "default";
214			pinctrl-0 = <&blsp1_i2c4_pins>;
215			#address-cells = <1>;
216			#size-cells = <0>;
217		};
218
219		blsp1_i2c5: i2c@f9927000 {
220			status = "disabled";
221			compatible = "qcom,i2c-qup-v2.1.1";
222			reg = <0xf9927000 0x1000>;
223			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
224			clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
225			clock-names = "core", "iface";
226			pinctrl-names = "default";
227			pinctrl-0 = <&blsp1_i2c5_pins>;
228			#address-cells = <1>;
229			#size-cells = <0>;
230		};
231
232		gcc: clock-controller@fc400000 {
233			compatible = "qcom,gcc-msm8226";
234			reg = <0xfc400000 0x4000>;
235			#clock-cells = <1>;
236			#reset-cells = <1>;
237			#power-domain-cells = <1>;
238		};
239
240		tlmm: pinctrl@fd510000 {
241			compatible = "qcom,msm8226-pinctrl";
242			reg = <0xfd510000 0x4000>;
243			gpio-controller;
244			#gpio-cells = <2>;
245			gpio-ranges = <&tlmm 0 0 117>;
246			interrupt-controller;
247			#interrupt-cells = <2>;
248			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
249
250			blsp1_i2c1_pins: blsp1-i2c1 {
251				pins = "gpio2", "gpio3";
252				function = "blsp_i2c1";
253				drive-strength = <2>;
254				bias-disable;
255			};
256
257			blsp1_i2c2_pins: blsp1-i2c2 {
258				pins = "gpio6", "gpio7";
259				function = "blsp_i2c2";
260				drive-strength = <2>;
261				bias-disable;
262			};
263
264			blsp1_i2c3_pins: blsp1-i2c3 {
265				pins = "gpio10", "gpio11";
266				function = "blsp_i2c3";
267				drive-strength = <2>;
268				bias-disable;
269			};
270
271			blsp1_i2c4_pins: blsp1-i2c4 {
272				pins = "gpio14", "gpio15";
273				function = "blsp_i2c4";
274				drive-strength = <2>;
275				bias-disable;
276			};
277
278			blsp1_i2c5_pins: blsp1-i2c5 {
279				pins = "gpio18", "gpio19";
280				function = "blsp_i2c5";
281				drive-strength = <2>;
282				bias-disable;
283			};
284		};
285
286		restart@fc4ab000 {
287			compatible = "qcom,pshold";
288			reg = <0xfc4ab000 0x4>;
289		};
290
291		spmi_bus: spmi@fc4cf000 {
292			compatible = "qcom,spmi-pmic-arb";
293			reg-names = "core", "intr", "cnfg";
294			reg = <0xfc4cf000 0x1000>,
295			      <0xfc4cb000 0x1000>,
296			      <0xfc4ca000 0x1000>;
297			interrupt-names = "periph_irq";
298			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
299			qcom,ee = <0>;
300			qcom,channel = <0>;
301			#address-cells = <2>;
302			#size-cells = <0>;
303			interrupt-controller;
304			#interrupt-cells = <4>;
305		};
306
307		rng@f9bff000 {
308			compatible = "qcom,prng";
309			reg = <0xf9bff000 0x200>;
310			clocks = <&gcc GCC_PRNG_AHB_CLK>;
311			clock-names = "core";
312		};
313
314		timer@f9020000 {
315			compatible = "arm,armv7-timer-mem";
316			reg = <0xf9020000 0x1000>;
317			#address-cells = <1>;
318			#size-cells = <1>;
319			ranges;
320
321			frame@f9021000 {
322				frame-number = <0>;
323				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
324					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
325				reg = <0xf9021000 0x1000>,
326				      <0xf9022000 0x1000>;
327			};
328
329			frame@f9023000 {
330				frame-number = <1>;
331				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
332				reg = <0xf9023000 0x1000>;
333				status = "disabled";
334			};
335
336			frame@f9024000 {
337				frame-number = <2>;
338				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
339				reg = <0xf9024000 0x1000>;
340				status = "disabled";
341			};
342
343			frame@f9025000 {
344				frame-number = <3>;
345				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
346				reg = <0xf9025000 0x1000>;
347				status = "disabled";
348			};
349
350			frame@f9026000 {
351				frame-number = <4>;
352				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
353				reg = <0xf9026000 0x1000>;
354				status = "disabled";
355			};
356
357			frame@f9027000 {
358				frame-number = <5>;
359				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
360				reg = <0xf9027000 0x1000>;
361				status = "disabled";
362			};
363
364			frame@f9028000 {
365				frame-number = <6>;
366				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
367				reg = <0xf9028000 0x1000>;
368				status = "disabled";
369			};
370		};
371
372		rpm_msg_ram: memory@fc428000 {
373			compatible = "qcom,rpm-msg-ram";
374			reg = <0xfc428000 0x4000>;
375		};
376
377		tcsr_mutex_block: syscon@fd484000 {
378			compatible = "syscon";
379			reg = <0xfd484000 0x2000>;
380		};
381	};
382
383	timer {
384		compatible = "arm,armv7-timer";
385		interrupts = <GIC_PPI 2
386				(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
387			     <GIC_PPI 3
388				(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
389			     <GIC_PPI 4
390				(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
391			     <GIC_PPI 1
392				(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>;
393	};
394};
395