1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car V2H (R8A77920) SoC 4 * 5 * Copyright (C) 2016 Cogent Embedded Inc. 6 */ 7 8#include <dt-bindings/clock/r8a7792-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/r8a7792-sysc.h> 12 13/ { 14 compatible = "renesas,r8a7792"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 aliases { 19 i2c0 = &i2c0; 20 i2c1 = &i2c1; 21 i2c2 = &i2c2; 22 i2c3 = &i2c3; 23 i2c4 = &i2c4; 24 i2c5 = &i2c5; 25 i2c6 = &iic3; 26 spi0 = &qspi; 27 spi1 = &msiof0; 28 spi2 = &msiof1; 29 vin0 = &vin0; 30 vin1 = &vin1; 31 vin2 = &vin2; 32 vin3 = &vin3; 33 vin4 = &vin4; 34 vin5 = &vin5; 35 }; 36 37 /* External CAN clock */ 38 can_clk: can { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 /* This value must be overridden by the board. */ 42 clock-frequency = <0>; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 49 cpu0: cpu@0 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a15"; 52 reg = <0>; 53 clock-frequency = <1000000000>; 54 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; 55 power-domains = <&sysc R8A7792_PD_CA15_CPU0>; 56 enable-method = "renesas,apmu"; 57 next-level-cache = <&L2_CA15>; 58 }; 59 60 cpu1: cpu@1 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a15"; 63 reg = <1>; 64 clock-frequency = <1000000000>; 65 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; 66 power-domains = <&sysc R8A7792_PD_CA15_CPU1>; 67 enable-method = "renesas,apmu"; 68 next-level-cache = <&L2_CA15>; 69 }; 70 71 L2_CA15: cache-controller-0 { 72 compatible = "cache"; 73 cache-unified; 74 cache-level = <2>; 75 power-domains = <&sysc R8A7792_PD_CA15_SCU>; 76 }; 77 }; 78 79 /* External root clock */ 80 extal_clk: extal { 81 compatible = "fixed-clock"; 82 #clock-cells = <0>; 83 /* This value must be overridden by the board. */ 84 clock-frequency = <0>; 85 }; 86 87 pmu { 88 compatible = "arm,cortex-a15-pmu"; 89 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 90 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 91 interrupt-affinity = <&cpu0>, <&cpu1>; 92 }; 93 94 /* External SCIF clock */ 95 scif_clk: scif { 96 compatible = "fixed-clock"; 97 #clock-cells = <0>; 98 /* This value must be overridden by the board. */ 99 clock-frequency = <0>; 100 }; 101 102 soc { 103 compatible = "simple-bus"; 104 interrupt-parent = <&gic>; 105 106 #address-cells = <2>; 107 #size-cells = <2>; 108 ranges; 109 110 rwdt: watchdog@e6020000 { 111 compatible = "renesas,r8a7792-wdt", 112 "renesas,rcar-gen2-wdt"; 113 reg = <0 0xe6020000 0 0x0c>; 114 clocks = <&cpg CPG_MOD 402>; 115 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 116 resets = <&cpg 402>; 117 status = "disabled"; 118 }; 119 120 gpio0: gpio@e6050000 { 121 compatible = "renesas,gpio-r8a7792", 122 "renesas,rcar-gen2-gpio"; 123 reg = <0 0xe6050000 0 0x50>; 124 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 125 #gpio-cells = <2>; 126 gpio-controller; 127 gpio-ranges = <&pfc 0 0 29>; 128 #interrupt-cells = <2>; 129 interrupt-controller; 130 clocks = <&cpg CPG_MOD 912>; 131 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 132 resets = <&cpg 912>; 133 }; 134 135 gpio1: gpio@e6051000 { 136 compatible = "renesas,gpio-r8a7792", 137 "renesas,rcar-gen2-gpio"; 138 reg = <0 0xe6051000 0 0x50>; 139 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 140 #gpio-cells = <2>; 141 gpio-controller; 142 gpio-ranges = <&pfc 0 32 23>; 143 #interrupt-cells = <2>; 144 interrupt-controller; 145 clocks = <&cpg CPG_MOD 911>; 146 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 147 resets = <&cpg 911>; 148 }; 149 150 gpio2: gpio@e6052000 { 151 compatible = "renesas,gpio-r8a7792", 152 "renesas,rcar-gen2-gpio"; 153 reg = <0 0xe6052000 0 0x50>; 154 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 155 #gpio-cells = <2>; 156 gpio-controller; 157 gpio-ranges = <&pfc 0 64 32>; 158 #interrupt-cells = <2>; 159 interrupt-controller; 160 clocks = <&cpg CPG_MOD 910>; 161 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 162 resets = <&cpg 910>; 163 }; 164 165 gpio3: gpio@e6053000 { 166 compatible = "renesas,gpio-r8a7792", 167 "renesas,rcar-gen2-gpio"; 168 reg = <0 0xe6053000 0 0x50>; 169 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 170 #gpio-cells = <2>; 171 gpio-controller; 172 gpio-ranges = <&pfc 0 96 28>; 173 #interrupt-cells = <2>; 174 interrupt-controller; 175 clocks = <&cpg CPG_MOD 909>; 176 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 177 resets = <&cpg 909>; 178 }; 179 180 gpio4: gpio@e6054000 { 181 compatible = "renesas,gpio-r8a7792", 182 "renesas,rcar-gen2-gpio"; 183 reg = <0 0xe6054000 0 0x50>; 184 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 185 #gpio-cells = <2>; 186 gpio-controller; 187 gpio-ranges = <&pfc 0 128 17>; 188 #interrupt-cells = <2>; 189 interrupt-controller; 190 clocks = <&cpg CPG_MOD 908>; 191 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 192 resets = <&cpg 908>; 193 }; 194 195 gpio5: gpio@e6055000 { 196 compatible = "renesas,gpio-r8a7792", 197 "renesas,rcar-gen2-gpio"; 198 reg = <0 0xe6055000 0 0x50>; 199 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 200 #gpio-cells = <2>; 201 gpio-controller; 202 gpio-ranges = <&pfc 0 160 17>; 203 #interrupt-cells = <2>; 204 interrupt-controller; 205 clocks = <&cpg CPG_MOD 907>; 206 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 207 resets = <&cpg 907>; 208 }; 209 210 gpio6: gpio@e6055100 { 211 compatible = "renesas,gpio-r8a7792", 212 "renesas,rcar-gen2-gpio"; 213 reg = <0 0xe6055100 0 0x50>; 214 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 215 #gpio-cells = <2>; 216 gpio-controller; 217 gpio-ranges = <&pfc 0 192 17>; 218 #interrupt-cells = <2>; 219 interrupt-controller; 220 clocks = <&cpg CPG_MOD 905>; 221 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 222 resets = <&cpg 905>; 223 }; 224 225 gpio7: gpio@e6055200 { 226 compatible = "renesas,gpio-r8a7792", 227 "renesas,rcar-gen2-gpio"; 228 reg = <0 0xe6055200 0 0x50>; 229 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 230 #gpio-cells = <2>; 231 gpio-controller; 232 gpio-ranges = <&pfc 0 224 17>; 233 #interrupt-cells = <2>; 234 interrupt-controller; 235 clocks = <&cpg CPG_MOD 904>; 236 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 237 resets = <&cpg 904>; 238 }; 239 240 gpio8: gpio@e6055300 { 241 compatible = "renesas,gpio-r8a7792", 242 "renesas,rcar-gen2-gpio"; 243 reg = <0 0xe6055300 0 0x50>; 244 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 245 #gpio-cells = <2>; 246 gpio-controller; 247 gpio-ranges = <&pfc 0 256 17>; 248 #interrupt-cells = <2>; 249 interrupt-controller; 250 clocks = <&cpg CPG_MOD 921>; 251 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 252 resets = <&cpg 921>; 253 }; 254 255 gpio9: gpio@e6055400 { 256 compatible = "renesas,gpio-r8a7792", 257 "renesas,rcar-gen2-gpio"; 258 reg = <0 0xe6055400 0 0x50>; 259 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 260 #gpio-cells = <2>; 261 gpio-controller; 262 gpio-ranges = <&pfc 0 288 17>; 263 #interrupt-cells = <2>; 264 interrupt-controller; 265 clocks = <&cpg CPG_MOD 919>; 266 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 267 resets = <&cpg 919>; 268 }; 269 270 gpio10: gpio@e6055500 { 271 compatible = "renesas,gpio-r8a7792", 272 "renesas,rcar-gen2-gpio"; 273 reg = <0 0xe6055500 0 0x50>; 274 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 275 #gpio-cells = <2>; 276 gpio-controller; 277 gpio-ranges = <&pfc 0 320 32>; 278 #interrupt-cells = <2>; 279 interrupt-controller; 280 clocks = <&cpg CPG_MOD 914>; 281 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 282 resets = <&cpg 914>; 283 }; 284 285 gpio11: gpio@e6055600 { 286 compatible = "renesas,gpio-r8a7792", 287 "renesas,rcar-gen2-gpio"; 288 reg = <0 0xe6055600 0 0x50>; 289 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 290 #gpio-cells = <2>; 291 gpio-controller; 292 gpio-ranges = <&pfc 0 352 30>; 293 #interrupt-cells = <2>; 294 interrupt-controller; 295 clocks = <&cpg CPG_MOD 913>; 296 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 297 resets = <&cpg 913>; 298 }; 299 300 pfc: pinctrl@e6060000 { 301 compatible = "renesas,pfc-r8a7792"; 302 reg = <0 0xe6060000 0 0x144>; 303 }; 304 305 cpg: clock-controller@e6150000 { 306 compatible = "renesas,r8a7792-cpg-mssr"; 307 reg = <0 0xe6150000 0 0x1000>; 308 clocks = <&extal_clk>; 309 clock-names = "extal"; 310 #clock-cells = <2>; 311 #power-domain-cells = <0>; 312 #reset-cells = <1>; 313 }; 314 315 apmu@e6152000 { 316 compatible = "renesas,r8a7792-apmu", "renesas,apmu"; 317 reg = <0 0xe6152000 0 0x188>; 318 cpus = <&cpu0>, <&cpu1>; 319 }; 320 321 rst: reset-controller@e6160000 { 322 compatible = "renesas,r8a7792-rst"; 323 reg = <0 0xe6160000 0 0x0100>; 324 }; 325 326 sysc: system-controller@e6180000 { 327 compatible = "renesas,r8a7792-sysc"; 328 reg = <0 0xe6180000 0 0x0200>; 329 #power-domain-cells = <1>; 330 }; 331 332 irqc: interrupt-controller@e61c0000 { 333 compatible = "renesas,irqc-r8a7792", "renesas,irqc"; 334 #interrupt-cells = <2>; 335 interrupt-controller; 336 reg = <0 0xe61c0000 0 0x200>; 337 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 340 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 341 clocks = <&cpg CPG_MOD 407>; 342 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 343 resets = <&cpg 407>; 344 }; 345 346 icram0: sram@e63a0000 { 347 compatible = "mmio-sram"; 348 reg = <0 0xe63a0000 0 0x12000>; 349 #address-cells = <1>; 350 #size-cells = <1>; 351 ranges = <0 0 0xe63a0000 0x12000>; 352 }; 353 354 icram1: sram@e63c0000 { 355 compatible = "mmio-sram"; 356 reg = <0 0xe63c0000 0 0x1000>; 357 #address-cells = <1>; 358 #size-cells = <1>; 359 ranges = <0 0 0xe63c0000 0x1000>; 360 361 smp-sram@0 { 362 compatible = "renesas,smp-sram"; 363 reg = <0 0x100>; 364 }; 365 }; 366 367 /* I2C doesn't need pinmux */ 368 i2c0: i2c@e6508000 { 369 compatible = "renesas,i2c-r8a7792", 370 "renesas,rcar-gen2-i2c"; 371 reg = <0 0xe6508000 0 0x40>; 372 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&cpg CPG_MOD 931>; 374 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 375 resets = <&cpg 931>; 376 i2c-scl-internal-delay-ns = <6>; 377 #address-cells = <1>; 378 #size-cells = <0>; 379 status = "disabled"; 380 }; 381 382 i2c1: i2c@e6518000 { 383 compatible = "renesas,i2c-r8a7792", 384 "renesas,rcar-gen2-i2c"; 385 reg = <0 0xe6518000 0 0x40>; 386 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&cpg CPG_MOD 930>; 388 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 389 resets = <&cpg 930>; 390 i2c-scl-internal-delay-ns = <6>; 391 #address-cells = <1>; 392 #size-cells = <0>; 393 status = "disabled"; 394 }; 395 396 i2c2: i2c@e6530000 { 397 compatible = "renesas,i2c-r8a7792", 398 "renesas,rcar-gen2-i2c"; 399 reg = <0 0xe6530000 0 0x40>; 400 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 401 clocks = <&cpg CPG_MOD 929>; 402 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 403 resets = <&cpg 929>; 404 i2c-scl-internal-delay-ns = <6>; 405 #address-cells = <1>; 406 #size-cells = <0>; 407 status = "disabled"; 408 }; 409 410 i2c3: i2c@e6540000 { 411 compatible = "renesas,i2c-r8a7792", 412 "renesas,rcar-gen2-i2c"; 413 reg = <0 0xe6540000 0 0x40>; 414 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 415 clocks = <&cpg CPG_MOD 928>; 416 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 417 resets = <&cpg 928>; 418 i2c-scl-internal-delay-ns = <6>; 419 #address-cells = <1>; 420 #size-cells = <0>; 421 status = "disabled"; 422 }; 423 424 i2c4: i2c@e6520000 { 425 compatible = "renesas,i2c-r8a7792", 426 "renesas,rcar-gen2-i2c"; 427 reg = <0 0xe6520000 0 0x40>; 428 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 429 clocks = <&cpg CPG_MOD 927>; 430 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 431 resets = <&cpg 927>; 432 i2c-scl-internal-delay-ns = <6>; 433 #address-cells = <1>; 434 #size-cells = <0>; 435 status = "disabled"; 436 }; 437 438 i2c5: i2c@e6528000 { 439 compatible = "renesas,i2c-r8a7792", 440 "renesas,rcar-gen2-i2c"; 441 reg = <0 0xe6528000 0 0x40>; 442 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&cpg CPG_MOD 925>; 444 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 445 resets = <&cpg 925>; 446 i2c-scl-internal-delay-ns = <110>; 447 #address-cells = <1>; 448 #size-cells = <0>; 449 status = "disabled"; 450 }; 451 452 iic3: i2c@e60b0000 { 453 #address-cells = <1>; 454 #size-cells = <0>; 455 compatible = "renesas,iic-r8a7792", 456 "renesas,rcar-gen2-iic", 457 "renesas,rmobile-iic"; 458 reg = <0 0xe60b0000 0 0x425>; 459 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&cpg CPG_MOD 926>; 461 dmas = <&dmac0 0x77>, <&dmac0 0x78>, 462 <&dmac1 0x77>, <&dmac1 0x78>; 463 dma-names = "tx", "rx", "tx", "rx"; 464 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 465 resets = <&cpg 926>; 466 status = "disabled"; 467 }; 468 469 dmac0: dma-controller@e6700000 { 470 compatible = "renesas,dmac-r8a7792", 471 "renesas,rcar-dmac"; 472 reg = <0 0xe6700000 0 0x20000>; 473 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 489 interrupt-names = "error", 490 "ch0", "ch1", "ch2", "ch3", 491 "ch4", "ch5", "ch6", "ch7", 492 "ch8", "ch9", "ch10", "ch11", 493 "ch12", "ch13", "ch14"; 494 clocks = <&cpg CPG_MOD 219>; 495 clock-names = "fck"; 496 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 497 resets = <&cpg 219>; 498 #dma-cells = <1>; 499 dma-channels = <15>; 500 }; 501 502 dmac1: dma-controller@e6720000 { 503 compatible = "renesas,dmac-r8a7792", 504 "renesas,rcar-dmac"; 505 reg = <0 0xe6720000 0 0x20000>; 506 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 522 interrupt-names = "error", 523 "ch0", "ch1", "ch2", "ch3", 524 "ch4", "ch5", "ch6", "ch7", 525 "ch8", "ch9", "ch10", "ch11", 526 "ch12", "ch13", "ch14"; 527 clocks = <&cpg CPG_MOD 218>; 528 clock-names = "fck"; 529 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 530 resets = <&cpg 218>; 531 #dma-cells = <1>; 532 dma-channels = <15>; 533 }; 534 535 avb: ethernet@e6800000 { 536 compatible = "renesas,etheravb-r8a7792", 537 "renesas,etheravb-rcar-gen2"; 538 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; 539 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&cpg CPG_MOD 812>; 541 clock-names = "fck"; 542 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 543 resets = <&cpg 812>; 544 #address-cells = <1>; 545 #size-cells = <0>; 546 status = "disabled"; 547 }; 548 549 qspi: spi@e6b10000 { 550 compatible = "renesas,qspi-r8a7792", "renesas,qspi"; 551 reg = <0 0xe6b10000 0 0x2c>; 552 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 553 clocks = <&cpg CPG_MOD 917>; 554 dmas = <&dmac0 0x17>, <&dmac0 0x18>, 555 <&dmac1 0x17>, <&dmac1 0x18>; 556 dma-names = "tx", "rx", "tx", "rx"; 557 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 558 resets = <&cpg 917>; 559 num-cs = <1>; 560 #address-cells = <1>; 561 #size-cells = <0>; 562 status = "disabled"; 563 }; 564 565 scif0: serial@e6e60000 { 566 compatible = "renesas,scif-r8a7792", 567 "renesas,rcar-gen2-scif", "renesas,scif"; 568 reg = <0 0xe6e60000 0 64>; 569 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 570 clocks = <&cpg CPG_MOD 721>, 571 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 572 clock-names = "fck", "brg_int", "scif_clk"; 573 dmas = <&dmac0 0x29>, <&dmac0 0x2a>, 574 <&dmac1 0x29>, <&dmac1 0x2a>; 575 dma-names = "tx", "rx", "tx", "rx"; 576 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 577 resets = <&cpg 721>; 578 status = "disabled"; 579 }; 580 581 scif1: serial@e6e68000 { 582 compatible = "renesas,scif-r8a7792", 583 "renesas,rcar-gen2-scif", "renesas,scif"; 584 reg = <0 0xe6e68000 0 64>; 585 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 586 clocks = <&cpg CPG_MOD 720>, 587 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 588 clock-names = "fck", "brg_int", "scif_clk"; 589 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, 590 <&dmac1 0x2d>, <&dmac1 0x2e>; 591 dma-names = "tx", "rx", "tx", "rx"; 592 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 593 resets = <&cpg 720>; 594 status = "disabled"; 595 }; 596 597 scif2: serial@e6e58000 { 598 compatible = "renesas,scif-r8a7792", 599 "renesas,rcar-gen2-scif", "renesas,scif"; 600 reg = <0 0xe6e58000 0 64>; 601 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 602 clocks = <&cpg CPG_MOD 719>, 603 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 604 clock-names = "fck", "brg_int", "scif_clk"; 605 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, 606 <&dmac1 0x2b>, <&dmac1 0x2c>; 607 dma-names = "tx", "rx", "tx", "rx"; 608 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 609 resets = <&cpg 719>; 610 status = "disabled"; 611 }; 612 613 scif3: serial@e6ea8000 { 614 compatible = "renesas,scif-r8a7792", 615 "renesas,rcar-gen2-scif", "renesas,scif"; 616 reg = <0 0xe6ea8000 0 64>; 617 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 618 clocks = <&cpg CPG_MOD 718>, 619 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 620 clock-names = "fck", "brg_int", "scif_clk"; 621 dmas = <&dmac0 0x2f>, <&dmac0 0x30>, 622 <&dmac1 0x2f>, <&dmac1 0x30>; 623 dma-names = "tx", "rx", "tx", "rx"; 624 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 625 resets = <&cpg 718>; 626 status = "disabled"; 627 }; 628 629 hscif0: serial@e62c0000 { 630 compatible = "renesas,hscif-r8a7792", 631 "renesas,rcar-gen2-hscif", "renesas,hscif"; 632 reg = <0 0xe62c0000 0 96>; 633 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&cpg CPG_MOD 717>, 635 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 636 clock-names = "fck", "brg_int", "scif_clk"; 637 dmas = <&dmac0 0x39>, <&dmac0 0x3a>, 638 <&dmac1 0x39>, <&dmac1 0x3a>; 639 dma-names = "tx", "rx", "tx", "rx"; 640 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 641 resets = <&cpg 717>; 642 status = "disabled"; 643 }; 644 645 hscif1: serial@e62c8000 { 646 compatible = "renesas,hscif-r8a7792", 647 "renesas,rcar-gen2-hscif", "renesas,hscif"; 648 reg = <0 0xe62c8000 0 96>; 649 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 650 clocks = <&cpg CPG_MOD 716>, 651 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 652 clock-names = "fck", "brg_int", "scif_clk"; 653 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, 654 <&dmac1 0x4d>, <&dmac1 0x4e>; 655 dma-names = "tx", "rx", "tx", "rx"; 656 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 657 resets = <&cpg 716>; 658 status = "disabled"; 659 }; 660 661 msiof0: spi@e6e20000 { 662 compatible = "renesas,msiof-r8a7792", 663 "renesas,rcar-gen2-msiof"; 664 reg = <0 0xe6e20000 0 0x0064>; 665 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 666 clocks = <&cpg CPG_MOD 000>; 667 dmas = <&dmac0 0x51>, <&dmac0 0x52>, 668 <&dmac1 0x51>, <&dmac1 0x52>; 669 dma-names = "tx", "rx", "tx", "rx"; 670 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 671 resets = <&cpg 000>; 672 #address-cells = <1>; 673 #size-cells = <0>; 674 status = "disabled"; 675 }; 676 677 msiof1: spi@e6e10000 { 678 compatible = "renesas,msiof-r8a7792", 679 "renesas,rcar-gen2-msiof"; 680 reg = <0 0xe6e10000 0 0x0064>; 681 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 682 clocks = <&cpg CPG_MOD 208>; 683 dmas = <&dmac0 0x55>, <&dmac0 0x56>, 684 <&dmac1 0x55>, <&dmac1 0x56>; 685 dma-names = "tx", "rx", "tx", "rx"; 686 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 687 resets = <&cpg 208>; 688 #address-cells = <1>; 689 #size-cells = <0>; 690 status = "disabled"; 691 }; 692 693 can0: can@e6e80000 { 694 compatible = "renesas,can-r8a7792", 695 "renesas,rcar-gen2-can"; 696 reg = <0 0xe6e80000 0 0x1000>; 697 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 698 clocks = <&cpg CPG_MOD 916>, 699 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; 700 clock-names = "clkp1", "clkp2", "can_clk"; 701 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 702 resets = <&cpg 916>; 703 status = "disabled"; 704 }; 705 706 can1: can@e6e88000 { 707 compatible = "renesas,can-r8a7792", 708 "renesas,rcar-gen2-can"; 709 reg = <0 0xe6e88000 0 0x1000>; 710 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 711 clocks = <&cpg CPG_MOD 915>, 712 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; 713 clock-names = "clkp1", "clkp2", "can_clk"; 714 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 715 resets = <&cpg 915>; 716 status = "disabled"; 717 }; 718 719 vin0: video@e6ef0000 { 720 compatible = "renesas,vin-r8a7792", 721 "renesas,rcar-gen2-vin"; 722 reg = <0 0xe6ef0000 0 0x1000>; 723 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 724 clocks = <&cpg CPG_MOD 811>; 725 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 726 resets = <&cpg 811>; 727 status = "disabled"; 728 }; 729 730 vin1: video@e6ef1000 { 731 compatible = "renesas,vin-r8a7792", 732 "renesas,rcar-gen2-vin"; 733 reg = <0 0xe6ef1000 0 0x1000>; 734 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 735 clocks = <&cpg CPG_MOD 810>; 736 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 737 resets = <&cpg 810>; 738 status = "disabled"; 739 }; 740 741 vin2: video@e6ef2000 { 742 compatible = "renesas,vin-r8a7792", 743 "renesas,rcar-gen2-vin"; 744 reg = <0 0xe6ef2000 0 0x1000>; 745 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 746 clocks = <&cpg CPG_MOD 809>; 747 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 748 resets = <&cpg 809>; 749 status = "disabled"; 750 }; 751 752 vin3: video@e6ef3000 { 753 compatible = "renesas,vin-r8a7792", 754 "renesas,rcar-gen2-vin"; 755 reg = <0 0xe6ef3000 0 0x1000>; 756 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 757 clocks = <&cpg CPG_MOD 808>; 758 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 759 resets = <&cpg 808>; 760 status = "disabled"; 761 }; 762 763 vin4: video@e6ef4000 { 764 compatible = "renesas,vin-r8a7792", 765 "renesas,rcar-gen2-vin"; 766 reg = <0 0xe6ef4000 0 0x1000>; 767 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 768 clocks = <&cpg CPG_MOD 805>; 769 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 770 resets = <&cpg 805>; 771 status = "disabled"; 772 }; 773 774 vin5: video@e6ef5000 { 775 compatible = "renesas,vin-r8a7792", 776 "renesas,rcar-gen2-vin"; 777 reg = <0 0xe6ef5000 0 0x1000>; 778 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&cpg CPG_MOD 804>; 780 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 781 resets = <&cpg 804>; 782 status = "disabled"; 783 }; 784 785 sdhi0: mmc@ee100000 { 786 compatible = "renesas,sdhi-r8a7792", 787 "renesas,rcar-gen2-sdhi"; 788 reg = <0 0xee100000 0 0x328>; 789 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; 790 dmas = <&dmac0 0xcd>, <&dmac0 0xce>, 791 <&dmac1 0xcd>, <&dmac1 0xce>; 792 dma-names = "tx", "rx", "tx", "rx"; 793 clocks = <&cpg CPG_MOD 314>; 794 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 795 resets = <&cpg 314>; 796 status = "disabled"; 797 }; 798 799 gic: interrupt-controller@f1001000 { 800 compatible = "arm,gic-400"; 801 #interrupt-cells = <3>; 802 interrupt-controller; 803 reg = <0 0xf1001000 0 0x1000>, 804 <0 0xf1002000 0 0x2000>, 805 <0 0xf1004000 0 0x2000>, 806 <0 0xf1006000 0 0x2000>; 807 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | 808 IRQ_TYPE_LEVEL_HIGH)>; 809 clocks = <&cpg CPG_MOD 408>; 810 clock-names = "clk"; 811 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 812 resets = <&cpg 408>; 813 }; 814 815 vsp@fe928000 { 816 compatible = "renesas,vsp1"; 817 reg = <0 0xfe928000 0 0x8000>; 818 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 819 clocks = <&cpg CPG_MOD 131>; 820 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 821 resets = <&cpg 131>; 822 }; 823 824 vsp@fe930000 { 825 compatible = "renesas,vsp1"; 826 reg = <0 0xfe930000 0 0x8000>; 827 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 828 clocks = <&cpg CPG_MOD 128>; 829 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 830 resets = <&cpg 128>; 831 }; 832 833 vsp@fe938000 { 834 compatible = "renesas,vsp1"; 835 reg = <0 0xfe938000 0 0x8000>; 836 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 837 clocks = <&cpg CPG_MOD 127>; 838 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 839 resets = <&cpg 127>; 840 }; 841 842 jpu: jpeg-codec@fe980000 { 843 compatible = "renesas,jpu-r8a7792", 844 "renesas,rcar-gen2-jpu"; 845 reg = <0 0xfe980000 0 0x10300>; 846 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 847 clocks = <&cpg CPG_MOD 106>; 848 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 849 resets = <&cpg 106>; 850 }; 851 852 du: display@feb00000 { 853 compatible = "renesas,du-r8a7792"; 854 reg = <0 0xfeb00000 0 0x40000>; 855 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 857 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; 858 clock-names = "du.0", "du.1"; 859 resets = <&cpg 724>; 860 reset-names = "du.0"; 861 status = "disabled"; 862 863 ports { 864 #address-cells = <1>; 865 #size-cells = <0>; 866 867 port@0 { 868 reg = <0>; 869 du_out_rgb0: endpoint { 870 }; 871 }; 872 port@1 { 873 reg = <1>; 874 du_out_rgb1: endpoint { 875 }; 876 }; 877 }; 878 }; 879 880 prr: chipid@ff000044 { 881 compatible = "renesas,prr"; 882 reg = <0 0xff000044 0 4>; 883 }; 884 885 cmt0: timer@ffca0000 { 886 compatible = "renesas,r8a7792-cmt0", 887 "renesas,rcar-gen2-cmt0"; 888 reg = <0 0xffca0000 0 0x1004>; 889 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 891 clocks = <&cpg CPG_MOD 124>; 892 clock-names = "fck"; 893 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 894 resets = <&cpg 124>; 895 896 status = "disabled"; 897 }; 898 899 cmt1: timer@e6130000 { 900 compatible = "renesas,r8a7792-cmt1", 901 "renesas,rcar-gen2-cmt1"; 902 reg = <0 0xe6130000 0 0x1004>; 903 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 911 clocks = <&cpg CPG_MOD 329>; 912 clock-names = "fck"; 913 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 914 resets = <&cpg 329>; 915 916 status = "disabled"; 917 }; 918 }; 919 920 timer { 921 compatible = "arm,armv7-timer"; 922 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 923 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 924 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 925 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 926 }; 927}; 928