1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2013 MundoReader S.L. 4 * Author: Heiko Stuebner <heiko@sntech.de> 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/pinctrl/rockchip.h> 9#include <dt-bindings/clock/rk3066a-cru.h> 10#include <dt-bindings/power/rk3066-power.h> 11#include "rk3xxx.dtsi" 12 13/ { 14 compatible = "rockchip,rk3066a"; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 enable-method = "rockchip,rk3066-smp"; 20 21 cpu0: cpu@0 { 22 device_type = "cpu"; 23 compatible = "arm,cortex-a9"; 24 next-level-cache = <&L2>; 25 reg = <0x0>; 26 operating-points = 27 /* kHz uV */ 28 <1416000 1300000>, 29 <1200000 1175000>, 30 <1008000 1125000>, 31 <816000 1125000>, 32 <600000 1100000>, 33 <504000 1100000>, 34 <312000 1075000>; 35 clock-latency = <40000>; 36 clocks = <&cru ARMCLK>; 37 }; 38 cpu1: cpu@1 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a9"; 41 next-level-cache = <&L2>; 42 reg = <0x1>; 43 }; 44 }; 45 46 display-subsystem { 47 compatible = "rockchip,display-subsystem"; 48 ports = <&vop0_out>, <&vop1_out>; 49 }; 50 51 sram: sram@10080000 { 52 compatible = "mmio-sram"; 53 reg = <0x10080000 0x10000>; 54 #address-cells = <1>; 55 #size-cells = <1>; 56 ranges = <0 0x10080000 0x10000>; 57 58 smp-sram@0 { 59 compatible = "rockchip,rk3066-smp-sram"; 60 reg = <0x0 0x50>; 61 }; 62 }; 63 64 vop0: vop@1010c000 { 65 compatible = "rockchip,rk3066-vop"; 66 reg = <0x1010c000 0x19c>; 67 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 68 clocks = <&cru ACLK_LCDC0>, 69 <&cru DCLK_LCDC0>, 70 <&cru HCLK_LCDC0>; 71 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 72 power-domains = <&power RK3066_PD_VIO>; 73 resets = <&cru SRST_LCDC0_AXI>, 74 <&cru SRST_LCDC0_AHB>, 75 <&cru SRST_LCDC0_DCLK>; 76 reset-names = "axi", "ahb", "dclk"; 77 status = "disabled"; 78 79 vop0_out: port { 80 #address-cells = <1>; 81 #size-cells = <0>; 82 83 vop0_out_hdmi: endpoint@0 { 84 reg = <0>; 85 remote-endpoint = <&hdmi_in_vop0>; 86 }; 87 }; 88 }; 89 90 vop1: vop@1010e000 { 91 compatible = "rockchip,rk3066-vop"; 92 reg = <0x1010e000 0x19c>; 93 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 94 clocks = <&cru ACLK_LCDC1>, 95 <&cru DCLK_LCDC1>, 96 <&cru HCLK_LCDC1>; 97 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 98 power-domains = <&power RK3066_PD_VIO>; 99 resets = <&cru SRST_LCDC1_AXI>, 100 <&cru SRST_LCDC1_AHB>, 101 <&cru SRST_LCDC1_DCLK>; 102 reset-names = "axi", "ahb", "dclk"; 103 status = "disabled"; 104 105 vop1_out: port { 106 #address-cells = <1>; 107 #size-cells = <0>; 108 109 vop1_out_hdmi: endpoint@0 { 110 reg = <0>; 111 remote-endpoint = <&hdmi_in_vop1>; 112 }; 113 }; 114 }; 115 116 hdmi: hdmi@10116000 { 117 compatible = "rockchip,rk3066-hdmi"; 118 reg = <0x10116000 0x2000>; 119 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 120 clocks = <&cru HCLK_HDMI>; 121 clock-names = "hclk"; 122 pinctrl-names = "default"; 123 pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>; 124 power-domains = <&power RK3066_PD_VIO>; 125 rockchip,grf = <&grf>; 126 status = "disabled"; 127 128 ports { 129 #address-cells = <1>; 130 #size-cells = <0>; 131 132 hdmi_in: port@0 { 133 reg = <0>; 134 #address-cells = <1>; 135 #size-cells = <0>; 136 137 hdmi_in_vop0: endpoint@0 { 138 reg = <0>; 139 remote-endpoint = <&vop0_out_hdmi>; 140 }; 141 142 hdmi_in_vop1: endpoint@1 { 143 reg = <1>; 144 remote-endpoint = <&vop1_out_hdmi>; 145 }; 146 }; 147 148 hdmi_out: port@1 { 149 reg = <1>; 150 }; 151 }; 152 }; 153 154 i2s0: i2s@10118000 { 155 compatible = "rockchip,rk3066-i2s"; 156 reg = <0x10118000 0x2000>; 157 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 158 pinctrl-names = "default"; 159 pinctrl-0 = <&i2s0_bus>; 160 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; 161 clock-names = "i2s_clk", "i2s_hclk"; 162 dmas = <&dmac1_s 4>, <&dmac1_s 5>; 163 dma-names = "tx", "rx"; 164 rockchip,playback-channels = <8>; 165 rockchip,capture-channels = <2>; 166 #sound-dai-cells = <0>; 167 status = "disabled"; 168 }; 169 170 i2s1: i2s@1011a000 { 171 compatible = "rockchip,rk3066-i2s"; 172 reg = <0x1011a000 0x2000>; 173 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 174 pinctrl-names = "default"; 175 pinctrl-0 = <&i2s1_bus>; 176 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; 177 clock-names = "i2s_clk", "i2s_hclk"; 178 dmas = <&dmac1_s 6>, <&dmac1_s 7>; 179 dma-names = "tx", "rx"; 180 rockchip,playback-channels = <2>; 181 rockchip,capture-channels = <2>; 182 #sound-dai-cells = <0>; 183 status = "disabled"; 184 }; 185 186 i2s2: i2s@1011c000 { 187 compatible = "rockchip,rk3066-i2s"; 188 reg = <0x1011c000 0x2000>; 189 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 190 pinctrl-names = "default"; 191 pinctrl-0 = <&i2s2_bus>; 192 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; 193 clock-names = "i2s_clk", "i2s_hclk"; 194 dmas = <&dmac1_s 9>, <&dmac1_s 10>; 195 dma-names = "tx", "rx"; 196 rockchip,playback-channels = <2>; 197 rockchip,capture-channels = <2>; 198 #sound-dai-cells = <0>; 199 status = "disabled"; 200 }; 201 202 cru: clock-controller@20000000 { 203 compatible = "rockchip,rk3066a-cru"; 204 reg = <0x20000000 0x1000>; 205 rockchip,grf = <&grf>; 206 207 #clock-cells = <1>; 208 #reset-cells = <1>; 209 assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>, 210 <&cru ACLK_CPU>, <&cru HCLK_CPU>, 211 <&cru PCLK_CPU>, <&cru ACLK_PERI>, 212 <&cru HCLK_PERI>, <&cru PCLK_PERI>; 213 assigned-clock-rates = <400000000>, <594000000>, 214 <300000000>, <150000000>, 215 <75000000>, <300000000>, 216 <150000000>, <75000000>; 217 }; 218 219 timer2: timer@2000e000 { 220 compatible = "snps,dw-apb-timer"; 221 reg = <0x2000e000 0x100>; 222 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 223 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>; 224 clock-names = "timer", "pclk"; 225 }; 226 227 efuse: efuse@20010000 { 228 compatible = "rockchip,rk3066a-efuse"; 229 reg = <0x20010000 0x4000>; 230 #address-cells = <1>; 231 #size-cells = <1>; 232 clocks = <&cru PCLK_EFUSE>; 233 clock-names = "pclk_efuse"; 234 235 cpu_leakage: cpu_leakage@17 { 236 reg = <0x17 0x1>; 237 }; 238 }; 239 240 timer0: timer@20038000 { 241 compatible = "snps,dw-apb-timer"; 242 reg = <0x20038000 0x100>; 243 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; 245 clock-names = "timer", "pclk"; 246 }; 247 248 timer1: timer@2003a000 { 249 compatible = "snps,dw-apb-timer"; 250 reg = <0x2003a000 0x100>; 251 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>; 253 clock-names = "timer", "pclk"; 254 }; 255 256 tsadc: tsadc@20060000 { 257 compatible = "rockchip,rk3066-tsadc"; 258 reg = <0x20060000 0x100>; 259 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 260 clock-names = "saradc", "apb_pclk"; 261 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 262 #io-channel-cells = <1>; 263 resets = <&cru SRST_TSADC>; 264 reset-names = "saradc-apb"; 265 status = "disabled"; 266 }; 267 268 pinctrl: pinctrl { 269 compatible = "rockchip,rk3066a-pinctrl"; 270 rockchip,grf = <&grf>; 271 #address-cells = <1>; 272 #size-cells = <1>; 273 ranges; 274 275 gpio0: gpio@20034000 { 276 compatible = "rockchip,gpio-bank"; 277 reg = <0x20034000 0x100>; 278 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&cru PCLK_GPIO0>; 280 281 gpio-controller; 282 #gpio-cells = <2>; 283 284 interrupt-controller; 285 #interrupt-cells = <2>; 286 }; 287 288 gpio1: gpio@2003c000 { 289 compatible = "rockchip,gpio-bank"; 290 reg = <0x2003c000 0x100>; 291 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 292 clocks = <&cru PCLK_GPIO1>; 293 294 gpio-controller; 295 #gpio-cells = <2>; 296 297 interrupt-controller; 298 #interrupt-cells = <2>; 299 }; 300 301 gpio2: gpio@2003e000 { 302 compatible = "rockchip,gpio-bank"; 303 reg = <0x2003e000 0x100>; 304 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&cru PCLK_GPIO2>; 306 307 gpio-controller; 308 #gpio-cells = <2>; 309 310 interrupt-controller; 311 #interrupt-cells = <2>; 312 }; 313 314 gpio3: gpio@20080000 { 315 compatible = "rockchip,gpio-bank"; 316 reg = <0x20080000 0x100>; 317 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&cru PCLK_GPIO3>; 319 320 gpio-controller; 321 #gpio-cells = <2>; 322 323 interrupt-controller; 324 #interrupt-cells = <2>; 325 }; 326 327 gpio4: gpio@20084000 { 328 compatible = "rockchip,gpio-bank"; 329 reg = <0x20084000 0x100>; 330 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&cru PCLK_GPIO4>; 332 333 gpio-controller; 334 #gpio-cells = <2>; 335 336 interrupt-controller; 337 #interrupt-cells = <2>; 338 }; 339 340 gpio6: gpio@2000a000 { 341 compatible = "rockchip,gpio-bank"; 342 reg = <0x2000a000 0x100>; 343 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&cru PCLK_GPIO6>; 345 346 gpio-controller; 347 #gpio-cells = <2>; 348 349 interrupt-controller; 350 #interrupt-cells = <2>; 351 }; 352 353 pcfg_pull_default: pcfg-pull-default { 354 bias-pull-pin-default; 355 }; 356 357 pcfg_pull_none: pcfg-pull-none { 358 bias-disable; 359 }; 360 361 emac { 362 emac_xfer: emac-xfer { 363 rockchip,pins = <1 RK_PC0 2 &pcfg_pull_none>, /* mac_clk */ 364 <1 RK_PC1 2 &pcfg_pull_none>, /* tx_en */ 365 <1 RK_PC2 2 &pcfg_pull_none>, /* txd1 */ 366 <1 RK_PC3 2 &pcfg_pull_none>, /* txd0 */ 367 <1 RK_PC4 2 &pcfg_pull_none>, /* rx_err */ 368 <1 RK_PC5 2 &pcfg_pull_none>, /* crs_dvalid */ 369 <1 RK_PC6 2 &pcfg_pull_none>, /* rxd1 */ 370 <1 RK_PC7 2 &pcfg_pull_none>; /* rxd0 */ 371 }; 372 373 emac_mdio: emac-mdio { 374 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, /* mac_md */ 375 <1 RK_PD1 2 &pcfg_pull_none>; /* mac_mdclk */ 376 }; 377 }; 378 379 emmc { 380 emmc_clk: emmc-clk { 381 rockchip,pins = <3 RK_PD7 2 &pcfg_pull_default>; 382 }; 383 384 emmc_cmd: emmc-cmd { 385 rockchip,pins = <4 RK_PB1 2 &pcfg_pull_default>; 386 }; 387 388 emmc_rst: emmc-rst { 389 rockchip,pins = <4 RK_PB2 2 &pcfg_pull_default>; 390 }; 391 392 /* 393 * The data pins are shared between nandc and emmc and 394 * not accessible through pinctrl. Also they should've 395 * been already set correctly by firmware, as 396 * flash/emmc is the boot-device. 397 */ 398 }; 399 400 hdmi { 401 hdmi_hpd: hdmi-hpd { 402 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>; 403 }; 404 405 hdmii2c_xfer: hdmii2c-xfer { 406 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>, 407 <0 RK_PA2 1 &pcfg_pull_none>; 408 }; 409 }; 410 411 i2c0 { 412 i2c0_xfer: i2c0-xfer { 413 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_none>, 414 <2 RK_PD5 1 &pcfg_pull_none>; 415 }; 416 }; 417 418 i2c1 { 419 i2c1_xfer: i2c1-xfer { 420 rockchip,pins = <2 RK_PD6 1 &pcfg_pull_none>, 421 <2 RK_PD7 1 &pcfg_pull_none>; 422 }; 423 }; 424 425 i2c2 { 426 i2c2_xfer: i2c2-xfer { 427 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none>, 428 <3 RK_PA1 1 &pcfg_pull_none>; 429 }; 430 }; 431 432 i2c3 { 433 i2c3_xfer: i2c3-xfer { 434 rockchip,pins = <3 RK_PA2 2 &pcfg_pull_none>, 435 <3 RK_PA3 2 &pcfg_pull_none>; 436 }; 437 }; 438 439 i2c4 { 440 i2c4_xfer: i2c4-xfer { 441 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>, 442 <3 RK_PA5 1 &pcfg_pull_none>; 443 }; 444 }; 445 446 pwm0 { 447 pwm0_out: pwm0-out { 448 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 449 }; 450 }; 451 452 pwm1 { 453 pwm1_out: pwm1-out { 454 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>; 455 }; 456 }; 457 458 pwm2 { 459 pwm2_out: pwm2-out { 460 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; 461 }; 462 }; 463 464 pwm3 { 465 pwm3_out: pwm3-out { 466 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>; 467 }; 468 }; 469 470 spi0 { 471 spi0_clk: spi0-clk { 472 rockchip,pins = <1 RK_PA5 2 &pcfg_pull_default>; 473 }; 474 spi0_cs0: spi0-cs0 { 475 rockchip,pins = <1 RK_PA4 2 &pcfg_pull_default>; 476 }; 477 spi0_tx: spi0-tx { 478 rockchip,pins = <1 RK_PA7 2 &pcfg_pull_default>; 479 }; 480 spi0_rx: spi0-rx { 481 rockchip,pins = <1 RK_PA6 2 &pcfg_pull_default>; 482 }; 483 spi0_cs1: spi0-cs1 { 484 rockchip,pins = <4 RK_PB7 1 &pcfg_pull_default>; 485 }; 486 }; 487 488 spi1 { 489 spi1_clk: spi1-clk { 490 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_default>; 491 }; 492 spi1_cs0: spi1-cs0 { 493 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_default>; 494 }; 495 spi1_rx: spi1-rx { 496 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_default>; 497 }; 498 spi1_tx: spi1-tx { 499 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_default>; 500 }; 501 spi1_cs1: spi1-cs1 { 502 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_default>; 503 }; 504 }; 505 506 uart0 { 507 uart0_xfer: uart0-xfer { 508 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>, 509 <1 RK_PA1 1 &pcfg_pull_default>; 510 }; 511 512 uart0_cts: uart0-cts { 513 rockchip,pins = <1 RK_PA2 1 &pcfg_pull_default>; 514 }; 515 516 uart0_rts: uart0-rts { 517 rockchip,pins = <1 RK_PA3 1 &pcfg_pull_default>; 518 }; 519 }; 520 521 uart1 { 522 uart1_xfer: uart1-xfer { 523 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>, 524 <1 RK_PA5 1 &pcfg_pull_default>; 525 }; 526 527 uart1_cts: uart1-cts { 528 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_default>; 529 }; 530 531 uart1_rts: uart1-rts { 532 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; 533 }; 534 }; 535 536 uart2 { 537 uart2_xfer: uart2-xfer { 538 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>, 539 <1 RK_PB1 1 &pcfg_pull_default>; 540 }; 541 /* no rts / cts for uart2 */ 542 }; 543 544 uart3 { 545 uart3_xfer: uart3-xfer { 546 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>, 547 <3 RK_PD4 1 &pcfg_pull_default>; 548 }; 549 550 uart3_cts: uart3-cts { 551 rockchip,pins = <3 RK_PD5 1 &pcfg_pull_default>; 552 }; 553 554 uart3_rts: uart3-rts { 555 rockchip,pins = <3 RK_PD6 1 &pcfg_pull_default>; 556 }; 557 }; 558 559 sd0 { 560 sd0_clk: sd0-clk { 561 rockchip,pins = <3 RK_PB0 1 &pcfg_pull_default>; 562 }; 563 564 sd0_cmd: sd0-cmd { 565 rockchip,pins = <3 RK_PB1 1 &pcfg_pull_default>; 566 }; 567 568 sd0_cd: sd0-cd { 569 rockchip,pins = <3 RK_PB6 1 &pcfg_pull_default>; 570 }; 571 572 sd0_wp: sd0-wp { 573 rockchip,pins = <3 RK_PB7 1 &pcfg_pull_default>; 574 }; 575 576 sd0_bus1: sd0-bus-width1 { 577 rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>; 578 }; 579 580 sd0_bus4: sd0-bus-width4 { 581 rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>, 582 <3 RK_PB3 1 &pcfg_pull_default>, 583 <3 RK_PB4 1 &pcfg_pull_default>, 584 <3 RK_PB5 1 &pcfg_pull_default>; 585 }; 586 }; 587 588 sd1 { 589 sd1_clk: sd1-clk { 590 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_default>; 591 }; 592 593 sd1_cmd: sd1-cmd { 594 rockchip,pins = <3 RK_PC0 1 &pcfg_pull_default>; 595 }; 596 597 sd1_cd: sd1-cd { 598 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_default>; 599 }; 600 601 sd1_wp: sd1-wp { 602 rockchip,pins = <3 RK_PC7 1 &pcfg_pull_default>; 603 }; 604 605 sd1_bus1: sd1-bus-width1 { 606 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>; 607 }; 608 609 sd1_bus4: sd1-bus-width4 { 610 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>, 611 <3 RK_PC2 1 &pcfg_pull_default>, 612 <3 RK_PC3 1 &pcfg_pull_default>, 613 <3 RK_PC4 1 &pcfg_pull_default>; 614 }; 615 }; 616 617 i2s0 { 618 i2s0_bus: i2s0-bus { 619 rockchip,pins = <0 RK_PA7 1 &pcfg_pull_default>, 620 <0 RK_PB0 1 &pcfg_pull_default>, 621 <0 RK_PB1 1 &pcfg_pull_default>, 622 <0 RK_PB2 1 &pcfg_pull_default>, 623 <0 RK_PB3 1 &pcfg_pull_default>, 624 <0 RK_PB4 1 &pcfg_pull_default>, 625 <0 RK_PB5 1 &pcfg_pull_default>, 626 <0 RK_PB6 1 &pcfg_pull_default>, 627 <0 RK_PB7 1 &pcfg_pull_default>; 628 }; 629 }; 630 631 i2s1 { 632 i2s1_bus: i2s1-bus { 633 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>, 634 <0 RK_PC1 1 &pcfg_pull_default>, 635 <0 RK_PC2 1 &pcfg_pull_default>, 636 <0 RK_PC3 1 &pcfg_pull_default>, 637 <0 RK_PC4 1 &pcfg_pull_default>, 638 <0 RK_PC5 1 &pcfg_pull_default>; 639 }; 640 }; 641 642 i2s2 { 643 i2s2_bus: i2s2-bus { 644 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_default>, 645 <0 RK_PD1 1 &pcfg_pull_default>, 646 <0 RK_PD2 1 &pcfg_pull_default>, 647 <0 RK_PD3 1 &pcfg_pull_default>, 648 <0 RK_PD4 1 &pcfg_pull_default>, 649 <0 RK_PD5 1 &pcfg_pull_default>; 650 }; 651 }; 652 }; 653}; 654 655&gpu { 656 compatible = "rockchip,rk3066-mali", "arm,mali-400"; 657 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 664 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 667 interrupt-names = "gp", 668 "gpmmu", 669 "pp0", 670 "ppmmu0", 671 "pp1", 672 "ppmmu1", 673 "pp2", 674 "ppmmu2", 675 "pp3", 676 "ppmmu3"; 677 power-domains = <&power RK3066_PD_GPU>; 678}; 679 680&grf { 681 compatible = "rockchip,rk3066-grf", "syscon", "simple-mfd"; 682 683 usbphy: usbphy { 684 compatible = "rockchip,rk3066a-usb-phy"; 685 #address-cells = <1>; 686 #size-cells = <0>; 687 status = "disabled"; 688 689 usbphy0: usb-phy@17c { 690 reg = <0x17c>; 691 clocks = <&cru SCLK_OTGPHY0>; 692 clock-names = "phyclk"; 693 #clock-cells = <0>; 694 #phy-cells = <0>; 695 }; 696 697 usbphy1: usb-phy@188 { 698 reg = <0x188>; 699 clocks = <&cru SCLK_OTGPHY1>; 700 clock-names = "phyclk"; 701 #clock-cells = <0>; 702 #phy-cells = <0>; 703 }; 704 }; 705}; 706 707&i2c0 { 708 pinctrl-names = "default"; 709 pinctrl-0 = <&i2c0_xfer>; 710}; 711 712&i2c1 { 713 pinctrl-names = "default"; 714 pinctrl-0 = <&i2c1_xfer>; 715}; 716 717&i2c2 { 718 pinctrl-names = "default"; 719 pinctrl-0 = <&i2c2_xfer>; 720}; 721 722&i2c3 { 723 pinctrl-names = "default"; 724 pinctrl-0 = <&i2c3_xfer>; 725}; 726 727&i2c4 { 728 pinctrl-names = "default"; 729 pinctrl-0 = <&i2c4_xfer>; 730}; 731 732&mmc0 { 733 clock-frequency = <50000000>; 734 dmas = <&dmac2 1>; 735 dma-names = "rx-tx"; 736 max-frequency = <50000000>; 737 pinctrl-names = "default"; 738 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; 739}; 740 741&mmc1 { 742 dmas = <&dmac2 3>; 743 dma-names = "rx-tx"; 744 pinctrl-names = "default"; 745 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; 746}; 747 748&emmc { 749 dmas = <&dmac2 4>; 750 dma-names = "rx-tx"; 751}; 752 753&pmu { 754 power: power-controller { 755 compatible = "rockchip,rk3066-power-controller"; 756 #power-domain-cells = <1>; 757 #address-cells = <1>; 758 #size-cells = <0>; 759 760 power-domain@RK3066_PD_VIO { 761 reg = <RK3066_PD_VIO>; 762 clocks = <&cru ACLK_LCDC0>, 763 <&cru ACLK_LCDC1>, 764 <&cru DCLK_LCDC0>, 765 <&cru DCLK_LCDC1>, 766 <&cru HCLK_LCDC0>, 767 <&cru HCLK_LCDC1>, 768 <&cru SCLK_CIF1>, 769 <&cru ACLK_CIF1>, 770 <&cru HCLK_CIF1>, 771 <&cru SCLK_CIF0>, 772 <&cru ACLK_CIF0>, 773 <&cru HCLK_CIF0>, 774 <&cru HCLK_HDMI>, 775 <&cru ACLK_IPP>, 776 <&cru HCLK_IPP>, 777 <&cru ACLK_RGA>, 778 <&cru HCLK_RGA>; 779 pm_qos = <&qos_lcdc0>, 780 <&qos_lcdc1>, 781 <&qos_cif0>, 782 <&qos_cif1>, 783 <&qos_ipp>, 784 <&qos_rga>; 785 #power-domain-cells = <0>; 786 }; 787 788 power-domain@RK3066_PD_VIDEO { 789 reg = <RK3066_PD_VIDEO>; 790 clocks = <&cru ACLK_VDPU>, 791 <&cru ACLK_VEPU>, 792 <&cru HCLK_VDPU>, 793 <&cru HCLK_VEPU>; 794 pm_qos = <&qos_vpu>; 795 #power-domain-cells = <0>; 796 }; 797 798 power-domain@RK3066_PD_GPU { 799 reg = <RK3066_PD_GPU>; 800 clocks = <&cru ACLK_GPU>; 801 pm_qos = <&qos_gpu>; 802 #power-domain-cells = <0>; 803 }; 804 }; 805}; 806 807&pwm0 { 808 pinctrl-names = "default"; 809 pinctrl-0 = <&pwm0_out>; 810}; 811 812&pwm1 { 813 pinctrl-names = "default"; 814 pinctrl-0 = <&pwm1_out>; 815}; 816 817&pwm2 { 818 pinctrl-names = "default"; 819 pinctrl-0 = <&pwm2_out>; 820}; 821 822&pwm3 { 823 pinctrl-names = "default"; 824 pinctrl-0 = <&pwm3_out>; 825}; 826 827&spi0 { 828 pinctrl-names = "default"; 829 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 830}; 831 832&spi1 { 833 pinctrl-names = "default"; 834 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 835}; 836 837&uart0 { 838 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; 839 dmas = <&dmac1_s 0>, <&dmac1_s 1>; 840 dma-names = "tx", "rx"; 841 pinctrl-names = "default"; 842 pinctrl-0 = <&uart0_xfer>; 843}; 844 845&uart1 { 846 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; 847 dmas = <&dmac1_s 2>, <&dmac1_s 3>; 848 dma-names = "tx", "rx"; 849 pinctrl-names = "default"; 850 pinctrl-0 = <&uart1_xfer>; 851}; 852 853&uart2 { 854 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; 855 dmas = <&dmac2 6>, <&dmac2 7>; 856 dma-names = "tx", "rx"; 857 pinctrl-names = "default"; 858 pinctrl-0 = <&uart2_xfer>; 859}; 860 861&uart3 { 862 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; 863 dmas = <&dmac2 8>, <&dmac2 9>; 864 dma-names = "tx", "rx"; 865 pinctrl-names = "default"; 866 pinctrl-0 = <&uart3_xfer>; 867}; 868 869&vpu { 870 power-domains = <&power RK3066_PD_VIDEO>; 871}; 872 873&wdt { 874 compatible = "rockchip,rk3066-wdt", "snps,dw-wdt"; 875}; 876 877&emac { 878 compatible = "rockchip,rk3066-emac"; 879}; 880